Updating LUT synthesis code.

src/aig/gia/giaDup.c

@@ -3460,6 +3460,8 @@ Gia_Man_t * Gia_ManDupCones( Gia_Man_t * p, int * pPos, int nPos, int fTrimPis )
     // create PIs
     if ( fTrimPis )
     {
+        Gia_ManForEachPi( p, pObj, i )
+            pObj->Value = ~0;
         Vec_PtrForEachEntry( Gia_Obj_t *, vLeaves, pObj, i )
             pObj->Value = Gia_ManAppendCi( pNew );
     }

src/base/abc/abcNtk.c

@@ -1286,6 +1286,7 @@ void Abc_NtkDelete( Abc_Ntk_t * pNtk )
     Abc_Obj_t * pObj;
     void * pAttrMan;
     int TotalMemory, i;
+    int fWarning = 0;
 //    int LargePiece = (4 << ABC_NUM_STEPS);
     if ( pNtk == NULL )
         return;
@@ -1310,9 +1311,11 @@ void Abc_NtkDelete( Abc_Ntk_t * pNtk )
 //            ABC_FREE( pObj->vFanouts.pArray );
         // these flags should be always zero
         // if this is not true, something is wrong somewhere
-        assert( pObj->fMarkA == 0 );
-        assert( pObj->fMarkB == 0 );
-        assert( pObj->fMarkC == 0 );
+//        assert( pObj->fMarkA == 0 );
+//        assert( pObj->fMarkB == 0 );
+//        assert( pObj->fMarkC == 0 );
+        if ( !fWarning && (pObj->fMarkA || pObj->fMarkB || pObj->fMarkC) )
+            { printf( "Flags A, B, or C are not zero.\n" ), fWarning = 1; }
     }
     // free the nodes
     if ( pNtk->pMmStep == NULL )

src/base/abci/abcLut.c

@@ -783,6 +783,164 @@ int Abc_NodeDecomposeStep( Abc_ManScl_t * p )
     return 1;
 }
 
+/**Function*************************************************************
+
+  Synopsis    [Performs specialized mapping.]
+
+  Description []
+               
+  SideEffects []
+
+  SeeAlso     []
+
+***********************************************************************/
+static word s__Truths6[6] = {
+    ABC_CONST(0xAAAAAAAAAAAAAAAA),
+    ABC_CONST(0xCCCCCCCCCCCCCCCC),
+    ABC_CONST(0xF0F0F0F0F0F0F0F0),
+    ABC_CONST(0xFF00FF00FF00FF00),
+    ABC_CONST(0xFFFF0000FFFF0000),
+    ABC_CONST(0xFFFFFFFF00000000)
+};
+word Abc_ObjComputeTruth( Abc_Obj_t * pObj, Vec_Int_t * vSupp )
+{
+    int Index; word t0, t1, tc;
+    assert( Vec_IntSize(vSupp) <= 6 );
+    if ( (Index = Vec_IntFind(vSupp, Abc_ObjId(pObj))) >= 0 )
+        return s__Truths6[Index];
+    assert( Abc_ObjIsNode(pObj) );
+    if ( Abc_ObjFaninNum(pObj) == 0 )
+        return Abc_NodeIsConst0(pObj) ? (word)0 : ~(word)0;
+    assert( Abc_ObjFaninNum(pObj) == 3 );
+    t0 = Abc_ObjComputeTruth( Abc_ObjFanin(pObj, 2), vSupp );
+    t1 = Abc_ObjComputeTruth( Abc_ObjFanin(pObj, 1), vSupp );
+    tc = Abc_ObjComputeTruth( Abc_ObjFanin(pObj, 0), vSupp );
+    return (tc & t1) | (~tc & t0);
+}
+Abc_Obj_t * Abc_NtkSpecialMap_rec( Abc_Ntk_t * pNew, Abc_Obj_t * pObj, Vec_Wec_t * vSupps, Vec_Int_t * vCover )
+{
+    if ( pObj->pCopy )
+        return pObj->pCopy;
+    if ( Abc_ObjFaninNum(pObj) == 0 )
+        return NULL;
+    assert( Abc_ObjFaninNum(pObj) == 3 );
+    if ( pObj->fMarkA || pObj->fMarkB )
+    {
+        Abc_Obj_t * pFan0 = Abc_NtkSpecialMap_rec( pNew, Abc_ObjFanin(pObj, 2), vSupps, vCover );
+        Abc_Obj_t * pFan1 = Abc_NtkSpecialMap_rec( pNew, Abc_ObjFanin(pObj, 1), vSupps, vCover );
+        Abc_Obj_t * pFanC = Abc_NtkSpecialMap_rec( pNew, Abc_ObjFanin(pObj, 0), vSupps, vCover );
+        if ( pFan0 == NULL )
+            pFan0 = Abc_NodeIsConst0(Abc_ObjFanin(pObj, 2)) ? Abc_NtkCreateNodeConst0(pNew) : Abc_NtkCreateNodeConst1(pNew);
+        if ( pFan1 == NULL )
+            pFan1 = Abc_NodeIsConst0(Abc_ObjFanin(pObj, 1)) ? Abc_NtkCreateNodeConst0(pNew) : Abc_NtkCreateNodeConst1(pNew);
+        pObj->pCopy = Abc_NtkCreateNodeMux( pNew, pFanC, pFan1, pFan0 );
+        pObj->pCopy->fMarkA = pObj->fMarkA;
+        pObj->pCopy->fMarkB = pObj->fMarkB;
+    }
+    else
+    {
+        Abc_Obj_t * pTemp; int i; word Truth;
+        Vec_Int_t * vSupp = Vec_WecEntry( vSupps, Abc_ObjId(pObj) );
+        Abc_NtkForEachObjVec( vSupp, pObj->pNtk, pTemp, i )
+            Abc_NtkSpecialMap_rec( pNew, pTemp, vSupps, vCover );
+        pObj->pCopy = Abc_NtkCreateNode( pNew );   
+        Abc_NtkForEachObjVec( vSupp, pObj->pNtk, pTemp, i )
+            Abc_ObjAddFanin( pObj->pCopy, pTemp->pCopy );
+        Truth = Abc_ObjComputeTruth( pObj, vSupp );
+        pObj->pCopy->pData = Abc_SopCreateFromTruthIsop( (Mem_Flex_t *)pNew->pManFunc, Vec_IntSize(vSupp), &Truth, vCover );
+        assert( Abc_SopGetVarNum((char *)pObj->pCopy->pData) == Vec_IntSize(vSupp) );
+    }
+    return pObj->pCopy;
+}
+Abc_Ntk_t * Abc_NtkSpecialMapping( Abc_Ntk_t * pNtk, int fVerbose )
+{
+    Abc_Ntk_t * pNtkNew;
+    Vec_Int_t * vCover = Vec_IntAlloc( 1 << 16 );
+    Vec_Wec_t * vSupps = Vec_WecStart( Abc_NtkObjNumMax(pNtk) );
+    Abc_Obj_t * pObj, * pFan0, * pFan1, * pFanC; int i, Count[2] = {0};
+    Abc_NtkForEachCi( pNtk, pObj, i )
+        Vec_IntPush( Vec_WecEntry(vSupps, i), i );
+    Abc_NtkForEachNode( pNtk, pObj, i )
+    {
+        Vec_Int_t * vSupp = Vec_WecEntry(vSupps, i);
+        if ( Abc_ObjFaninNum(pObj) == 0 )
+            continue;
+        assert( Abc_ObjFaninNum(pObj) == 3 );
+        pFan0 = Abc_ObjFanin( pObj, 2 );
+        pFan1 = Abc_ObjFanin( pObj, 1 );
+        pFanC = Abc_ObjFanin0( pObj );
+        assert( Abc_ObjIsCi(pFanC) );
+        if ( pFan0->fMarkA && pFan1->fMarkA )
+        {
+            pObj->fMarkB = 1;
+            Vec_IntPush( vSupp, Abc_ObjId(pObj) );
+            continue;
+        }
+        Vec_IntTwoMerge2( Vec_WecEntry(vSupps, Abc_ObjId(pFan0)), Vec_WecEntry(vSupps, Abc_ObjId(pFan1)), vSupp );
+        assert( Vec_IntFind(vSupp, Abc_ObjId(pFanC)) == -1 );
+        Vec_IntPushOrder( vSupp, Abc_ObjId(pFanC) );
+        if ( Vec_IntSize(vSupp) <= 6 )
+            continue;
+        Vec_IntClear( vSupp );
+        if ( !pFan0->fMarkA && !pFan1->fMarkA )
+        {
+            pObj->fMarkA = 1;
+            Vec_IntPush( vSupp, Abc_ObjId(pObj) );
+        }
+        else
+        {
+            Vec_IntPushOrder( vSupp, Abc_ObjId(pFan0) );
+            Vec_IntPushOrder( vSupp, Abc_ObjId(pFan1) );
+            Vec_IntPushOrder( vSupp, Abc_ObjId(pFanC) );
+        }
+    }
+
+    if ( fVerbose )
+    Abc_NtkForEachNode( pNtk, pObj, i )
+    {
+        printf( "Node %4d : ", i );
+        if ( pObj->fMarkA )
+            printf( " MarkA  " );
+        else
+            printf( "        " );
+        if ( pObj->fMarkB )
+            printf( " MarkB  " );
+        else
+            printf( "        " );
+        Vec_IntPrint( Vec_WecEntry(vSupps, i) );
+    }
+
+    Abc_NtkCleanCopy( pNtk );
+    pNtkNew = Abc_NtkStartFrom( pNtk, ABC_NTK_LOGIC, ABC_FUNC_SOP );
+    Abc_NtkForEachCo( pNtk, pObj, i )
+        if ( Abc_ObjFaninNum(Abc_ObjFanin0(pObj)) == 0 )
+            Abc_ObjFanin0(pObj)->pCopy = Abc_NodeIsConst0(Abc_ObjFanin0(pObj)) ? Abc_NtkCreateNodeConst0(pNtkNew) : Abc_NtkCreateNodeConst1(pNtkNew);
+        else
+            Abc_NtkSpecialMap_rec( pNtkNew, Abc_ObjFanin0(pObj), vSupps, vCover );
+    Abc_NtkFinalize( pNtk, pNtkNew );
+    Abc_NtkCleanMarkAB( pNtk );
+    Vec_WecFree( vSupps );
+    Vec_IntFree( vCover );
+
+    Abc_NtkForEachNode( pNtkNew, pObj, i )
+    {
+        Count[0] += pObj->fMarkA,
+        Count[1] += pObj->fMarkB;
+        pObj->fPersist = pObj->fMarkA | pObj->fMarkB;
+        pObj->fMarkA = pObj->fMarkB = 0;
+    }
+    //printf( "Total = %3d.  Nodes = %3d. MarkA = %3d. MarkB = %3d.\n", Abc_NtkNodeNum(pNtkNew), 
+    //    Abc_NtkNodeNum(pNtkNew) - Count[0] - Count[1], Count[0], Count[1] );
+
+    if ( !Abc_NtkCheck( pNtkNew ) )
+    {
+        printf( "Abc_NtkSpecialMapping: The network check has failed.\n" );
+        Abc_NtkDelete( pNtkNew );
+        return NULL;
+    }
+    return pNtkNew;
+}
+
 ////////////////////////////////////////////////////////////////////////
 ///                       END OF FILE                                ///
 ////////////////////////////////////////////////////////////////////////

src/base/abci/abcNtbdd.c

@@ -274,7 +274,7 @@ int Abc_NtkBddToMuxesPerformGlo( Abc_Ntk_t * pNtk, Abc_Ntk_t * pNtkNew, int Limi
     Abc_Obj_t * pObj, * pObjNew; int i;
     st__table * tBdd2Node;
     assert( Abc_NtkIsStrash(pNtk) );
-    dd = (DdManager *)Abc_NtkBuildGlobalBdds( pNtk, Limit, 1, 1, fReorder, 0 );
+    dd = (DdManager *)Abc_NtkBuildGlobalBdds( pNtk, Limit, 1, fReorder, 0, 0 );
     if ( dd == NULL )
     {
         printf( "Construction of global BDDs has failed.\n" );

src/base/io/io.c

@@ -2982,13 +2982,13 @@ usage:
 ***********************************************************************/
 int IoCommandWriteVerilog( Abc_Frame_t * pAbc, int argc, char **argv )
 {
-    extern void Io_WriteVerilogLut( Abc_Ntk_t * pNtk, char * pFileName, int nLutSize );
+    extern void Io_WriteVerilogLut( Abc_Ntk_t * pNtk, char * pFileName, int nLutSize, int fFixed, int fNoModules );
     char * pFileName;
-    int c, fOnlyAnds = 0;
+    int c, fFixed = 0, fOnlyAnds = 0, fNoModules = 0;
     int nLutSize = -1;
 
     Extra_UtilGetoptReset();
-    while ( ( c = Extra_UtilGetopt( argc, argv, "Kah" ) ) != EOF )
+    while ( ( c = Extra_UtilGetopt( argc, argv, "Kfamh" ) ) != EOF )
     {
         switch ( c )
         {
@@ -3003,9 +3003,15 @@ int IoCommandWriteVerilog( Abc_Frame_t * pAbc, int argc, char **argv )
                 if ( nLutSize < 2 || nLutSize > 6 )
                     goto usage;
                 break;
+            case 'f':
+                fFixed ^= 1;
+                break;
             case 'a':
                 fOnlyAnds ^= 1;
                 break;
+            case 'm':
+                fNoModules ^= 1;
+                break;
             case 'h':
                 goto usage;
             default:
@@ -3019,6 +3025,8 @@ int IoCommandWriteVerilog( Abc_Frame_t * pAbc, int argc, char **argv )
     }
     if ( argc != globalUtilOptind + 1 )
         goto usage;
+    if ( fFixed )
+        nLutSize = 6;
     // get the output file name
     pFileName = argv[globalUtilOptind];
     // call the corresponding file writer
@@ -3031,16 +3039,18 @@ int IoCommandWriteVerilog( Abc_Frame_t * pAbc, int argc, char **argv )
         Abc_NtkDelete( pNtkTemp );
     }
     else if ( nLutSize >= 2 && nLutSize <= 6 )
-        Io_WriteVerilogLut( pAbc->pNtkCur, pFileName, nLutSize );
+        Io_WriteVerilogLut( pAbc->pNtkCur, pFileName, nLutSize, fFixed, fNoModules );
     else
         Io_Write( pAbc->pNtkCur, pFileName, IO_FILE_VERILOG );
     return 0;
 
 usage:
-    fprintf( pAbc->Err, "usage: write_verilog [-K num] [-ah] <file>\n" );
+    fprintf( pAbc->Err, "usage: write_verilog [-K num] [-famh] <file>\n" );
     fprintf( pAbc->Err, "\t         writes the current network in Verilog format\n" );
     fprintf( pAbc->Err, "\t-K num : write the network using instances of K-LUTs (2 <= K <= 6) [default = not used]\n" );
+    fprintf( pAbc->Err, "\t-f     : toggle using fixed format [default = %s]\n", fFixed? "yes":"no" );
     fprintf( pAbc->Err, "\t-a     : toggle writing expressions with only ANDs (without XORs and MUXes) [default = %s]\n", fOnlyAnds? "yes":"no" );
+    fprintf( pAbc->Err, "\t-m     : toggle writing additional modules [default = %s]\n", !fNoModules? "yes":"no" );
     fprintf( pAbc->Err, "\t-h     : print the help massage\n" );
     fprintf( pAbc->Err, "\tfile   : the name of the file to write\n" );
     return 1;

src/base/io/ioWriteVerilog.c

@@ -639,10 +639,8 @@ int Io_WriteVerilogWiresCount( Abc_Ntk_t * pNtk )
 char * Io_WriteVerilogGetName( char * pName )
 {
     static char Buffer[500];
-    int Length, i;
-    Length = strlen(pName);
-    // consider the case of a signal having name "0" or "1"
-    if ( !(Length == 1 && (pName[0] == '0' || pName[0] == '1')) )
+    int i, Length = strlen(pName);
+    if ( pName[0] < '0' || pName[0] > '9' )
     {
         for ( i = 0; i < Length; i++ )
             if ( !((pName[i] >= 'a' && pName[i] <= 'z') || 
@@ -679,7 +677,39 @@ void Io_WriteLutModule( FILE * pFile, int nLutSize )
     fprintf( pFile, "    assign out = TT[in];\n" );
     fprintf( pFile, "endmodule\n\n" );
 }
-void Io_WriteVerilogObjectsLut( FILE * pFile, Abc_Ntk_t * pNtk, int nLutSize )
+void Io_WriteFixedModules( FILE * pFile )
+{    
+    fprintf( pFile, "module LUT6 #( parameter INIT = 64\'h0000000000000000 ) (\n" );
+    fprintf( pFile, "    output O,\n" );
+    fprintf( pFile, "    input I0,\n" );
+    fprintf( pFile, "    input I1,\n" );
+    fprintf( pFile, "    input I2,\n" );
+    fprintf( pFile, "    input I3,\n" );
+    fprintf( pFile, "    input I4,\n" );
+    fprintf( pFile, "    input I5\n" );
+    fprintf( pFile, ");\n" );
+    fprintf( pFile, "    assign O = INIT[ {I5, I4, I3, I2, I1, I0} ];\n" );
+    fprintf( pFile, "endmodule\n\n" );
+
+    fprintf( pFile, "module MUXF7 (\n" );
+    fprintf( pFile, "    output O,\n" );
+    fprintf( pFile, "    input I0,\n" );
+    fprintf( pFile, "    input I1,\n" );
+    fprintf( pFile, "    input S\n" );
+    fprintf( pFile, ");\n" );
+    fprintf( pFile, "    assign O = S ? I1 : I0;\n" );
+    fprintf( pFile, "endmodule\n\n" );
+
+    fprintf( pFile, "module MUXF8 (\n" );
+    fprintf( pFile, "    output O,\n" );
+    fprintf( pFile, "    input I0,\n" );
+    fprintf( pFile, "    input I1,\n" );
+    fprintf( pFile, "    input S\n" );
+    fprintf( pFile, ");\n" );
+    fprintf( pFile, "    assign O = S ? I1 : I0;\n" );
+    fprintf( pFile, "endmodule\n\n" );
+}
+void Io_WriteVerilogObjectsLut( FILE * pFile, Abc_Ntk_t * pNtk, int nLutSize, int fFixed )
 {
     Abc_Ntk_t * pNtkBox;
     Abc_Obj_t * pObj, * pTerm;
@@ -719,6 +749,34 @@ void Io_WriteVerilogObjectsLut( FILE * pFile, Abc_Ntk_t * pNtk, int nLutSize )
     // write LUT instances
     nDigits = Abc_Base10Log( Abc_NtkNodeNum(pNtk) );
     Counter = 0;
+    if ( fFixed )
+    Abc_NtkForEachNode( pNtk, pObj, i )
+    {
+        if ( pObj->fPersist )
+        {
+            int One = Abc_ObjFanin0(Abc_ObjFanin(pObj, 1))->fPersist && Abc_ObjFanin0(Abc_ObjFanin(pObj, 2))->fPersist;
+            fprintf( pFile, "  MUXF%d                       ", 7+One );
+            fprintf( pFile, " mux_%0*d (", nDigits, Counter++ );
+            fprintf( pFile, " %*s", Length, Io_WriteVerilogGetName(Abc_ObjName(Abc_ObjFanout0(pObj))) );
+            for ( k = Abc_ObjFaninNum(pObj) - 1; k >= 0; k-- )
+                fprintf( pFile, ", %*s", Length, Io_WriteVerilogGetName(Abc_ObjName(Abc_ObjFanin(pObj, k))) );
+            fprintf( pFile, " );\n" );
+        }
+        else
+        {
+            word Truth = Abc_SopToTruth( (char *)pObj->pData, Abc_ObjFaninNum(pObj) );
+            fprintf( pFile, "  LUT6 #(64\'h" );
+            fprintf( pFile, "%08x%08x", (unsigned)(Truth >> 32), (unsigned)Truth );
+            fprintf( pFile, ") lut_%0*d (", nDigits, Counter++ );
+            fprintf( pFile, " %*s", Length, Io_WriteVerilogGetName(Abc_ObjName(Abc_ObjFanout0(pObj))) );
+            for ( k = 0; k < Abc_ObjFaninNum(pObj); k++ )
+                fprintf( pFile, ", %*s", Length, Io_WriteVerilogGetName(Abc_ObjName(Abc_ObjFanin(pObj, k))) );
+            for (      ; k < 6; k++ )
+                fprintf( pFile, ", %*s", Length, "1\'b0" );
+            fprintf( pFile, " );\n" );
+        }
+    }
+    else
     Abc_NtkForEachNode( pNtk, pObj, i )
     {
         word Truth = Abc_SopToTruth( (char *)pObj->pData, Abc_ObjFaninNum(pObj) );
@@ -735,7 +793,7 @@ void Io_WriteVerilogObjectsLut( FILE * pFile, Abc_Ntk_t * pNtk, int nLutSize )
         fprintf( pFile, "}, %*s );\n", Length, Io_WriteVerilogGetName(Abc_ObjName(Abc_ObjFanout0(pObj))) );
     }
 }
-void Io_WriteVerilogLutInt( FILE * pFile, Abc_Ntk_t * pNtk, int nLutSize )
+void Io_WriteVerilogLutInt( FILE * pFile, Abc_Ntk_t * pNtk, int nLutSize, int fFixed )
 {
     // write inputs and outputs
 //    fprintf( pFile, "module %s ( gclk,\n   ", Abc_NtkName(pNtk) );
@@ -786,7 +844,7 @@ void Io_WriteVerilogLutInt( FILE * pFile, Abc_Ntk_t * pNtk, int nLutSize )
             fprintf( pFile, ";\n\n" );
         }
         // write nodes
-        Io_WriteVerilogObjectsLut( pFile, pNtk, nLutSize );        
+        Io_WriteVerilogObjectsLut( pFile, pNtk, nLutSize, fFixed );        
         // write registers
         if ( Abc_NtkLatchNum(pNtk) > 0 )
         {
@@ -797,7 +855,7 @@ void Io_WriteVerilogLutInt( FILE * pFile, Abc_Ntk_t * pNtk, int nLutSize )
     // finalize the file
     fprintf( pFile, "\nendmodule\n\n" );
 } 
-void Io_WriteVerilogLut( Abc_Ntk_t * pNtk, char * pFileName, int nLutSize )
+void Io_WriteVerilogLut( Abc_Ntk_t * pNtk, char * pFileName, int nLutSize, int fFixed, int fNoModules )
 {
     FILE * pFile;
     Abc_Ntk_t * pNtkTemp;
@@ -827,11 +885,16 @@ void Io_WriteVerilogLut( Abc_Ntk_t * pNtk, char * pFileName, int nLutSize )
     // write the equations for the network
     fprintf( pFile, "// Benchmark \"%s\" written by ABC on %s\n", pNtk->pName, Extra_TimeStamp() );
     fprintf( pFile, "\n" );
-    Io_WriteLutModule( pFile, nLutSize );
-
+    if ( !fNoModules )
+    {
+        if ( fFixed )
+            Io_WriteFixedModules( pFile );
+        else
+            Io_WriteLutModule( pFile, nLutSize );
+    }
     pNtkTemp = Abc_NtkToNetlist( pNtk );
     Abc_NtkToSop( pNtkTemp, -1, ABC_INFINITY );
-    Io_WriteVerilogLutInt( pFile, pNtkTemp, nLutSize );
+    Io_WriteVerilogLutInt( pFile, pNtkTemp, nLutSize, fFixed );
     Abc_NtkDelete( pNtkTemp );
 
     fprintf( pFile, "\n" );