sswPart.c 13.8 KB
Newer Older
Alan Mishchenko committed
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
/**CFile****************************************************************

  FileName    [sswPart.c]

  SystemName  [ABC: Logic synthesis and verification system.]

  PackageName [Inductive prover with constraints.]

  Synopsis    [Partitioned signal correspondence.]

  Author      [Alan Mishchenko]
  
  Affiliation [UC Berkeley]

  Date        [Ver. 1.0. Started - September 1, 2008.]

  Revision    [$Id: sswPart.c,v 1.00 2008/09/01 00:00:00 alanmi Exp $]

***********************************************************************/

#include "sswInt.h"
22
#include "aig/ioa/ioa.h"
Alan Mishchenko committed
23 24
#include "aig/gia/giaAig.h"
#include "proof/cec/cec.h"
25

Alan Mishchenko committed
26 27 28 29 30 31 32 33 34 35
#ifdef ABC_USE_PTHREADS

#ifdef _WIN32
#include "../lib/pthread.h"
#else
#include <pthread.h>
#include <unistd.h>
#endif

#endif
36

Alan Mishchenko committed
37

Alan Mishchenko committed
38 39
ABC_NAMESPACE_IMPL_START

Alan Mishchenko committed
40 41 42 43 44 45 46 47 48 49
////////////////////////////////////////////////////////////////////////
///                        DECLARATIONS                              ///
////////////////////////////////////////////////////////////////////////

////////////////////////////////////////////////////////////////////////
///                     FUNCTION DEFINITIONS                         ///
////////////////////////////////////////////////////////////////////////

/**Function*************************************************************

Alan Mishchenko committed
50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184
  Synopsis    [Performing SAT sweeping for the array of AIGs.]

  Description []
               
  SideEffects []

  SeeAlso     []

***********************************************************************/
void Ssw_SignalCorrespondenceArray1( Vec_Ptr_t * vGias, Ssw_Pars_t * pPars )
{
    Gia_Man_t * pGia; int i;
    Cec_ParCor_t CorPars, * pCorPars = &CorPars;
    Cec_ManCorSetDefaultParams( pCorPars );
    pCorPars->nBTLimit  = pPars->nBTLimit;
    pCorPars->fVerbose  = pPars->fVerbose;
    pCorPars->fUseCSat  = 1; 
    Vec_PtrForEachEntry( Gia_Man_t *, vGias, pGia, i )
        if ( Gia_ManPiNum(pGia) > 0 )
            Cec_ManLSCorrespondenceClasses( pGia, pCorPars );
}

/**Function*************************************************************

  Synopsis    [Performing SAT sweeping for the array of AIGs.]

  Description []
               
  SideEffects []

  SeeAlso     []

***********************************************************************/
#ifndef ABC_USE_PTHREADS

void Ssw_SignalCorrespondenceArray( Vec_Ptr_t * vGias, Ssw_Pars_t * pPars )
{
    Ssw_SignalCorrespondenceArray1( vGias, pPars );
}

#else // pthreads are used


#define PAR_THR_MAX 100
typedef struct Par_ScorrThData_t_
{
    Cec_ParCor_t CorPars;
    Gia_Man_t *  p;
    int *        pMap;
    int          iThread;
    int          nTimeOut;
    int          fWorking;
} Par_ScorrThData_t;

void * Ssw_GiaWorkerThread( void * pArg )
{
    Par_ScorrThData_t * pThData = (Par_ScorrThData_t *)pArg;
    volatile int * pPlace = &pThData->fWorking;
    while ( 1 )
    {
        while ( *pPlace == 0 );
        assert( pThData->fWorking );
        if ( pThData->p == NULL )
        {
            pthread_exit( NULL );
            assert( 0 );
            return NULL;
        }
        Cec_ManLSCorrespondenceClasses( pThData->p, &pThData->CorPars );
        pThData->fWorking = 0;
    }
    assert( 0 );
    return NULL;
}

void Ssw_SignalCorrespondenceArray( Vec_Ptr_t * vGias, Ssw_Pars_t * pPars )
{
    //abctime clkTotal = Abc_Clock();
    Par_ScorrThData_t ThData[PAR_THR_MAX];
    pthread_t WorkerThread[PAR_THR_MAX];
    int i, status, nProcs = pPars->nProcs;
    Vec_Ptr_t * vStack;
    Cec_ParCor_t CorPars, * pCorPars = &CorPars;
    Cec_ManCorSetDefaultParams( pCorPars );
    if ( pPars->fVerbose )
        printf( "Running concurrent &scorr with %d processes.\n", nProcs );
    fflush( stdout );
    if ( pPars->nProcs < 2 )
        return Ssw_SignalCorrespondenceArray1( vGias, pPars );
    // subtract manager thread
    nProcs--;
    assert( nProcs >= 1 && nProcs <= PAR_THR_MAX );
    // start threads
    for ( i = 0; i < nProcs; i++ )
    {
        ThData[i].CorPars  = *pCorPars;
        ThData[i].iThread  = i;
        //ThData[i].nTimeOut = pPars->nTimeOut;
        ThData[i].fWorking = 0;
        status = pthread_create( WorkerThread + i, NULL, Ssw_GiaWorkerThread, (void *)(ThData + i) );  assert( status == 0 );
    }
    // look at the threads
    vStack = Vec_PtrDup( vGias );
    while ( Vec_PtrSize(vStack) > 0 )
    {
        for ( i = 0; i < nProcs; i++ )
        {
            if ( ThData[i].fWorking )
                continue;
            ThData[i].p = (Gia_Man_t*)Vec_PtrPop( vStack );
            ThData[i].fWorking = 1;   
            break;
        }
    }
    Vec_PtrFree( vStack );    
    // wait till threads finish
    for ( i = 0; i < nProcs; i++ )
        if ( ThData[i].fWorking )
            i = -1;
    // stop threads
    for ( i = 0; i < nProcs; i++ )
    {
        assert( !ThData[i].fWorking );
        // stop
        ThData[i].p = NULL;
        ThData[i].fWorking = 1;
    }

}

#endif // pthreads are used


/**Function*************************************************************

Alan Mishchenko committed
185
  Synopsis    [Performs partitioned sequential SAT sweeping.]
Alan Mishchenko committed
186 187 188 189 190 191 192 193 194 195

  Description []
               
  SideEffects []

  SeeAlso     []

***********************************************************************/
Aig_Man_t * Ssw_SignalCorrespondencePart( Aig_Man_t * pAig, Ssw_Pars_t * pPars )
{
Alan Mishchenko committed
196
    int fPrintParts = 1;
Alan Mishchenko committed
197 198 199 200 201 202 203
    char Buffer[100];
    Aig_Man_t * pTemp, * pNew;
    Vec_Ptr_t * vResult;
    Vec_Int_t * vPart;
    int * pMapBack;
    int i, nCountPis, nCountRegs;
    int nClasses, nPartSize, fVerbose;
204
    abctime clk = Abc_Clock();
205 206
    if ( pPars->fConstrs )
    {
207
        Abc_Print( 1, "Cannot use partitioned computation with constraints.\n" );
208 209
        return NULL;
    }
Alan Mishchenko committed
210 211
    // save parameters
    nPartSize = pPars->nPartSize; pPars->nPartSize = 0;
212
    fVerbose  = pPars->fVerbose;  pPars->fVerbose  = 0;
Alan Mishchenko committed
213 214 215 216 217
    // generate partitions
    if ( pAig->vClockDoms )
    {
        // divide large clock domains into separate partitions
        vResult = Vec_PtrAlloc( 100 );
218
        Vec_PtrForEachEntry( Vec_Int_t *, (Vec_Ptr_t *)pAig->vClockDoms, vPart, i )
Alan Mishchenko committed
219 220 221 222 223 224 225 226 227 228 229 230 231 232
        {
            if ( nPartSize && Vec_IntSize(vPart) > nPartSize )
                Aig_ManPartDivide( vResult, vPart, nPartSize, pPars->nOverSize );
            else
                Vec_PtrPush( vResult, Vec_IntDup(vPart) );
        }
    }
    else
        vResult = Aig_ManRegPartitionSimple( pAig, nPartSize, pPars->nOverSize );
//    vResult = Aig_ManPartitionSmartRegisters( pAig, nPartSize, 0 ); 
//    vResult = Aig_ManRegPartitionSmart( pAig, nPartSize );
    if ( fPrintParts )
    {
        // print partitions
233
        Abc_Print( 1, "Simple partitioning. %d partitions are saved:\n", Vec_PtrSize(vResult) );
234
        Vec_PtrForEachEntry( Vec_Int_t *, vResult, vPart, i )
Alan Mishchenko committed
235
        {
236
//            extern void Ioa_WriteAiger( Aig_Man_t * pMan, char * pFileName, int fWriteSymbols, int fCompact );
Alan Mishchenko committed
237 238 239
            sprintf( Buffer, "part%03d.aig", i );
            pTemp = Aig_ManRegCreatePart( pAig, vPart, &nCountPis, &nCountRegs, NULL );
            Ioa_WriteAiger( pTemp, Buffer, 0, 0 );
240
            Abc_Print( 1, "part%03d.aig : Reg = %4d. PI = %4d. (True = %4d. Regs = %4d.) And = %5d.\n",
241
                i, Vec_IntSize(vPart), Aig_ManCiNum(pTemp)-Vec_IntSize(vPart), nCountPis, nCountRegs, Aig_ManNodeNum(pTemp) );
Alan Mishchenko committed
242 243 244 245 246 247
            Aig_ManStop( pTemp );
        }
    }

    // perform SSW with partitions
    Aig_ManReprStart( pAig, Aig_ManObjNumMax(pAig) );
248
    Vec_PtrForEachEntry( Vec_Int_t *, vResult, vPart, i )
Alan Mishchenko committed
249 250 251 252 253 254 255
    {
        pTemp = Aig_ManRegCreatePart( pAig, vPart, &nCountPis, &nCountRegs, &pMapBack );
        Aig_ManSetRegNum( pTemp, pTemp->nRegs );
        // create the projection of 1-hot registers
        if ( pAig->vOnehots )
            pTemp->vOnehots = Aig_ManRegProjectOnehots( pAig, pTemp, pAig->vOnehots, fVerbose );
        // run SSW
Alan Mishchenko committed
256 257 258 259
        if (nCountPis>0) {
            pNew = Ssw_SignalCorrespondence( pTemp, pPars );
            nClasses = Aig_TransferMappedClasses( pAig, pTemp, pMapBack );
            if ( fVerbose )
260
                Abc_Print( 1, "%3d : Reg = %4d. PI = %4d. (True = %4d. Regs = %4d.) And = %5d. It = %3d. Cl = %5d.\n",
261
                    i, Vec_IntSize(vPart), Aig_ManCiNum(pTemp)-Vec_IntSize(vPart), nCountPis, nCountRegs, Aig_ManNodeNum(pTemp), pPars->nIters, nClasses );
Alan Mishchenko committed
262 263
            Aig_ManStop( pNew );
        }
Alan Mishchenko committed
264
        Aig_ManStop( pTemp );
Alan Mishchenko committed
265
        ABC_FREE( pMapBack );
Alan Mishchenko committed
266 267 268 269 270 271 272 273 274 275 276
    }
    // remap the AIG
    pNew = Aig_ManDupRepr( pAig, 0 );
    Aig_ManSeqCleanup( pNew );
//    Aig_ManPrintStats( pAig );
//    Aig_ManPrintStats( pNew );
    Vec_VecFree( (Vec_Vec_t *)vResult );
    pPars->nPartSize = nPartSize;
    pPars->fVerbose = fVerbose;
    if ( fVerbose )
    {
277
        ABC_PRT( "Total time", Abc_Clock() - clk );
Alan Mishchenko committed
278 279 280 281 282
    }
    return pNew;
}


Alan Mishchenko committed
283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419
/**Function*************************************************************

  Synopsis    [Performs partitioned sequential SAT sweeping.]

  Description []
               
  SideEffects []

  SeeAlso     []

***********************************************************************/
Aig_Man_t * Ssw_SignalCorrespondencePart2( Aig_Man_t * pAig, Ssw_Pars_t * pPars )
{
    int fPrintParts = 1;
    //char Buffer[100];
    Aig_Man_t * pTemp, * pNew;
    Vec_Ptr_t * vAigs;    
    Vec_Ptr_t * vGias;
    Vec_Ptr_t * vMaps;
    Vec_Ptr_t * vResult;
    Vec_Int_t * vPart;
    int * pMapBack = NULL;
    int i, nCountPis, nCountRegs;
    int nClasses, nPartSize, fVerbose;
    abctime clk = Abc_Clock();
    if ( pPars->fConstrs )
    {
        Abc_Print( 1, "Cannot use partitioned computation with constraints.\n" );
        return NULL;
    }
    // save parameters
    nPartSize = pPars->nPartSize; pPars->nPartSize = 0;
    fVerbose  = pPars->fVerbose;  pPars->fVerbose  = 0;
    // generate partitions
    if ( pAig->vClockDoms )
    {
        // divide large clock domains into separate partitions
        vResult = Vec_PtrAlloc( 100 );
        Vec_PtrForEachEntry( Vec_Int_t *, (Vec_Ptr_t *)pAig->vClockDoms, vPart, i )
        {
            if ( nPartSize && Vec_IntSize(vPart) > nPartSize )
                Aig_ManPartDivide( vResult, vPart, nPartSize, pPars->nOverSize );
            else
                Vec_PtrPush( vResult, Vec_IntDup(vPart) );
        }
    }
    else
        vResult = Aig_ManRegPartitionSimple( pAig, nPartSize, pPars->nOverSize );
//    vResult = Aig_ManPartitionSmartRegisters( pAig, nPartSize, 0 ); 
//    vResult = Aig_ManRegPartitionSmart( pAig, nPartSize );
    // collect partitions
    vAigs = Vec_PtrAlloc( 100 );
    vGias = Vec_PtrAlloc( 100 );
    vMaps = Vec_PtrAlloc( 100 );
    if ( fPrintParts )
        Abc_Print( 1, "Simple partitioning. %d partitions are saved:\n", Vec_PtrSize(vResult) );
    Vec_PtrForEachEntry( Vec_Int_t *, vResult, vPart, i )
    {
        pTemp = Aig_ManRegCreatePart( pAig, vPart, &nCountPis, &nCountRegs, &pMapBack );
        Aig_ManSetRegNum( pTemp, pTemp->nRegs );
        Vec_PtrPush( vAigs, pTemp );
        Vec_PtrPush( vGias, Gia_ManFromAigSimple(pTemp) );
        Vec_PtrPush( vMaps, pMapBack );
        //sprintf( Buffer, "part%03d.aig", i );
        //Ioa_WriteAiger( pTemp, Buffer, 0, 0 );
        if ( fPrintParts )
            Abc_Print( 1, "part%03d.aig : Reg = %4d. PI = %4d. (True = %4d. Regs = %4d.) And = %5d.\n",
                i, Vec_IntSize(vPart), Aig_ManCiNum(pTemp)-Vec_IntSize(vPart), nCountPis, nCountRegs, Aig_ManNodeNum(pTemp) );
    }
    // solve partitions
    Ssw_SignalCorrespondenceArray( vGias, pPars );
    // collect the results
    Aig_ManReprStart( pAig, Aig_ManObjNumMax(pAig) );
    Vec_PtrForEachEntry( Vec_Int_t *, vResult, vPart, i )
    {
        int * pMapBack = (int *)Vec_PtrEntry( vMaps, i );
        Gia_Man_t * pGia = (Gia_Man_t *)Vec_PtrEntry( vGias, i );
        Aig_Man_t * pTemp2 = Gia_ManToAigSimple( pGia );
        pTemp = (Aig_Man_t *)Vec_PtrEntry( vAigs, i );
        Gia_ManReprToAigRepr2( pTemp2, pGia );
        // remap back
        nClasses = Aig_TransferMappedClasses( pAig, pTemp2, pMapBack );
        if ( fVerbose )
            Abc_Print( 1, "%3d : Reg = %4d. PI = %4d. (True = %4d. Regs = %4d.) And = %5d. It = %3d. Cl = %5d.\n",
                i, Vec_IntSize(vPart), Aig_ManCiNum(pTemp)-Vec_IntSize(vPart), 0, 0, Aig_ManNodeNum(pTemp), 0, nClasses );
        Aig_ManStop( pTemp );
        Aig_ManStop( pTemp2 );
        Gia_ManStop( pGia );
        ABC_FREE( pMapBack );
    }
    Vec_PtrFree( vAigs );
    Vec_PtrFree( vGias );
    Vec_PtrFree( vMaps );

    // remap the AIG
    pNew = Aig_ManDupRepr( pAig, 0 );
    Aig_ManSeqCleanup( pNew );
//    Aig_ManPrintStats( pAig );
//    Aig_ManPrintStats( pNew );
    Vec_VecFree( (Vec_Vec_t *)vResult );
    pPars->nPartSize = nPartSize;
    pPars->fVerbose = fVerbose;
    if ( fVerbose )
    {
        ABC_PRT( "Total time", Abc_Clock() - clk );
    }
    return pNew;
}
void Gia_ManRestoreNodeMapping( Aig_Man_t * pAig, Gia_Man_t * pGia )
{
    Aig_Obj_t * pObjAig; int i;
    assert( Gia_ManObjNum(pGia) == Aig_ManObjNum(pAig) );
    Aig_ManForEachObj( pAig, pObjAig, i )
        pObjAig->iData = Abc_Var2Lit(i, 0);
}
Gia_Man_t * Gia_SignalCorrespondencePart( Gia_Man_t * p, Cec_ParCor_t * pPars )
{
    Gia_Man_t * pRes = NULL;
    Aig_Man_t * pNew = NULL;
    Aig_Man_t * pAig = Gia_ManToAigSimple(p);
    Ssw_Pars_t SswPars, * pSswPars = &SswPars;
    assert( pPars->nProcs > 0 );
    assert( pPars->nPartSize > 0 );
    Ssw_ManSetDefaultParams( pSswPars ); 
    pSswPars->nBTLimit  = pPars->nBTLimit;
    pSswPars->nProcs    = pPars->nProcs;
    pSswPars->nPartSize = pPars->nPartSize;
    pSswPars->fVerbose  = pPars->fVerbose;
    pNew = Ssw_SignalCorrespondencePart2( pAig, pSswPars );
    Gia_ManRestoreNodeMapping( pAig, p );
    Gia_ManReprFromAigRepr2( pAig, p );
    pRes = Gia_ManFromAigSimple(pNew);
    Aig_ManStop( pNew );
    Aig_ManStop( pAig );
    return pRes;
}

Alan Mishchenko committed
420 421 422 423 424
////////////////////////////////////////////////////////////////////////
///                       END OF FILE                                ///
////////////////////////////////////////////////////////////////////////


425
ABC_NAMESPACE_IMPL_END