Skip to content

P
PropertyEmb
Commit 4055a7ab by lvzhengyang
Options

clean the cdfg tool dir

parent 7404953b
Showing with 8 additions and 210 deletions
thirdparty/RTL2CDFG/v2cdfg/.gitignore 0 → 100644
tmp/
operatorlist.txt
output.log
\ No newline at end of file
thirdparty/RTL2CDFG/v2cdfg/cdfg/.gitignore 0 → 100644
*.dot
\ No newline at end of file
thirdparty/RTL2CDFG/v2cdfg/cdfg/75_ast_clean_cdfg.dot deleted 100644 → 0
digraph test {
"Input,1,fifo_rd" [style=filled, color=yellow];
"Input,1,rst_n" [style=filled, color=yellow];
"Output,1,fifo_EF" [style=filled, color=green];
"Output,8,fifo_rdata" [style=filled, color=green];
"Output,1,rfifo_full" [style=filled, color=green];
"Output,6,rfifo_used" [style=filled, color=green];
"Wire,32,_00_" [style=filled, color=orange];
"Wire,1,_01_" [style=filled, color=orange];
"Wire,32,_02_" [style=filled, color=orange];
"Wire,32,_03_" [style=filled, color=orange];
"Wire,32,_04_" [style=filled, color=orange];
"Reg,32,bytes_left" [style=filled, color=orange];
"Reg,1,fifo_rd_d" [style=filled, color=orange];
"Wire,1,new_rom" [style=filled, color=orange];
"Wire,32,num_bytes" [style=filled, color=orange];
"Wire,7,rfifo_entries" [style=filled, color=orange];
"LNot,Null,LNot_1" [style=filled, color=pink];
"Gt,Null,Gt_1" [style=filled, color=pink];
"Const,7,Constant_7'H40" [style=filled, color=grey];
"Cond,Null,Cond_1" [style=filled, color=pink];
"Cond,Null,Cond_2" [style=filled, color=pink];
"Const,32,Constant_32'D0" [style=filled, color=grey];
"Cond,Null,Cond_3" [style=filled, color=pink];
"Const,1,Constant_1'H0" [style=filled, color=grey];
"Sub,Null,Sub_1" [style=filled, color=pink];
"Const,1,Constant_1'H1" [style=filled, color=grey];
"PartSelect,Null,PartSelect_0" [style=filled, color=pink];
"Const,Null,Constant_0" [style=filled, color=grey];
"Const,Null,Constant_5" [style=filled, color=grey];
"PartSelect,Null,PartSelect_1" [style=filled, color=pink];
"Const,Null,Constant_6" [style=filled, color=grey];
"PartSelect,Null,PartSelect_2" [style=filled, color=pink];
"Const,Null,Constant_7" [style=filled, color=grey];
"Const,Null,Constant_31" [style=filled, color=grey];
"Cond,Null,Cond_4" [style=filled, color=pink];
"Const,32,Constant_32'D64" [style=filled, color=grey];
"Concat,Null,Concat_1" [style=filled, color=pink];
"PartSelect,Null,PartSelect_3" [style=filled, color=pink];
"Const,8,Constant_8'H0" [style=filled, color=grey];
"Concat,Null,Concat_3" [style=filled, color=pink];
"Concat,Null,Concat_4" [style=filled, color=pink];
"Input,1,fifo_rd" -> "Cond,Null,Cond_3" [label="2"];
"Input,1,rst_n" -> "Cond,Null,Cond_2" [label="1"];
"Input,1,rst_n" -> "Cond,Null,Cond_3" [label="1"];
"Output,1,rfifo_full" -> "Cond,Null,Cond_4" [label="1"];
"Output,6,rfifo_used" -> "Concat,Null,Concat_1" [label="2"];
"Output,6,rfifo_used" -> "Concat,Null,Concat_3" [label="2"];
"Wire,32,_00_" -> "Reg,32,bytes_left" [label="1"];
"Wire,1,_01_" -> "Reg,1,fifo_rd_d" [label="1"];
"Wire,32,_02_" -> "Cond,Null,Cond_2" [label="2"];
"Wire,32,_03_" -> "Cond,Null,Cond_1" [label="2"];
"Reg,32,bytes_left" -> "LNot,Null,LNot_1" [label="1"];
"Reg,32,bytes_left" -> "Gt,Null,Gt_1" [label="1"];
"Reg,32,bytes_left" -> "Cond,Null,Cond_1" [label="3"];
"Reg,32,bytes_left" -> "Sub,Null,Sub_1" [label="1"];
"Reg,32,bytes_left" -> "Cond,Null,Cond_4" [label="3"];
"Reg,1,fifo_rd_d" -> "Cond,Null,Cond_1" [label="1"];
"Wire,7,rfifo_entries" -> "PartSelect,Null,PartSelect_3" [label="1"];
"LNot,Null,LNot_1" -> "Output,1,fifo_EF" [label="1"];
"Gt,Null,Gt_1" -> "Output,1,rfifo_full" [label="1"];
"Const,7,Constant_7'H40" -> "Gt,Null,Gt_1" [label="2"];
"Cond,Null,Cond_1" -> "Wire,32,_02_" [label="1"];
"Cond,Null,Cond_2" -> "Wire,32,_00_" [label="1"];
"Const,32,Constant_32'D0" -> "Cond,Null,Cond_2" [label="3"];
"Const,32,Constant_32'D0" -> "Wire,32,num_bytes" [label="1"];
"Cond,Null,Cond_3" -> "Wire,1,_01_" [label="1"];
"Const,1,Constant_1'H0" -> "Cond,Null,Cond_3" [label="3"];
"Const,1,Constant_1'H0" -> "Wire,1,new_rom" [label="1"];
"Sub,Null,Sub_1" -> "Wire,32,_03_" [label="1"];
"Const,1,Constant_1'H1" -> "Sub,Null,Sub_1" [label="2"];
"PartSelect,Null,PartSelect_0" -> "Output,6,rfifo_used" [label="1"];
"Const,Null,Constant_0" -> "PartSelect,Null,PartSelect_0" [label="3"];
"Const,Null,Constant_5" -> "PartSelect,Null,PartSelect_0" [label="2"];
"PartSelect,Null,PartSelect_1" -> "Concat,Null,Concat_3" [label="1"];
"Const,Null,Constant_6" -> "PartSelect,Null,PartSelect_1" [label="3"];
"Const,Null,Constant_6" -> "PartSelect,Null,PartSelect_1" [label="2"];
"Const,Null,Constant_6" -> "PartSelect,Null,PartSelect_3" [label="2"];
"Const,Null,Constant_6" -> "PartSelect,Null,PartSelect_3" [label="3"];
"PartSelect,Null,PartSelect_2" -> "Concat,Null,Concat_4" [label="1"];
"Const,Null,Constant_7" -> "PartSelect,Null,PartSelect_2" [label="3"];
"Const,Null,Constant_31" -> "PartSelect,Null,PartSelect_2" [label="2"];
"Cond,Null,Cond_4" -> "PartSelect,Null,PartSelect_0" [label="1"];
"Cond,Null,Cond_4" -> "PartSelect,Null,PartSelect_1" [label="1"];
"Cond,Null,Cond_4" -> "PartSelect,Null,PartSelect_2" [label="1"];
"Const,32,Constant_32'D64" -> "Cond,Null,Cond_4" [label="2"];
"Concat,Null,Concat_1" -> "Concat,Null,Concat_4" [label="2"];
"PartSelect,Null,PartSelect_3" -> "Concat,Null,Concat_1" [label="1"];
"Const,8,Constant_8'H0" -> "Output,8,fifo_rdata" [label="1"];
"Concat,Null,Concat_3" -> "Wire,7,rfifo_entries" [label="1"];
"Concat,Null,Concat_4" -> "Wire,32,_04_" [label="1"];
}
thirdparty/RTL2CDFG/v2cdfg/cdfg/Led_ast_clean_cdfg.dot deleted 100644 → 0
digraph test {
"Input,1,rst" [style=filled, color=yellow];
"Output,8,led" [style=filled, color=green];
"Wire,8,_0_" [style=filled, color=orange];
"Cond,Null,Cond_1" [style=filled, color=pink];
"Const,8,Constant_8'H1" [style=filled, color=grey];
"Concat,Null,Concat_1" [style=filled, color=pink];
"PartSelect,Null,PartSelect_0" [style=filled, color=pink];
"Const,Null,Constant_6" [style=filled, color=grey];
"Const,Null,Constant_0" [style=filled, color=grey];
"PartSelect,Null,PartSelect_1" [style=filled, color=pink];
"Const,Null,Constant_7" [style=filled, color=grey];
"Input,1,rst" -> "Cond,Null,Cond_1" [label="1"];
"Output,8,led" -> "PartSelect,Null,PartSelect_0" [label="1"];
"Output,8,led" -> "PartSelect,Null,PartSelect_1" [label="1"];
"Wire,8,_0_" -> "Output,8,led" [label="1"];
"Cond,Null,Cond_1" -> "Wire,8,_0_" [label="1"];
"Const,8,Constant_8'H1" -> "Cond,Null,Cond_1" [label="2"];
"Concat,Null,Concat_1" -> "Cond,Null,Cond_1" [label="3"];
"PartSelect,Null,PartSelect_0" -> "Concat,Null,Concat_1" [label="1"];
"Const,Null,Constant_6" -> "PartSelect,Null,PartSelect_0" [label="2"];
"Const,Null,Constant_0" -> "PartSelect,Null,PartSelect_0" [label="3"];
"PartSelect,Null,PartSelect_1" -> "Concat,Null,Concat_1" [label="2"];
"Const,Null,Constant_7" -> "PartSelect,Null,PartSelect_1" [label="2"];
"Const,Null,Constant_7" -> "PartSelect,Null,PartSelect_1" [label="3"];
}
thirdparty/RTL2CDFG/v2cdfg/cdfg/test_ast_clean_cdfg.dot deleted 100644 → 0
digraph test {
"Input,1,fifo_rd" [style=filled, color=yellow];
"Input,1,rst_n" [style=filled, color=yellow];
"Output,1,fifo_EF" [style=filled, color=green];
"Output,8,fifo_rdata" [style=filled, color=green];
"Output,1,rfifo_full" [style=filled, color=green];
"Output,6,rfifo_used" [style=filled, color=green];
"Wire,32,_00_" [style=filled, color=orange];
"Wire,1,_01_" [style=filled, color=orange];
"Wire,32,_02_" [style=filled, color=orange];
"Wire,32,_03_" [style=filled, color=orange];
"Wire,32,_04_" [style=filled, color=orange];
"Reg,32,bytes_left" [style=filled, color=orange];
"Reg,1,fifo_rd_d" [style=filled, color=orange];
"Wire,1,new_rom" [style=filled, color=orange];
"Wire,32,num_bytes" [style=filled, color=orange];
"Wire,7,rfifo_entries" [style=filled, color=orange];
"LNot,Null,LNot_1" [style=filled, color=pink];
"Gt,Null,Gt_1" [style=filled, color=pink];
"Const,7,Constant_7'H40" [style=filled, color=grey];
"Cond,Null,Cond_1" [style=filled, color=pink];
"Cond,Null,Cond_2" [style=filled, color=pink];
"Const,32,Constant_32'D0" [style=filled, color=grey];
"Cond,Null,Cond_3" [style=filled, color=pink];
"Const,1,Constant_1'H0" [style=filled, color=grey];
"Sub,Null,Sub_1" [style=filled, color=pink];
"Const,1,Constant_1'H1" [style=filled, color=grey];
"PartSelect,Null,PartSelect_0" [style=filled, color=pink];
"Const,Null,Constant_0" [style=filled, color=grey];
"Const,Null,Constant_5" [style=filled, color=grey];
"PartSelect,Null,PartSelect_1" [style=filled, color=pink];
"Const,Null,Constant_6" [style=filled, color=grey];
"PartSelect,Null,PartSelect_2" [style=filled, color=pink];
"Const,Null,Constant_7" [style=filled, color=grey];
"Const,Null,Constant_31" [style=filled, color=grey];
"Cond,Null,Cond_4" [style=filled, color=pink];
"Const,32,Constant_32'D64" [style=filled, color=grey];
"Concat,Null,Concat_1" [style=filled, color=pink];
"PartSelect,Null,PartSelect_3" [style=filled, color=pink];
"Const,8,Constant_8'H0" [style=filled, color=grey];
"Concat,Null,Concat_3" [style=filled, color=pink];
"Concat,Null,Concat_4" [style=filled, color=pink];
"Input,1,fifo_rd" -> "Cond,Null,Cond_3" [label="2"];
"Input,1,rst_n" -> "Cond,Null,Cond_2" [label="1"];
"Input,1,rst_n" -> "Cond,Null,Cond_3" [label="1"];
"Output,1,rfifo_full" -> "Cond,Null,Cond_4" [label="1"];
"Output,6,rfifo_used" -> "Concat,Null,Concat_1" [label="2"];
"Output,6,rfifo_used" -> "Concat,Null,Concat_3" [label="2"];
"Wire,32,_00_" -> "Reg,32,bytes_left" [label="1"];
"Wire,1,_01_" -> "Reg,1,fifo_rd_d" [label="1"];
"Wire,32,_02_" -> "Cond,Null,Cond_2" [label="2"];
"Wire,32,_03_" -> "Cond,Null,Cond_1" [label="2"];
"Reg,32,bytes_left" -> "LNot,Null,LNot_1" [label="1"];
"Reg,32,bytes_left" -> "Gt,Null,Gt_1" [label="1"];
"Reg,32,bytes_left" -> "Cond,Null,Cond_1" [label="3"];
"Reg,32,bytes_left" -> "Sub,Null,Sub_1" [label="1"];
"Reg,32,bytes_left" -> "Cond,Null,Cond_4" [label="3"];
"Reg,1,fifo_rd_d" -> "Cond,Null,Cond_1" [label="1"];
"Wire,7,rfifo_entries" -> "PartSelect,Null,PartSelect_3" [label="1"];
"LNot,Null,LNot_1" -> "Output,1,fifo_EF" [label="1"];
"Gt,Null,Gt_1" -> "Output,1,rfifo_full" [label="1"];
"Const,7,Constant_7'H40" -> "Gt,Null,Gt_1" [label="2"];
"Cond,Null,Cond_1" -> "Wire,32,_02_" [label="1"];
"Cond,Null,Cond_2" -> "Wire,32,_00_" [label="1"];
"Const,32,Constant_32'D0" -> "Cond,Null,Cond_2" [label="3"];
"Const,32,Constant_32'D0" -> "Wire,32,num_bytes" [label="1"];
"Cond,Null,Cond_3" -> "Wire,1,_01_" [label="1"];
"Const,1,Constant_1'H0" -> "Cond,Null,Cond_3" [label="3"];
"Const,1,Constant_1'H0" -> "Wire,1,new_rom" [label="1"];
"Sub,Null,Sub_1" -> "Wire,32,_03_" [label="1"];
"Const,1,Constant_1'H1" -> "Sub,Null,Sub_1" [label="2"];
"PartSelect,Null,PartSelect_0" -> "Output,6,rfifo_used" [label="1"];
"Const,Null,Constant_0" -> "PartSelect,Null,PartSelect_0" [label="3"];
"Const,Null,Constant_5" -> "PartSelect,Null,PartSelect_0" [label="2"];
"PartSelect,Null,PartSelect_1" -> "Concat,Null,Concat_3" [label="1"];
"Const,Null,Constant_6" -> "PartSelect,Null,PartSelect_1" [label="3"];
"Const,Null,Constant_6" -> "PartSelect,Null,PartSelect_1" [label="2"];
"Const,Null,Constant_6" -> "PartSelect,Null,PartSelect_3" [label="2"];
"Const,Null,Constant_6" -> "PartSelect,Null,PartSelect_3" [label="3"];
"PartSelect,Null,PartSelect_2" -> "Concat,Null,Concat_4" [label="1"];
"Const,Null,Constant_7" -> "PartSelect,Null,PartSelect_2" [label="3"];
"Const,Null,Constant_31" -> "PartSelect,Null,PartSelect_2" [label="2"];
"Cond,Null,Cond_4" -> "PartSelect,Null,PartSelect_0" [label="1"];
"Cond,Null,Cond_4" -> "PartSelect,Null,PartSelect_1" [label="1"];
"Cond,Null,Cond_4" -> "PartSelect,Null,PartSelect_2" [label="1"];
"Const,32,Constant_32'D64" -> "Cond,Null,Cond_4" [label="2"];
"Concat,Null,Concat_1" -> "Concat,Null,Concat_4" [label="2"];
"PartSelect,Null,PartSelect_3" -> "Concat,Null,Concat_1" [label="1"];
"Const,8,Constant_8'H0" -> "Output,8,fifo_rdata" [label="1"];
"Concat,Null,Concat_3" -> "Wire,7,rfifo_entries" [label="1"];
"Concat,Null,Concat_4" -> "Wire,32,_04_" [label="1"];
}
thirdparty/RTL2CDFG/v2cdfg/cdfg/timescale_ast_clean_cdfg.dot deleted 100644 → 0
This source diff could not be displayed because it is too large. You can view the blob instead.
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment