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MiniEDA
Commit 8f2a1719 by lvzhengyang
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fix syntax error in db_mgr.tcl

parent 8b471d37
Showing with 1 additions and 1 deletions
src/db_mgr/src/db_mgr.tcl
...@@ -57,7 +57,7 @@ define_cmd_args "read_verilog" { [-design]\ ...@@ -57,7 +57,7 @@ define_cmd_args "read_verilog" { [-design]\
proc read_verilog { args } { proc read_verilog { args } {
parse_key_args "read_verilog" args keys {-design} flags {} parse_key_args "read_verilog" args keys {-design} flags {}
set design "" set design ""
if { info exists keys(-design) } { if { [info exists keys(-design)] } {
set design $keys(-design) set design $keys(-design)
} }
set filename [file nativename [lindex $args 0]] set filename [file nativename [lindex $args 0]]
......
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