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MiniEDA
Commit 0c66a59f by lvzhengyang
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add 'test' from OpenROAD proj.

parent 511d537b
Showing with 3446 additions and 1 deletions
README.md
......@@ -9,6 +9,10 @@
* with swig
* use the original OpenDB, and build the tcl api by myself.
* add DB Manager
* manager multi block circuits. Because OpenDB supports only 2-level hierarchical dbBlock.
* each db is a block?
## DONE
### 2022.10.30
......
src/main/MiniEda.cc
......@@ -4,6 +4,7 @@
#include "utl/MakeLogger.h"
#include "utl/Logger.h"
#include "utl/tcl_utl.h"
#include "odb/db.h"
namespace eda {
extern const char* minieda_swig_tcl_inits[];
......@@ -23,16 +24,19 @@ namespace eda {
using utl::evalTclInit;
using utl::initTclUtil;
using odb::dbDatabase;
MiniEda::MiniEda()
: tcl_interp_(nullptr),
logger_(nullptr)
logger_(nullptr),
db_(nullptr)
{
}
MiniEda::~MiniEda()
{
odb::dbDatabase::destroy(db_);
delete logger_;
}
......@@ -64,6 +68,7 @@ void MiniEda::init(Tcl_Interp* interp)
}
logger_ = makeLogger(log_filename, metrics_filename);
db_ = dbDatabase::create();
// Init components.
Minieda_swig_Init(interp);
......
src/main/MiniEda.i
......@@ -2,6 +2,7 @@
#include "eda/MiniEda.hh"
#include "utl/Logger.h"
#include "odb/db.h"
////////////////////////////////////////////////////////////////
//
......@@ -22,11 +23,17 @@ utl::Logger* getLogger()
return MiniEda::miniEda()->getLogger();
}
odb::dbDatabase* getDb()
{
return MiniEda::miniEda()->getDb();
}
} // namespace eda
using eda::MiniEda;
using eda::getMiniEda;
using eda::getLogger;
using eda::getDb;
%}
......@@ -55,6 +62,11 @@ void logger_echo(const char* usr_input)
getLogger()->info(utl::EDA, 1, usr_input);
}
odb::dbDatabase* get_db()
{
return getDb();
}
}
%} // inline
......
src/main/MiniEda.tcl
......@@ -8,3 +8,7 @@ proc simple_test {args} {
parse_key_args "simple_test" args keys {-tmp}
logger_echo $keys(-tmp)
}
proc get_db {} {
eda::get_db
}
src/main/include/eda/MiniEda.hh
......@@ -8,6 +8,10 @@ namespace utl {
class Logger;
}
namespace odb {
class dbDatabase;
}
namespace eda {
class MiniEda
......@@ -18,6 +22,9 @@ public:
Tcl_Interp* tclInterp() { return tcl_interp_; }
utl::Logger* getLogger() { return logger_; }
// currently, we use db directly
// TODO: makes a db manager
odb::dbDatabase* getDb() { return db_; }
protected:
~MiniEda();
......@@ -28,6 +35,9 @@ private:
Tcl_Interp* tcl_interp_;
utl::Logger* logger_;
// currently, we use db directly
// TODO: makes a db manager
odb::dbDatabase* db_;
};
int tclAppInit(Tcl_Interp* interp);
......
test/Nangate45/Nangate45.lef 0 → 100644
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test/Nangate45/Nangate45.pdn.tcl 0 → 100644
####################################
# global connections
####################################
add_global_connection -defer_connection -net {VDD} -inst_pattern {.*} -pin_pattern {^VDD$} -power
add_global_connection -defer_connection -net {VDD} -inst_pattern {.*} -pin_pattern {^VDDPE$}
add_global_connection -defer_connection -net {VDD} -inst_pattern {.*} -pin_pattern {^VDDCE$}
add_global_connection -defer_connection -net {VSS} -inst_pattern {.*} -pin_pattern {^VSS$} -ground
add_global_connection -defer_connection -net {VSS} -inst_pattern {.*} -pin_pattern {^VSSE$}
global_connect
####################################
# voltage domains
####################################
set_voltage_domain -name {CORE} -power {VDD} -ground {VSS}
####################################
# standard cell grid
####################################
define_pdn_grid -name {grid} -voltage_domains {CORE}
add_pdn_stripe -grid {grid} -layer {metal1} -width {0.17} -pitch {2.4} -offset {0} -followpins
add_pdn_stripe -grid {grid} -layer {metal4} -width {0.48} -pitch {56.0} -offset {2}
add_pdn_stripe -grid {grid} -layer {metal7} -width {1.40} -pitch {40.0} -offset {2}
add_pdn_connect -grid {grid} -layers {metal1 metal4}
add_pdn_connect -grid {grid} -layers {metal4 metal7}
####################################
# macro grids
####################################
####################################
# grid for: CORE_macro_grid_1
####################################
define_pdn_grid -name {CORE_macro_grid_1} -voltage_domains {CORE} -macro -orient {R0 R180 MX MY} -halo {4.0 4.0 4.0 4.0} -default -grid_over_boundary
add_pdn_stripe -grid {CORE_macro_grid_1} -layer {metal5} -width {0.93} -pitch {10.0} -offset {2}
add_pdn_stripe -grid {CORE_macro_grid_1} -layer {metal6} -width {0.93} -pitch {10.0} -offset {2}
add_pdn_connect -grid {CORE_macro_grid_1} -layers {metal4 metal5}
add_pdn_connect -grid {CORE_macro_grid_1} -layers {metal5 metal6}
add_pdn_connect -grid {CORE_macro_grid_1} -layers {metal6 metal7}
####################################
# grid for: CORE_macro_grid_2
####################################
define_pdn_grid -name {CORE_macro_grid_2} -voltage_domains {CORE} -macro -orient {R90 R270 MXR90 MYR90} -halo {4.0 4.0 4.0 4.0} -default -grid_over_boundary
add_pdn_stripe -grid {CORE_macro_grid_2} -layer {metal6} -width {0.93} -pitch {40.0} -offset {2}
add_pdn_connect -grid {CORE_macro_grid_2} -layers {metal4 metal6}
add_pdn_connect -grid {CORE_macro_grid_2} -layers {metal6 metal7}
test/Nangate45/Nangate45.rc 0 → 100644
# find_wire_rc -17% adjustment
set_layer_rc -layer metal1 -resistance 5.432e-03 -capacitance 8.494e-02
set_layer_rc -layer metal2 -resistance 3.574e-03 -capacitance 8.081e-02
set_layer_rc -layer metal3 -resistance 3.574e-03 -capacitance 7.516e-02
set_layer_rc -layer metal4 -resistance 1.502e-03 -capacitance 9.663e-02
set_layer_rc -layer metal5 -resistance 1.502e-03 -capacitance 8.394e-02
set_layer_rc -layer metal6 -resistance 1.502e-03 -capacitance 7.298e-02
set_layer_rc -layer metal7 -resistance 1.883e-04 -capacitance 1.112e-01
set_layer_rc -layer metal8 -resistance 1.883e-04 -capacitance 8.528e-02
set_layer_rc -layer metal9 -resistance 3.780e-05 -capacitance 9.063e-02
set_layer_rc -layer metal10 -resistance 3.780e-05 -capacitance 6.635e-02
#MIA set_layer_rc -via -resistance
test/Nangate45/Nangate45.rcx_rules 0 → 100755
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test/Nangate45/Nangate45.tracks 0 → 100644
make_tracks metal1 -x_offset 0.095 -x_pitch 0.19 -y_offset 0.07 -y_pitch 0.14
make_tracks metal2 -x_offset 0.095 -x_pitch 0.19 -y_offset 0.07 -y_pitch 0.14
make_tracks metal3 -x_offset 0.095 -x_pitch 0.19 -y_offset 0.07 -y_pitch 0.14
make_tracks metal4 -x_offset 0.095 -x_pitch 0.28 -y_offset 0.07 -y_pitch 0.28
make_tracks metal5 -x_offset 0.095 -x_pitch 0.28 -y_offset 0.07 -y_pitch 0.28
make_tracks metal6 -x_offset 0.095 -x_pitch 0.28 -y_offset 0.07 -y_pitch 0.28
make_tracks metal7 -x_offset 0.095 -x_pitch 0.8 -y_offset 0.07 -y_pitch 0.8
make_tracks metal8 -x_offset 0.095 -x_pitch 0.8 -y_offset 0.07 -y_pitch 0.8
make_tracks metal9 -x_offset 0.095 -x_pitch 1.6 -y_offset 0.07 -y_pitch 1.6
make_tracks metal10 -x_offset 0.095 -x_pitch 1.6 -y_offset 0.07 -y_pitch 1.6
test/Nangate45/Nangate45.vars 0 → 100644
set platform "nangate45"
set tech_lef "Nangate45/Nangate45_tech.lef"
set std_cell_lef "Nangate45/Nangate45_stdcell.lef"
set extra_lef {}
set liberty_file "Nangate45/Nangate45_typ.lib"
set extra_liberty {}
set site "FreePDK45_38x28_10R_NP_162NW_34O"
set pdn_cfg "Nangate45/Nangate45.pdn.tcl"
set tracks_file "Nangate45/Nangate45.tracks"
set io_placer_hor_layer metal3
set io_placer_ver_layer metal2
set tapcell_args "-distance 120 \
-tapcell_master TAPCELL_X1 \
-endcap_master TAPCELL_X1"
set global_place_density 0.3
# default value
set global_place_density_penalty 8e-5
# placement padding in SITE widths applied to both sides
set global_place_pad 2
set detail_place_pad 1
set macro_place_halo {22.4 15.12}
set macro_place_channel {18.8 19.95}
set layer_rc_file "Nangate45/Nangate45.rc"
# equiv -resistance .0035 -capacitance .052
set wire_rc_layer "metal3"
set wire_rc_layer_clk "metal6"
set tielo_port "LOGIC0_X1/Z"
set tiehi_port "LOGIC1_X1/Z"
set dont_use {CLKBUF_* AOI211_X1 OAI211_X1}
# tie hi/low instance to load separation (microns)
set tie_separation 5
set cts_buffer "BUF_X4"
set cts_cluster_diameter 100
set filler_cells "FILLCELL*"
# global route
set global_routing_layers metal2-metal10
set global_routing_clock_layers metal6-metal10
set global_routing_layer_adjustments {{{metal2-metal10} 0.5}}
# detail route
set min_routing_layer metal2
set max_routing_layer metal10
set rcx_rules_file "Nangate45/Nangate45.rcx_rules"
# Local Variables:
# mode:tcl
# End:
test/Nangate45/Nangate45_fast.lib 0 → 100644
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test/Nangate45/Nangate45_slow.lib 0 → 100644
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test/Nangate45/Nangate45_stdcell.lef 0 → 100644
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test/Nangate45/Nangate45_typ.lib 0 → 100644
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test/Nangate45/fake_macros.lef 0 → 100644
VERSION 5.6 ;
BUSBITCHARS "[]" ;
DIVIDERCHAR "/" ;
MACRO HM_100x400_4x4
CLASS BLOCK ;
FOREIGN HM_100x400_4x4 0 0 ;
ORIGIN 0 0 ;
SYMMETRY X Y ;
SIZE 100 BY 400 ;
PIN I1
DIRECTION INPUT ;
PORT
LAYER metal1 ;
RECT 0 200 1 201 ;
END
END I1
PIN I2
DIRECTION INPUT ;
PORT
LAYER metal1 ;
RECT 0 210 1 211 ;
END
END I2
PIN I3
DIRECTION INPUT ;
PORT
LAYER metal1 ;
RECT 0 220 1 221 ;
END
END I3
PIN I4
DIRECTION INPUT ;
PORT
LAYER metal1 ;
RECT 0 230 1 231 ;
END
END I4
PIN O1
DIRECTION OUTPUT ;
PORT
LAYER metal1 ;
RECT 99 200 100 201 ;
END
END O1
PIN O2
DIRECTION OUTPUT ;
PORT
LAYER metal1 ;
RECT 99 210 100 211 ;
END
END O2
PIN O3
DIRECTION OUTPUT ;
PORT
LAYER metal1 ;
RECT 99 220 100 221 ;
END
END O3
PIN O4
DIRECTION OUTPUT ;
PORT
LAYER metal1 ;
RECT 99 230 100 231 ;
END
END O4
OBS
LAYER metal1 ;
POLYGON 0.235 0.84 0.47 0.84 0.47 0.46 0.045 0.46 0.045 0.19 0.115 0.19 0.115 0.39 0.54 0.39 0.54 0.91 0.305 0.91 0.305 1.25 0.235 1.25 ;
END
END HM_100x400_4x4
MACRO HM_100x100_1x1
CLASS BLOCK ;
FOREIGN HM_100x100_1x1 0 0 ;
ORIGIN 0 0 ;
SYMMETRY X Y ;
SIZE 100 BY 100 ;
PIN I1
DIRECTION INPUT ;
PORT
LAYER metal1 ;
RECT 0 50 1 51 ;
END
END I1
PIN O1
DIRECTION OUTPUT ;
PORT
LAYER metal1 ;
RECT 99 50 100 51 ;
END
END O1
OBS
LAYER metal1 ;
POLYGON 0.235 0.84 0.47 0.84 0.47 0.46 0.045 0.46 0.045 0.19 0.115 0.19 0.115 0.39 0.54 0.39 0.54 0.91 0.305 0.91 0.305 1.25 0.235 1.25 ;
END
END HM_100x100_1x1
test/Nangate45/fake_macros.lib 0 → 100644
library(fake_macros) {
technology (cmos);
delay_model : table_lookup;
revision : 1.0;
date : "2019-11-05 15:53:47Z";
comment : "SRAM";
time_unit : "1ns";
voltage_unit : "1V";
current_unit : "1mA";
leakage_power_unit : "1mW";
nom_process : 1;
nom_temperature : 25.000;
nom_voltage : 1.1;
capacitive_load_unit (1,pf);
pulling_resistance_unit : "1kohm";
operating_conditions(tt_1.0_25.0) {
process : 1;
temperature : 25.000;
voltage : 1.1;
tree_type : balanced_tree;
}
/* default attributes */
default_cell_leakage_power : 0;
default_fanout_load : 1;
default_inout_pin_cap : 0.0;
default_input_pin_cap : 0.0;
default_output_pin_cap : 0.0;
default_input_pin_cap : 0.0;
default_max_transition : 0.0;
default_operating_conditions : tt_1.0_25.0;
default_leakage_power_density : 0.0;
/* additional header data */
slew_derate_from_library : 1.000;
slew_lower_threshold_pct_fall : 10.000;
slew_upper_threshold_pct_fall : 90.000;
slew_lower_threshold_pct_rise : 10.000;
slew_upper_threshold_pct_rise : 90.000;
input_threshold_pct_fall : 50.000;
input_threshold_pct_rise : 50.000;
output_threshold_pct_fall : 50.000;
output_threshold_pct_rise : 50.000;
lu_table_template(fakeram45_64x7_mem_out_delay_template) {
variable_1 : input_net_transition;
variable_2 : total_output_net_capacitance;
index_1 ("1000, 1001");
index_2 ("1000, 1001");
}
lu_table_template(fakeram45_64x7_mem_out_slew_template) {
variable_1 : total_output_net_capacitance;
index_1 ("1000, 1001");
}
lu_table_template(fakeram45_64x7_constraint_template) {
variable_1 : related_pin_transition;
variable_2 : constrained_pin_transition;
index_1 ("1000, 1001");
index_2 ("1000, 1001");
}
power_lut_template(fakeram45_64x7_energy_template_clkslew) {
variable_1 : input_transition_time;
index_1 ("1000, 1001");
}
power_lut_template(fakeram45_64x7_energy_template_sigslew) {
variable_1 : input_transition_time;
index_1 ("1000, 1001");
}
library_features(report_delay_calculation);
cell(HM_100x400_4x4) {
area : 40000;
interface_timing : true;
is_macro : true;
pin (I1) {
direction : input;
}
pin (I2) {
direction : input;
}
pin (I3) {
direction : input;
}
pin (I4) {
direction : input;
}
pin (O1) {
direction : output;
}
pin (O2) {
direction : output;
}
pin (O3) {
direction : output;
}
pin (O4) {
direction : output;
}
}
cell(HM_100x100_1x1) {
area : 10000;
interface_timing : true;
is_macro : true;
pin (I1) {
direction : input;
}
pin (O1) {
direction : output;
}
}
}
test/Nangate45/fakeram45.cfg 0 → 100755
# config file to drive BSG Black-box SRAM Generator
# https://github.com/bespoke-silicon-group/bsg_fakeram.git
{
# The process node. This is used to tell cacti what technology to use when
# estimating power, performance and area numbers.
"tech_nm": 45,
# The operating voltage.
"voltage": 1.1,
# String to add in front of every metal layer number for the layer name.
"metalPrefix": "metal",
# The pin width for signal pins.
"pinWidth_nm": 70,
# The minimum pin pitch for signal pins (all pins will have a pitch that is a
# multuple of this pitch. The first pin will be a multiple of this pitch from
# the bottom edge of the macro too.
"pinPitch_nm": 140,
# Optional: snap the width and height of the sram to a multiple value.
"snapWidth_nm": 190,
"snapHeight_nm": 1400,
# Flips the pin orientations. Non-fliped assumes metal1 is vertical therefore
# supply pins on metal4 will be horizontal and signal pins will also be on
# metal4. If set to true, supply pins on metal4 will be vertical and signal
# pins will be on metal3.
"flipPins": true,
"libertyTimeUnit": "ns",
"libertyCapUnit": "ff",
"libertyPowerUnit": "nw",
# List of SRAM configurations (name, width, depth, and banks)
"srams": [
{"name": "fakeram45_64x7", "width": 7, "depth": 64, "banks": 1},
{"name": "fakeram45_64x32", "width": 32, "depth": 64, "banks": 1},
{"name": "fakeram45_1024x32", "width": 32, "depth": 1024, "banks": 1}
]
}
test/Nangate45/fakeram45_1024x32.lib 0 → 100644
library(fakeram45_1024x32) {
technology (cmos);
delay_model : table_lookup;
revision : 1.0;
date : "2021-12-02 00:16:14Z";
comment : "SRAM";
time_unit : "1ns";
voltage_unit : "1V";
current_unit : "1uA";
leakage_power_unit : "1nw";
nom_process : 1;
nom_temperature : 25.000;
nom_voltage : 1.1;
capacitive_load_unit (1,ff);
pulling_resistance_unit : "1kohm";
operating_conditions(tt_1.0_25.0) {
process : 1;
temperature : 25.000;
voltage : 1.1;
tree_type : balanced_tree;
}
/* default attributes */
default_cell_leakage_power : 0;
default_fanout_load : 1;
default_inout_pin_cap : 0.0;
default_input_pin_cap : 0.0;
default_output_pin_cap : 0.0;
default_input_pin_cap : 0.0;
default_max_transition : 0.227;
default_operating_conditions : tt_1.0_25.0;
default_leakage_power_density : 0.0;
/* additional header data */
slew_derate_from_library : 1.000;
slew_lower_threshold_pct_fall : 20.000;
slew_upper_threshold_pct_fall : 80.000;
slew_lower_threshold_pct_rise : 20.000;
slew_upper_threshold_pct_rise : 80.000;
input_threshold_pct_fall : 50.000;
input_threshold_pct_rise : 50.000;
output_threshold_pct_fall : 50.000;
output_threshold_pct_rise : 50.000;
lu_table_template(fakeram45_1024x32_mem_out_slew_template) {
variable_1 : total_output_net_capacitance;
index_1 ("1000, 1001");
}
library_features(report_delay_calculation);
type (fakeram45_1024x32_DATA) {
base_type : array ;
data_type : bit ;
bit_width : 32;
bit_from : 31;
bit_to : 0 ;
downto : true ;
}
type (fakeram45_1024x32_ADDRESS) {
base_type : array ;
data_type : bit ;
bit_width : 10;
bit_from : 9;
bit_to : 0 ;
downto : true ;
}
cell(fakeram45_1024x32) {
area : 33210.100;
interface_timing : true;
memory() {
type : ram;
address_width : 10;
word_width : 32;
}
pin(clk) {
direction : input;
capacitance : 25.000;
clock : true;
min_period : 0.304 ;
internal_power(){
rise_power(scalar) {
values ("6056.430")
}
fall_power(scalar) {
values ("6056.430")
}
}
}
bus(rd_out) {
bus_type : fakeram45_1024x32_DATA;
direction : output;
max_capacitance : 500.000;
memory_read() {
address : addr_in;
}
timing() {
related_pin : "clk" ;
timing_type : rising_edge;
timing_sense : non_unate;
cell_rise(scalar) {
values ("0.349");
}
cell_fall(scalar) {
values ("0.349");
}
rise_transition(fakeram45_1024x32_mem_out_slew_template) {
index_1 ("5.000, 500.000");
values ("0.009, 0.227")
}
fall_transition(fakeram45_1024x32_mem_out_slew_template) {
index_1 ("5.000, 500.000");
values ("0.009, 0.227")
}
}
}
pin(we_in){
direction : input;
capacitance : 5.000;
timing() {
related_pin : clk;
timing_type : setup_rising ;
rise_constraint(scalar) {
values ("0.050");
}
fall_constraint(scalar) {
values ("0.050");
}
}
timing() {
related_pin : clk;
timing_type : hold_rising ;
rise_constraint(scalar) {
values ("0.050");
}
fall_constraint(scalar) {
values ("0.050");
}
}
internal_power(){
rise_power(scalar) {
values ("60.564");
}
fall_power(scalar) {
values ("60.564");
}
}
}
pin(ce_in){
direction : input;
capacitance : 5.000;
timing() {
related_pin : clk;
timing_type : setup_rising ;
rise_constraint(scalar) {
values ("0.050");
}
fall_constraint(scalar) {
values ("0.050");
}
}
timing() {
related_pin : clk;
timing_type : hold_rising ;
rise_constraint(scalar) {
values ("0.050");
}
fall_constraint(scalar) {
values ("0.050");
}
}
internal_power(){
rise_power(scalar) {
values ("60.564");
}
fall_power(scalar) {
values ("60.564");
}
}
}
bus(addr_in) {
bus_type : fakeram45_1024x32_ADDRESS;
direction : input;
capacitance : 5.000;
timing() {
related_pin : clk;
timing_type : setup_rising ;
rise_constraint(scalar) {
values ("0.050");
}
fall_constraint(scalar) {
values ("0.050");
}
}
timing() {
related_pin : clk;
timing_type : hold_rising ;
rise_constraint(scalar) {
values ("0.050");
}
fall_constraint(scalar) {
values ("0.050");
}
}
internal_power(){
rise_power(scalar) {
values ("60.564");
}
fall_power(scalar) {
values ("60.564");
}
}
}
bus(wd_in) {
bus_type : fakeram45_1024x32_DATA;
memory_write() {
address : addr_in;
clocked_on : "clk";
}
direction : input;
capacitance : 5.000;
timing() {
related_pin : clk;
timing_type : setup_rising ;
rise_constraint(scalar) {
values ("0.050");
}
fall_constraint(scalar) {
values ("0.050");
}
}
timing() {
related_pin : clk;
timing_type : hold_rising ;
rise_constraint(scalar) {
values ("0.050");
}
fall_constraint(scalar) {
values ("0.050");
}
}
internal_power(){
when : "(! (we_in) )";
rise_power(scalar) {
values ("60.564");
}
fall_power(scalar) {
values ("60.564");
}
}
internal_power(){
when : "(we_in)";
rise_power(scalar) {
values ("60.564");
}
fall_power(scalar) {
values ("60.564");
}
}
}
bus(w_mask_in) {
bus_type : fakeram45_1024x32_DATA;
memory_write() {
address : addr_in;
clocked_on : "clk";
}
direction : input;
capacitance : 5.000;
timing() {
related_pin : clk;
timing_type : setup_rising ;
rise_constraint(scalar) {
values ("0.050");
}
fall_constraint(scalar) {
values ("0.050");
}
}
timing() {
related_pin : clk;
timing_type : hold_rising ;
rise_constraint(scalar) {
values ("0.050");
}
fall_constraint(scalar) {
values ("0.050");
}
}
internal_power(){
when : "(! (we_in) )";
rise_power(scalar) {
values ("60.564");
}
fall_power(scalar) {
values ("60.564");
}
}
internal_power(){
when : "(we_in)";
rise_power(scalar) {
values ("60.564");
}
fall_power(scalar) {
values ("60.564");
}
}
}
cell_leakage_power : 1607080.000;
}
}
test/Nangate45/fakeram45_64x32.lib 0 → 100644
library(fakeram45_64x32) {
technology (cmos);
delay_model : table_lookup;
revision : 1.0;
date : "2021-12-02 00:16:14Z";
comment : "SRAM";
time_unit : "1ns";
voltage_unit : "1V";
current_unit : "1uA";
leakage_power_unit : "1nw";
nom_process : 1;
nom_temperature : 25.000;
nom_voltage : 1.1;
capacitive_load_unit (1,ff);
pulling_resistance_unit : "1kohm";
operating_conditions(tt_1.0_25.0) {
process : 1;
temperature : 25.000;
voltage : 1.1;
tree_type : balanced_tree;
}
/* default attributes */
default_cell_leakage_power : 0;
default_fanout_load : 1;
default_inout_pin_cap : 0.0;
default_input_pin_cap : 0.0;
default_output_pin_cap : 0.0;
default_input_pin_cap : 0.0;
default_max_transition : 0.227;
default_operating_conditions : tt_1.0_25.0;
default_leakage_power_density : 0.0;
/* additional header data */
slew_derate_from_library : 1.000;
slew_lower_threshold_pct_fall : 20.000;
slew_upper_threshold_pct_fall : 80.000;
slew_lower_threshold_pct_rise : 20.000;
slew_upper_threshold_pct_rise : 80.000;
input_threshold_pct_fall : 50.000;
input_threshold_pct_rise : 50.000;
output_threshold_pct_fall : 50.000;
output_threshold_pct_rise : 50.000;
lu_table_template(fakeram45_64x32_mem_out_slew_template) {
variable_1 : total_output_net_capacitance;
index_1 ("1000, 1001");
}
library_features(report_delay_calculation);
type (fakeram45_64x32_DATA) {
base_type : array ;
data_type : bit ;
bit_width : 32;
bit_from : 31;
bit_to : 0 ;
downto : true ;
}
type (fakeram45_64x32_ADDRESS) {
base_type : array ;
data_type : bit ;
bit_width : 6;
bit_from : 5;
bit_to : 0 ;
downto : true ;
}
cell(fakeram45_64x32) {
area : 3888.122;
interface_timing : true;
memory() {
type : ram;
address_width : 6;
word_width : 32;
}
pin(clk) {
direction : input;
capacitance : 25.000;
clock : true;
min_period : 0.182 ;
internal_power(){
rise_power(scalar) {
values ("1696.620")
}
fall_power(scalar) {
values ("1696.620")
}
}
}
bus(rd_out) {
bus_type : fakeram45_64x32_DATA;
direction : output;
max_capacitance : 500.000;
memory_read() {
address : addr_in;
}
timing() {
related_pin : "clk" ;
timing_type : rising_edge;
timing_sense : non_unate;
cell_rise(scalar) {
values ("0.213");
}
cell_fall(scalar) {
values ("0.213");
}
rise_transition(fakeram45_64x32_mem_out_slew_template) {
index_1 ("5.000, 500.000");
values ("0.009, 0.227")
}
fall_transition(fakeram45_64x32_mem_out_slew_template) {
index_1 ("5.000, 500.000");
values ("0.009, 0.227")
}
}
}
pin(we_in){
direction : input;
capacitance : 5.000;
timing() {
related_pin : clk;
timing_type : setup_rising ;
rise_constraint(scalar) {
values ("0.050");
}
fall_constraint(scalar) {
values ("0.050");
}
}
timing() {
related_pin : clk;
timing_type : hold_rising ;
rise_constraint(scalar) {
values ("0.050");
}
fall_constraint(scalar) {
values ("0.050");
}
}
internal_power(){
rise_power(scalar) {
values ("16.966");
}
fall_power(scalar) {
values ("16.966");
}
}
}
pin(ce_in){
direction : input;
capacitance : 5.000;
timing() {
related_pin : clk;
timing_type : setup_rising ;
rise_constraint(scalar) {
values ("0.050");
}
fall_constraint(scalar) {
values ("0.050");
}
}
timing() {
related_pin : clk;
timing_type : hold_rising ;
rise_constraint(scalar) {
values ("0.050");
}
fall_constraint(scalar) {
values ("0.050");
}
}
internal_power(){
rise_power(scalar) {
values ("16.966");
}
fall_power(scalar) {
values ("16.966");
}
}
}
bus(addr_in) {
bus_type : fakeram45_64x32_ADDRESS;
direction : input;
capacitance : 5.000;
timing() {
related_pin : clk;
timing_type : setup_rising ;
rise_constraint(scalar) {
values ("0.050");
}
fall_constraint(scalar) {
values ("0.050");
}
}
timing() {
related_pin : clk;
timing_type : hold_rising ;
rise_constraint(scalar) {
values ("0.050");
}
fall_constraint(scalar) {
values ("0.050");
}
}
internal_power(){
rise_power(scalar) {
values ("16.966");
}
fall_power(scalar) {
values ("16.966");
}
}
}
bus(wd_in) {
bus_type : fakeram45_64x32_DATA;
memory_write() {
address : addr_in;
clocked_on : "clk";
}
direction : input;
capacitance : 5.000;
timing() {
related_pin : clk;
timing_type : setup_rising ;
rise_constraint(scalar) {
values ("0.050");
}
fall_constraint(scalar) {
values ("0.050");
}
}
timing() {
related_pin : clk;
timing_type : hold_rising ;
rise_constraint(scalar) {
values ("0.050");
}
fall_constraint(scalar) {
values ("0.050");
}
}
internal_power(){
when : "(! (we_in) )";
rise_power(scalar) {
values ("16.966");
}
fall_power(scalar) {
values ("16.966");
}
}
internal_power(){
when : "(we_in)";
rise_power(scalar) {
values ("16.966");
}
fall_power(scalar) {
values ("16.966");
}
}
}
bus(w_mask_in) {
bus_type : fakeram45_64x32_DATA;
memory_write() {
address : addr_in;
clocked_on : "clk";
}
direction : input;
capacitance : 5.000;
timing() {
related_pin : clk;
timing_type : setup_rising ;
rise_constraint(scalar) {
values ("0.050");
}
fall_constraint(scalar) {
values ("0.050");
}
}
timing() {
related_pin : clk;
timing_type : hold_rising ;
rise_constraint(scalar) {
values ("0.050");
}
fall_constraint(scalar) {
values ("0.050");
}
}
internal_power(){
when : "(! (we_in) )";
rise_power(scalar) {
values ("16.966");
}
fall_power(scalar) {
values ("16.966");
}
}
internal_power(){
when : "(we_in)";
rise_power(scalar) {
values ("16.966");
}
fall_power(scalar) {
values ("16.966");
}
}
}
cell_leakage_power : 169765.000;
}
}
test/Nangate45/fakeram45_64x7.lib 0 → 100644
library(fakeram45_64x7) {
technology (cmos);
delay_model : table_lookup;
revision : 1.0;
date : "2021-12-02 00:16:13Z";
comment : "SRAM";
time_unit : "1ns";
voltage_unit : "1V";
current_unit : "1uA";
leakage_power_unit : "1nw";
nom_process : 1;
nom_temperature : 25.000;
nom_voltage : 1.1;
capacitive_load_unit (1,ff);
pulling_resistance_unit : "1kohm";
operating_conditions(tt_1.0_25.0) {
process : 1;
temperature : 25.000;
voltage : 1.1;
tree_type : balanced_tree;
}
/* default attributes */
default_cell_leakage_power : 0;
default_fanout_load : 1;
default_inout_pin_cap : 0.0;
default_input_pin_cap : 0.0;
default_output_pin_cap : 0.0;
default_input_pin_cap : 0.0;
default_max_transition : 0.227;
default_operating_conditions : tt_1.0_25.0;
default_leakage_power_density : 0.0;
/* additional header data */
slew_derate_from_library : 1.000;
slew_lower_threshold_pct_fall : 20.000;
slew_upper_threshold_pct_fall : 80.000;
slew_lower_threshold_pct_rise : 20.000;
slew_upper_threshold_pct_rise : 80.000;
input_threshold_pct_fall : 50.000;
input_threshold_pct_rise : 50.000;
output_threshold_pct_fall : 50.000;
output_threshold_pct_rise : 50.000;
lu_table_template(fakeram45_64x7_mem_out_slew_template) {
variable_1 : total_output_net_capacitance;
index_1 ("1000, 1001");
}
library_features(report_delay_calculation);
type (fakeram45_64x7_DATA) {
base_type : array ;
data_type : bit ;
bit_width : 7;
bit_from : 6;
bit_to : 0 ;
downto : true ;
}
type (fakeram45_64x7_ADDRESS) {
base_type : array ;
data_type : bit ;
bit_width : 6;
bit_from : 5;
bit_to : 0 ;
downto : true ;
}
cell(fakeram45_64x7) {
area : 3011.120;
interface_timing : true;
memory() {
type : ram;
address_width : 6;
word_width : 7;
}
pin(clk) {
direction : input;
capacitance : 25.000;
clock : true;
min_period : 0.185 ;
internal_power(){
rise_power(scalar) {
values ("1126.120")
}
fall_power(scalar) {
values ("1126.120")
}
}
}
bus(rd_out) {
bus_type : fakeram45_64x7_DATA;
direction : output;
max_capacitance : 500.000;
memory_read() {
address : addr_in;
}
timing() {
related_pin : "clk" ;
timing_type : rising_edge;
timing_sense : non_unate;
cell_rise(scalar) {
values ("0.212");
}
cell_fall(scalar) {
values ("0.212");
}
rise_transition(fakeram45_64x7_mem_out_slew_template) {
index_1 ("5.000, 500.000");
values ("0.009, 0.227")
}
fall_transition(fakeram45_64x7_mem_out_slew_template) {
index_1 ("5.000, 500.000");
values ("0.009, 0.227")
}
}
}
pin(we_in){
direction : input;
capacitance : 5.000;
timing() {
related_pin : clk;
timing_type : setup_rising ;
rise_constraint(scalar) {
values ("0.050");
}
fall_constraint(scalar) {
values ("0.050");
}
}
timing() {
related_pin : clk;
timing_type : hold_rising ;
rise_constraint(scalar) {
values ("0.050");
}
fall_constraint(scalar) {
values ("0.050");
}
}
internal_power(){
rise_power(scalar) {
values ("11.261");
}
fall_power(scalar) {
values ("11.261");
}
}
}
pin(ce_in){
direction : input;
capacitance : 5.000;
timing() {
related_pin : clk;
timing_type : setup_rising ;
rise_constraint(scalar) {
values ("0.050");
}
fall_constraint(scalar) {
values ("0.050");
}
}
timing() {
related_pin : clk;
timing_type : hold_rising ;
rise_constraint(scalar) {
values ("0.050");
}
fall_constraint(scalar) {
values ("0.050");
}
}
internal_power(){
rise_power(scalar) {
values ("11.261");
}
fall_power(scalar) {
values ("11.261");
}
}
}
bus(addr_in) {
bus_type : fakeram45_64x7_ADDRESS;
direction : input;
capacitance : 5.000;
timing() {
related_pin : clk;
timing_type : setup_rising ;
rise_constraint(scalar) {
values ("0.050");
}
fall_constraint(scalar) {
values ("0.050");
}
}
timing() {
related_pin : clk;
timing_type : hold_rising ;
rise_constraint(scalar) {
values ("0.050");
}
fall_constraint(scalar) {
values ("0.050");
}
}
internal_power(){
rise_power(scalar) {
values ("11.261");
}
fall_power(scalar) {
values ("11.261");
}
}
}
bus(wd_in) {
bus_type : fakeram45_64x7_DATA;
memory_write() {
address : addr_in;
clocked_on : "clk";
}
direction : input;
capacitance : 5.000;
timing() {
related_pin : clk;
timing_type : setup_rising ;
rise_constraint(scalar) {
values ("0.050");
}
fall_constraint(scalar) {
values ("0.050");
}
}
timing() {
related_pin : clk;
timing_type : hold_rising ;
rise_constraint(scalar) {
values ("0.050");
}
fall_constraint(scalar) {
values ("0.050");
}
}
internal_power(){
when : "(! (we_in) )";
rise_power(scalar) {
values ("11.261");
}
fall_power(scalar) {
values ("11.261");
}
}
internal_power(){
when : "(we_in)";
rise_power(scalar) {
values ("11.261");
}
fall_power(scalar) {
values ("11.261");
}
}
}
bus(w_mask_in) {
bus_type : fakeram45_64x7_DATA;
memory_write() {
address : addr_in;
clocked_on : "clk";
}
direction : input;
capacitance : 5.000;
timing() {
related_pin : clk;
timing_type : setup_rising ;
rise_constraint(scalar) {
values ("0.050");
}
fall_constraint(scalar) {
values ("0.050");
}
}
timing() {
related_pin : clk;
timing_type : hold_rising ;
rise_constraint(scalar) {
values ("0.050");
}
fall_constraint(scalar) {
values ("0.050");
}
}
internal_power(){
when : "(! (we_in) )";
rise_power(scalar) {
values ("11.261");
}
fall_power(scalar) {
values ("11.261");
}
}
internal_power(){
when : "(we_in)";
rise_power(scalar) {
values ("11.261");
}
fall_power(scalar) {
values ("11.261");
}
}
}
cell_leakage_power : 136990.000;
}
}
test/aes_nangate45.metrics 0 → 100644
{
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"IFP::instance_count": "16759",
"floorplan__design__io": 388,
"design__instance__displacement__total": 10852.3130,
"design__instance__displacement__mean": 0.5690,
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"design__instance__displacement__max": 6.0075,
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"route__net": 16770,
"route__net__special": 2,
"GRT::ANT::errors": "0",
"route__drc_errors__iter:1": 7066,
"route__wirelength__iter:1": 644685,
"route__drc_errors__iter:2": 575,
"route__wirelength__iter:2": 642297,
"route__drc_errors__iter:3": 299,
"route__wirelength__iter:3": 641968,
"route__drc_errors__iter:4": 5,
"route__wirelength__iter:4": 641979,
"route__drc_errors__iter:5": 0,
"route__wirelength__iter:5": 641981,
"route__drc_errors": 0,
"route__wirelength": 641981,
"route__vias": 145321,
"route__vias__singlecut": 145321,
"route__vias__multicut": 0,
"DRT::drv": "0",
"DRT::ANT::errors": "0",
"DRT::worst_slack_min": "-0.05718108093315136",
"DRT::worst_slack_max": "-0.2342942572935271",
"DRT::tns_max": "-31.61210405143708",
"DRT::clock_skew": "0.0662706297484934",
"DRT::max_slew_slack": "39.00053949958037",
"DRT::max_fanout_slack": "100.0",
"DRT::max_capacitance_slack": "-1.3525113493335195",
"DRT::clock_period": "0.810900"
}
\ No newline at end of file
test/aes_nangate45.metrics_limits 0 → 100644
{
"IFP::instance_count" : "20110.8"
,"DPL::design_area" : "38067.6"
,"DPL::utilization" : "4.2"
,"RSZ::repair_design_buffer_count" : "423"
,"RSZ::max_slew_slack" : "0"
,"RSZ::max_capacitance_slack" : "0"
,"RSZ::max_fanout_slack" : "0"
,"RSZ::worst_slack_min" : "-0.07608769573204721"
,"RSZ::worst_slack_max" : "-0.2512975195629629"
,"RSZ::tns_max" : "-158.92208554118423"
,"RSZ::hold_buffer_count" : "37"
,"GRT::ANT::errors" : "0"
,"DRT::drv" : "0"
,"DRT::worst_slack_min" : "-0.11107108790535214"
,"DRT::worst_slack_max" : "-0.31131995273003293"
,"DRT::tns_max" : "-166.24929836283943"
,"DRT::clock_skew" : "0.08174567920615498"
,"DRT::max_slew_slack" : "0"
,"DRT::max_capacitance_slack" : "-7.552585746284018"
,"DRT::max_fanout_slack" : "0"
,"DRT::clock_period" : "0.8109"
}
test/aes_nangate45.sdc 0 → 100644
create_clock [get_ports clk] -period 0.8109
set_all_input_output_delays
test/aes_nangate45.tcl 0 → 100644
# aes flow pipe cleaner
source "helpers.tcl"
source "flow_helpers.tcl"
source "Nangate45/Nangate45.vars"
set design "aes"
set top_module "aes_cipher_top"
set synth_verilog "aes_nangate45.v"
set sdc_file "aes_nangate45.sdc"
set die_area {0 0 1020 920.8}
set core_area {10 12 1010 911.2}
set cap_margin 20
source -echo "flow.tcl"
test/aes_nangate45.v 0 → 100644
This source diff could not be displayed because it is too large. You can view the blob instead.
test/aes_sky130hd.metrics 0 → 100644
{
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"RSZ::max_slew_slack": "20.51331798235575",
"RSZ::max_fanout_slack": "100.0",
"RSZ::max_capacitance_slack": "81.48681816333135",
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"design__instance__displacement__mean": 0.0070,
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"RSZ::worst_slack_min": "0.0008095746524529989",
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"design__instance__displacement__total": 4220.2840,
"design__instance__displacement__mean": 0.0740,
"design__instance__displacement__max": 14.4540,
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"DPL::utilization": "7.3",
"DPL::design_area": "219447",
"design__violations": 0,
"route__net": 16572,
"route__net__special": 2,
"GRT::ANT::errors": "508",
"route__drc_errors__iter:1": 16208,
"route__wirelength__iter:1": 1563964,
"route__drc_errors__iter:2": 4458,
"route__wirelength__iter:2": 1557296,
"route__drc_errors__iter:3": 4265,
"route__wirelength__iter:3": 1553889,
"route__drc_errors__iter:4": 313,
"route__wirelength__iter:4": 1553935,
"route__drc_errors__iter:5": 65,
"route__wirelength__iter:5": 1553905,
"route__drc_errors__iter:6": 13,
"route__wirelength__iter:6": 1553894,
"route__drc_errors__iter:7": 8,
"route__wirelength__iter:7": 1553892,
"route__drc_errors__iter:8": 4,
"route__wirelength__iter:8": 1553893,
"route__drc_errors__iter:9": 1,
"route__wirelength__iter:9": 1553896,
"route__drc_errors__iter:10": 0,
"route__wirelength__iter:10": 1553895,
"route__drc_errors": 0,
"route__wirelength": 1553895,
"route__vias": 153687,
"route__vias__singlecut": 153687,
"route__vias__multicut": 0,
"DRT::drv": "0",
"DRT::ANT::errors": "494",
"DRT::worst_slack_min": "-0.0870157304174139",
"DRT::worst_slack_max": "-1.5170327645697625",
"DRT::tns_max": "-242.5023592795052",
"DRT::clock_skew": "1.2768122476254826",
"DRT::max_slew_slack": "-0.11608922555737015",
"DRT::max_fanout_slack": "100.0",
"DRT::max_capacitance_slack": "-0.7950441028491559",
"DRT::clock_period": "3.740000"
}
\ No newline at end of file
test/aes_sky130hd.metrics_limits 0 → 100644
{
"IFP::instance_count" : "20652.0"
,"DPL::design_area" : "263336.39999999997"
,"DPL::utilization" : "8.76"
,"RSZ::repair_design_buffer_count" : "391"
,"RSZ::max_slew_slack" : "0"
,"RSZ::max_capacitance_slack" : "0"
,"RSZ::max_fanout_slack" : "0"
,"RSZ::worst_slack_min" : "-0.37319042534754704"
,"RSZ::worst_slack_max" : "-1.423933947279282"
,"RSZ::tns_max" : "-818.883506975476"
,"RSZ::hold_buffer_count" : "792"
,"GRT::ANT::errors" : "520"
,"DRT::drv" : "0"
,"DRT::worst_slack_min" : "-0.46101573041741395"
,"DRT::worst_slack_max" : "-1.8910327645697627"
,"DRT::tns_max" : "-886.1563592795053"
,"DRT::clock_skew" : "1.5321746971505792"
,"DRT::max_slew_slack" : "-0.13930707066884418"
,"DRT::max_capacitance_slack" : "-0.9540529234189871"
,"DRT::max_fanout_slack" : "0"
,"DRT::clock_period" : "3.74"
}
test/aes_sky130hd.sdc 0 → 100644
create_clock [get_ports clk] -period 3.74
set_all_input_output_delays
test/aes_sky130hd.tcl 0 → 100644
# aes sky130hd 23539 insts
source "helpers.tcl"
source "flow_helpers.tcl"
source "sky130hd/sky130hd.vars"
set design "aes"
set top_module "aes_cipher_top"
set synth_verilog "aes_sky130hd.v"
set sdc_file "aes_sky130hd.sdc"
set die_area {0 0 2000 2000}
set core_area {30 30 1770 1770}
set slew_margin 20
source -echo "flow.tcl"
test/aes_sky130hd.v 0 → 100644
This source diff could not be displayed because it is too large. You can view the blob instead.
test/aes_sky130hs.metrics 0 → 100644
{
"IFP::ord_version" : ""
, "IFP::instance_count" : "16324"
, "RSZ::repair_design_buffer_count" : "567"
, "RSZ::max_slew_slack" : "20.783552527427673"
, "RSZ::max_fanout_slack" : "100.0"
, "RSZ::max_capacitance_slack" : "54.14508103045722"
, "RSZ::worst_slack_min" : "0.0001769695551302908"
, "RSZ::worst_slack_max" : "-0.7033427372926923"
, "RSZ::tns_max" : "-120.91811982837284"
, "RSZ::hold_buffer_count" : "1301"
, "DPL::utilization" : "10.6"
, "DPL::design_area" : "320572"
, "GRT::ANT::errors" : "0"
, "drt::wire length::total" : 1708380
, "drt::vias::total" : 154035
, "DRT::drv" : "0"
, "DRT::worst_slack_min" : "-0.023951730166059393"
, "DRT::worst_slack_max" : "-0.9552692240950822"
, "DRT::tns_max" : "-145.454681749565"
, "DRT::clock_skew" : "0.7748965022311598"
, "DRT::max_slew_slack" : "15.751168131828308"
, "DRT::max_fanout_slack" : "100.0"
, "DRT::max_capacitance_slack" : "42.8462133686562"
, "DRT::clock_period" : "2.811000"
}
test/aes_sky130hs.metrics_limits 0 → 100644
{
"IFP::instance_count" : "19588.8"
,"DPL::design_area" : "384686.39999999997"
,"DPL::utilization" : "12.719999999999999"
,"RSZ::repair_design_buffer_count" : "680"
,"RSZ::max_slew_slack" : "0"
,"RSZ::max_capacitance_slack" : "0"
,"RSZ::max_fanout_slack" : "0"
,"RSZ::worst_slack_min" : "-0.2809230304448697"
,"RSZ::worst_slack_max" : "-0.9844427372926923"
,"RSZ::tns_max" : "-579.7857598283729"
,"RSZ::hold_buffer_count" : "1561"
,"GRT::ANT::errors" : "400"
,"DRT::drv" : "0"
,"DRT::worst_slack_min" : "-0.3050517301660594"
,"DRT::worst_slack_max" : "-1.2363692240950823"
,"DRT::tns_max" : "-604.322321749565"
,"DRT::clock_skew" : "0.9298758026773917"
,"DRT::max_slew_slack" : "0"
,"DRT::max_capacitance_slack" : "0"
,"DRT::max_fanout_slack" : "0"
,"DRT::clock_period" : "2.811"
}
test/aes_sky130hs.sdc 0 → 100644
create_clock -period 2.811 [get_ports clk]
set_all_input_output_delays
test/aes_sky130hs.tcl 0 → 100644
# aes flow pipe cleaner
source "helpers.tcl"
source "flow_helpers.tcl"
source "sky130hs/sky130hs.vars"
set design "aes"
set top_module "aes_cipher_top"
set synth_verilog "aes_sky130hs.v"
set sdc_file "aes_sky130hs.sdc"
set die_area {0 0 2000 2000}
set core_area {30 30 1770 1770}
set slew_margin 15
set cap_margin 20
source -echo "flow.tcl"
test/aes_sky130hs.v 0 → 100644
This source diff could not be displayed because it is too large. You can view the blob instead.
test/compare_flow_metrics 0 → 100755
#!/bin/sh
# The next line is executed by /bin/sh, but not Tcl \
exec tclsh $0 ${1+"$@"}
# Directory containing tests.
set test_dir [file dirname [file normalize [info script]]]
set openroad_dir [file dirname $test_dir]
source [file join $test_dir "regression.tcl"]
source [file join $test_dir "regression_tests.tcl"]
source [file join $test_dir "flow_metrics.tcl"]
compare_flow_metrics_main
# Local Variables:
# mode:tcl
# End:
test/error1.ok 0 → 100644
[ERROR ORD-0001] catch a luser
caught 'ORD-0001'
[ERROR ORD-0003] xxx does not exist.
caught 'ORD-0003'
test/error1.tcl 0 → 100644
# error handling
if { [catch { utl::error ORD 1 "catch a luser" } result] } {
puts "caught '$result'"
}
if { [catch { read_def xxx } result] } {
puts "caught '$result'"
}
catch {utl::error ORD 1"last chance"} error
test/flow.tcl 0 → 100644
This diff is collapsed. Click to expand it.
test/flow_helpers.tcl 0 → 100644
# defaults
set slew_margin 0
set cap_margin 0
set power_corner "default"
proc read_libraries {} {
global tech_lef std_cell_lef extra_lef
global liberty_file liberty_files extra_liberty
read_lef $tech_lef
read_lef $std_cell_lef
foreach file $extra_lef { read_lef $file }
set corners [sta::corners]
if { [llength $corners] > 1 } {
foreach corner $corners {
set corner_name [$corner name]
set corner_index [lsearch $liberty_files $corner_name]
if { $corner_index == -1 } {
error "No liberty file in \$liberty_files for corner $corner_name."
} else {
set liberty_file [lindex $liberty_files [expr $corner_index + 1]]
read_liberty -corner $corner_name $liberty_file
}
}
} else {
read_liberty $liberty_file
}
foreach file $extra_liberty { read_liberty $file }
}
proc have_macros {} {
set db [::ord::get_db]
set block [[$db getChip] getBlock]
foreach inst [$block getInsts] {
set inst_master [$inst getMaster]
# BLOCK means MACRO cells
if { [string match [$inst_master getType] "BLOCK"] } {
return 1
}
}
return 0
}
proc derate_layer_wire_rc { layer_name corner derate_factor } {
set layer [[ord::get_db_tech] findLayer $layer_name]
lassign [rsz::dblayer_wire_rc $layer] r c
# ohm/meter -> kohm/micron
set r_ui [expr $r * 1e-3 * 1e-6]
# F/meter -> fF/micron
set c_ui [expr $c * 1e+15 * 1e-6]
set_layer_rc -layer $layer_name -corner $corner \
-resistance [expr $r_ui * $derate_factor] \
-capacitance [expr $c_ui * $derate_factor]
}
proc set_all_input_output_delays {{clk_period_factor .2}} {
set clk [lindex [all_clocks] 0]
set period [get_property $clk period]
set delay [expr $period * $clk_period_factor]
set_input_delay $delay -clock $clk [delete_from_list [all_inputs] [all_clocks]]
set_output_delay $delay -clock $clk [delete_from_list [all_outputs] [all_clocks]]
}
test/gcd_nangate45.metrics 0 → 100644
{
"IFP::ord_version" : ""
, "IFP::instance_count" : "363"
, "RSZ::repair_design_buffer_count" : "0"
, "RSZ::max_slew_slack" : "38.38480220375221"
, "RSZ::max_fanout_slack" : "100.0"
, "RSZ::max_capacitance_slack" : "9.247201894102455"
, "RSZ::worst_slack_min" : "0.05458949419236768"
, "RSZ::worst_slack_max" : "-0.04705735934112258"
, "RSZ::tns_max" : "-0.6746677296682354"
, "RSZ::hold_buffer_count" : "0"
, "DPL::utilization" : "8.7"
, "DPL::design_area" : "556"
, "GRT::ANT::errors" : "0"
, "drt::wire length::total" : 5800
, "drt::vias::total" : 2401
, "DRT::drv" : "0"
, "DRT::worst_slack_min" : "0.05372399205346745"
, "DRT::worst_slack_max" : "-0.06167350138483673"
, "DRT::tns_max" : "-0.8102423405988921"
, "DRT::clock_skew" : "0.003904279787756438"
, "DRT::max_slew_slack" : "36.16262384735254"
, "DRT::max_fanout_slack" : "100.0"
, "DRT::max_capacitance_slack" : "5.728270756197659"
, "DRT::clock_period" : "0.485000"
}
test/gcd_nangate45.metrics_limits 0 → 100644
{
"IFP::instance_count" : "435.59999999999997"
,"DPL::design_area" : "667.1999999999999"
,"DPL::utilization" : "10.44"
,"RSZ::repair_design_buffer_count" : "0"
,"RSZ::max_slew_slack" : "0"
,"RSZ::max_capacitance_slack" : "0"
,"RSZ::max_fanout_slack" : "0"
,"RSZ::worst_slack_min" : "0.006089494192367678"
,"RSZ::worst_slack_max" : "-0.09555735934112258"
,"RSZ::tns_max" : "-2.4352177296682354"
,"RSZ::hold_buffer_count" : "0"
,"GRT::ANT::errors" : "0"
,"DRT::drv" : "0"
,"DRT::worst_slack_min" : "0.0052239920534674494"
,"DRT::worst_slack_max" : "-0.11017350138483673"
,"DRT::tns_max" : "-2.570792340598892"
,"DRT::clock_skew" : "0.004685135745307725"
,"DRT::max_slew_slack" : "0"
,"DRT::max_capacitance_slack" : "0"
,"DRT::max_fanout_slack" : "0"
,"DRT::clock_period" : "0.485"
}
test/gcd_nangate45.sdc 0 → 100644
create_clock [get_ports clk] -name core_clock -period 0.4850
set_all_input_output_delays
test/gcd_nangate45.tcl 0 → 100644
# gcd flow pipe cleaner
source "helpers.tcl"
source "flow_helpers.tcl"
source "Nangate45/Nangate45.vars"
set design "gcd"
set top_module "gcd"
set synth_verilog "gcd_nangate45.v"
set sdc_file "gcd_nangate45.sdc"
set die_area {0 0 100.13 100.8}
set core_area {10.07 11.2 90.25 91}
source -echo "flow.tcl"
test/gcd_sky130hd.metrics 0 → 100644
{
"IFP::ord_version": "",
"IFP::instance_count": "250",
"floorplan__design__io": 54,
"design__instance__displacement__total": 491.5280,
"design__instance__displacement__mean": 0.3840,
"design__instance__displacement__max": 7.8400,
"route__wirelength__estimated": 12384.0710,
"RSZ::repair_design_buffer_count": "0",
"RSZ::max_slew_slack": "20.705445607503258",
"RSZ::max_fanout_slack": "100.0",
"RSZ::max_capacitance_slack": "20.335694059745553",
"design__instance__displacement__total": 5.5760,
"design__instance__displacement__mean": 0.0040,
"design__instance__displacement__max": 2.9200,
"route__wirelength__estimated": 12790.8860,
"RSZ::worst_slack_min": "0.48320909752299246",
"RSZ::worst_slack_max": "-0.658877637765081",
"RSZ::tns_max": "-15.178505992817524",
"RSZ::hold_buffer_count": "0",
"design__instance__displacement__total": 48.2430,
"design__instance__displacement__mean": 0.0370,
"design__instance__displacement__max": 6.7130,
"route__wirelength__estimated": 13031.9770,
"DPL::utilization": "4.9",
"DPL::design_area": "3834",
"design__violations": 0,
"route__net": 285,
"route__net__special": 2,
"GRT::ANT::errors": "8",
"route__drc_errors__iter:1": 146,
"route__wirelength__iter:1": 15642,
"route__drc_errors__iter:2": 67,
"route__wirelength__iter:2": 15537,
"route__drc_errors__iter:3": 19,
"route__wirelength__iter:3": 15500,
"route__drc_errors__iter:4": 0,
"route__wirelength__iter:4": 15511,
"route__drc_errors": 0,
"route__wirelength": 15511,
"route__vias": 1881,
"route__vias__singlecut": 1881,
"route__vias__multicut": 0,
"DRT::drv": "0",
"DRT::ANT::errors": "9",
"DRT::worst_slack_min": "0.474528429981396",
"DRT::worst_slack_max": "-0.6411247270100283",
"DRT::tns_max": "-16.662588225262926",
"DRT::clock_skew": "0.030209502421340975",
"DRT::max_slew_slack": "39.12427140884942",
"DRT::max_fanout_slack": "100.0",
"DRT::max_capacitance_slack": "89.15129055973324",
"DRT::clock_period": "4.360000"
}
\ No newline at end of file
test/gcd_sky130hd.metrics_limits 0 → 100644
{
"IFP::instance_count" : "300.0"
,"DPL::design_area" : "4600.8"
,"DPL::utilization" : "5.88"
,"RSZ::repair_design_buffer_count" : "0"
,"RSZ::max_slew_slack" : "0"
,"RSZ::max_capacitance_slack" : "0"
,"RSZ::max_fanout_slack" : "0"
,"RSZ::worst_slack_min" : "0.047209097522992405"
,"RSZ::worst_slack_max" : "-1.094877637765081"
,"RSZ::tns_max" : "-26.078505992817526"
,"RSZ::hold_buffer_count" : "0"
,"GRT::ANT::errors" : "8"
,"DRT::drv" : "0"
,"DRT::worst_slack_min" : "0.03852842998139594"
,"DRT::worst_slack_max" : "-1.0771247270100284"
,"DRT::tns_max" : "-27.562588225262928"
,"DRT::clock_skew" : "0.036251402905609166"
,"DRT::max_slew_slack" : "0"
,"DRT::max_capacitance_slack" : "0"
,"DRT::max_fanout_slack" : "0"
,"DRT::clock_period" : "4.36"
}
test/gcd_sky130hd.sdc 0 → 100644
create_clock -name core_clock -period 4.36 [get_ports clk]
set_all_input_output_delays
test/gcd_sky130hd.tcl 0 → 100644
# gcd flow pipe cleaner
source "helpers.tcl"
source "flow_helpers.tcl"
source "sky130hd/sky130hd.vars"
set synth_verilog "gcd_sky130hd.v"
set design "gcd"
set top_module "gcd"
set sdc_file "gcd_sky130hd.sdc"
set die_area {0 0 299.96 300.128}
set core_area {9.996 10.08 289.964 290.048}
source -echo "flow.tcl"
test/gcd_sky130hd_fast_slow.tcl 0 → 100644
# gcd flow with fast/slow corners
source "helpers.tcl"
source "flow_helpers.tcl"
source "sky130hd/sky130hd.vars"
set synth_verilog "gcd_sky130hd.v"
set design "gcd"
set top_module "gcd"
set sdc_file "gcd_sky130hd.sdc"
set die_area {0 0 299.96 300.128}
set core_area {9.996 10.08 289.964 290.048}
set max_drv_count 1
# liberty units (ns)
set setup_slack_limit -7.0
set hold_slack_limit 0.0
define_corners fast slow
set power_corner "fast"
source -echo flow.tcl
test/gcd_sky130hs.metrics 0 → 100644
{
"IFP::ord_version": "",
"IFP::instance_count": "305",
"floorplan__design__io": 54,
"design__instance__displacement__total": 912.2000,
"design__instance__displacement__mean": 0.7960,
"design__instance__displacement__max": 9.9270,
"route__wirelength__estimated": 13097.3420,
"RSZ::repair_design_buffer_count": "0",
"RSZ::max_slew_slack": "33.45616161823273",
"RSZ::max_fanout_slack": "100.0",
"RSZ::max_capacitance_slack": "94.60247183876743",
"design__instance__displacement__total": 14.5950,
"design__instance__displacement__mean": 0.0120,
"design__instance__displacement__max": 4.8000,
"route__wirelength__estimated": 13546.9180,
"RSZ::worst_slack_min": "0.09843440230420133",
"RSZ::worst_slack_max": "-0.23241476068198338",
"RSZ::tns_max": "-4.08168177476705",
"RSZ::hold_buffer_count": "0",
"design__instance__displacement__total": 236.3150,
"design__instance__displacement__mean": 0.1990,
"design__instance__displacement__max": 8.8250,
"route__wirelength__estimated": 13921.2580,
"DPL::utilization": "7.1",
"DPL::design_area": "5508",
"design__violations": 0,
"route__net": 368,
"route__net__special": 2,
"GRT::ANT::errors": "1",
"route__drc_errors__iter:1": 93,
"route__wirelength__iter:1": 16402,
"route__drc_errors__iter:2": 11,
"route__wirelength__iter:2": 16349,
"route__drc_errors__iter:3": 6,
"route__wirelength__iter:3": 16338,
"route__drc_errors__iter:4": 0,
"route__wirelength__iter:4": 16337,
"route__drc_errors": 0,
"route__wirelength": 16337,
"route__vias": 2226,
"route__vias__singlecut": 2226,
"route__vias__multicut": 0,
"DRT::drv": "0",
"DRT::ANT::errors": "1",
"DRT::worst_slack_min": "0.10848508509693192",
"DRT::worst_slack_max": "-0.24042168936203143",
"DRT::tns_max": "-4.043763660600815",
"DRT::clock_skew": "0.035697695809762835",
"DRT::max_slew_slack": "36.02901995182037",
"DRT::max_fanout_slack": "100.0",
"DRT::max_capacitance_slack": "93.5331882029241",
"DRT::clock_period": "1.780000"
}
\ No newline at end of file
test/gcd_sky130hs.metrics_limits 0 → 100644
{
"IFP::instance_count" : "366.0"
,"DPL::design_area" : "6609.599999999999"
,"DPL::utilization" : "8.52"
,"RSZ::repair_design_buffer_count" : "0"
,"RSZ::max_slew_slack" : "0"
,"RSZ::max_capacitance_slack" : "0"
,"RSZ::max_fanout_slack" : "0"
,"RSZ::worst_slack_min" : "-0.07956559769579868"
,"RSZ::worst_slack_max" : "-0.4104147606819834"
,"RSZ::tns_max" : "-9.51068177476705"
,"RSZ::hold_buffer_count" : "0"
,"GRT::ANT::errors" : "3"
,"DRT::drv" : "0"
,"DRT::worst_slack_min" : "-0.0695149149030681"
,"DRT::worst_slack_max" : "-0.41842168936203145"
,"DRT::tns_max" : "-9.472763660600815"
,"DRT::clock_skew" : "0.0428372349717154"
,"DRT::max_slew_slack" : "0"
,"DRT::max_capacitance_slack" : "0"
,"DRT::max_fanout_slack" : "0"
,"DRT::clock_period" : "1.78"
}
test/gcd_sky130hs.sdc 0 → 100644
create_clock -name core_clock -period 1.78 [get_ports clk]
set_all_input_output_delays
test/gcd_sky130hs.tcl 0 → 100644
# gcd flow pipe cleaner
source "helpers.tcl"
source "flow_helpers.tcl"
source "sky130hs/sky130hs.vars"
set synth_verilog "gcd_sky130hs.v"
set design "gcd"
set top_module "gcd"
set sdc_file "gcd_sky130hs.sdc"
set die_area {0 0 299.96 300.128}
set core_area {9.996 10.08 289.964 290.048}
source -echo "flow.tcl"
test/get_core_die_areas.def 0 → 100644
VERSION 5.8 ;
DIVIDERCHAR "/" ;
BUSBITCHARS "[]" ;
DESIGN top ;
UNITS DISTANCE MICRONS 2000 ;
DIEAREA ( 0 0 ) ( 1020280 510140 ) ;
ROW ROW_0 FreePDK45_38x28_10R_NP_162NW_34O 399760 198800 FS DO 54 BY 1 STEP 380 0 ;
ROW ROW_1 FreePDK45_38x28_10R_NP_162NW_34O 399760 201600 N DO 54 BY 1 STEP 380 0 ;
ROW ROW_2 FreePDK45_38x28_10R_NP_162NW_34O 399760 204400 FS DO 54 BY 1 STEP 380 0 ;
ROW ROW_3 FreePDK45_38x28_10R_NP_162NW_34O 399760 207200 N DO 54 BY 1 STEP 380 0 ;
COMPONENTS 5 ;
- r1 DFF_X1 ;
- r2 DFF_X1 ;
- r3 DFF_X1 ;
- u1 BUF_X1 ;
- u2 AND2_X1 ;
END COMPONENTS
PINS 6 ;
- clk1 + NET clk1 + DIRECTION INPUT + USE SIGNAL ;
- clk2 + NET clk2 + DIRECTION INPUT + USE SIGNAL ;
- clk3 + NET clk3 + DIRECTION INPUT + USE SIGNAL ;
- in1 + NET in1 + DIRECTION INPUT + USE SIGNAL ;
- in2 + NET in2 + DIRECTION INPUT + USE SIGNAL ;
- out + NET out + DIRECTION OUTPUT + USE SIGNAL ;
END PINS
NETS 10 ;
- clk1 ( PIN clk1 ) ( r1 CK ) + USE SIGNAL ;
- clk2 ( PIN clk2 ) ( r2 CK ) + USE SIGNAL ;
- clk3 ( PIN clk3 ) ( r3 CK ) + USE SIGNAL ;
- in1 ( PIN in1 ) ( r1 D ) + USE SIGNAL ;
- in2 ( PIN in2 ) ( r2 D ) + USE SIGNAL ;
- out ( PIN out ) ( r3 Q ) + USE SIGNAL ;
- r1q ( u2 A1 ) ( r1 Q ) + USE SIGNAL ;
- r2q ( u1 A ) ( r2 Q ) + USE SIGNAL ;
- u1z ( u2 A2 ) ( u1 Z ) + USE SIGNAL ;
- u2z ( u2 ZN ) ( r3 D ) + USE SIGNAL ;
END NETS
END DESIGN
test/get_core_die_areas.ok 0 → 100644
[INFO ODB-0222] Reading LEF file: Nangate45/Nangate45.lef
[INFO ODB-0223] Created 22 technology layers
[INFO ODB-0224] Created 27 technology vias
[INFO ODB-0225] Created 135 library cells
[INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef
[INFO ODB-0128] Design: top
[INFO ODB-0130] Created 6 pins.
[INFO ODB-0131] Created 5 components and 27 component-terminals.
[INFO ODB-0133] Created 10 nets and 14 connections.
0.0 0.0 510.14 255.07
199.88 99.4 210.14 105.0
test/get_core_die_areas.tcl 0 → 100644
# check accessors for die and core area in microns
source "helpers.tcl"
read_lef Nangate45/Nangate45.lef
read_liberty Nangate45/Nangate45_typ.lib
read_def get_core_die_areas.def
puts "[ord::get_die_area]"
puts "[ord::get_core_area]"
test/helpers.py 0 → 100644
import odb
import os
import utl
def make_rect(design, xl, yl, xh, yh):
xl = design.micronToDBU(xl)
yl = design.micronToDBU(yl)
xh = design.micronToDBU(xh)
yh = design.micronToDBU(yh)
return odb.Rect(xl, yl, xh, yh)
def make_result_file(filename):
result_dir = os.path.join(os.getcwd(), 'results')
if not os.path.exists(result_dir):
os.mkdir(result_dir)
root_ext = os.path.splitext(filename)
filename = "{}-py{}".format(*root_ext)
return os.path.join(result_dir, filename)
def diff_files(file1, file2):
with open(file1, 'r') as f:
lines1 = f.readlines()
with open(file2, 'r') as f:
lines2 = f.readlines()
num_lines1 = len(lines1)
num_lines2 = len(lines2)
for i in range(min(num_lines1, num_lines2)):
if lines1[i] != lines2[i]:
print(f"Differences found at line {i}")
print(lines1[i])
print(lines2[i])
return 1
if num_lines1 != num_lines2:
print(f"Number of lines differs {num_lines1} vs {num_lines2}.")
return 1
print("No differences found.")
return 0
# Output voltage file is specified as ...
utl.suppress_message(utl.PSM, 2)
# Output current file specified ...
utl.suppress_message(utl.PSM, 3)
# Output spice file is specified as
utl.suppress_message(utl.PSM, 5)
# SPICE file is written at
utl.suppress_message(utl.PSM, 6)
# Reading DEF file
utl.suppress_message(utl.ODB, 127)
# Finished DEF file
utl.suppress_message(utl.ODB, 134)
test/helpers.tcl 0 → 100644
# Helper functions common to multiple regressions.
set test_dir [file dirname [file normalize [info script]]]
set result_dir [file join $test_dir "results"]
proc make_result_file { filename } {
variable result_dir
if { ![file exists $result_dir] } {
file mkdir $result_dir
}
set root [file rootname $filename]
set ext [file extension $filename]
set filename "$root-tcl$ext"
return [file join $result_dir $filename]
}
# puts [exec cat $file] without forking.
proc report_file { file } {
set stream [open $file r]
while { [gets $stream line] >= 0 } {
puts $line
}
close $stream
}
proc diff_files { file1 file2 } {
set stream1 [open $file1 r]
set stream2 [open $file2 r]
set line 1
set found_diff 0
set line1_length [gets $stream1 line1]
set line2_length [gets $stream2 line2]
while { $line1_length >= 0 && $line2_length >= 0 } {
if { $line1 != $line2 } {
set found_diff 1
break
}
incr line
set line1_length [gets $stream1 line1]
set line2_length [gets $stream2 line2]
}
close $stream1
close $stream2
if { $found_diff || $line1_length != $line2_length} {
puts "Differences found at line $line."
puts "$line1"
puts "$line2"
return 1
} else {
puts "No differences found."
return 0
}
}
# Output voltage file is specified as ...
suppress_message PSM 2
# Output current file specified ...
suppress_message PSM 3
# Output spice file is specified as
suppress_message PSM 5
# SPICE file is written at
suppress_message PSM 6
# Reading DEF file
suppress_message ODB 127
# Finished DEF file
suppress_message ODB 134
test/ibex_sky130hd.metrics 0 → 100644
{
"IFP::ord_version": "",
"IFP::instance_count": "15696",
"floorplan__design__io": 264,
"design__instance__displacement__total": 35306.7980,
"design__instance__displacement__mean": 0.2650,
"design__instance__displacement__max": 24.6620,
"route__wirelength__estimated": 1127004.0280,
"RSZ::repair_design_buffer_count": "530",
"RSZ::max_slew_slack": "28.16686234651901",
"RSZ::max_fanout_slack": "100.0",
"RSZ::max_capacitance_slack": "84.4983050787515",
"design__instance__displacement__total": 734.8280,
"design__instance__displacement__mean": 0.0050,
"design__instance__displacement__max": 10.0430,
"route__wirelength__estimated": 1159085.4730,
"design__instance__count__hold_buffer": 823,
"RSZ::worst_slack_min": "-0.047005067835183836",
"RSZ::worst_slack_max": "-4.764350826488901",
"RSZ::tns_max": "-1707.695380994691",
"RSZ::hold_buffer_count": "823",
"design__instance__displacement__total": 4331.0210,
"design__instance__displacement__mean": 0.0320,
"design__instance__displacement__max": 23.7300,
"route__wirelength__estimated": 1232969.9150,
"DPL::utilization": "3.6",
"DPL::design_area": "321871",
"design__violations": 0,
"route__net": 16370,
"route__net__special": 2,
"GRT::ANT::errors": "375",
"route__drc_errors__iter:1": 12092,
"route__wirelength__iter:1": 1480601,
"route__drc_errors__iter:2": 2551,
"route__wirelength__iter:2": 1474891,
"route__drc_errors__iter:3": 2079,
"route__wirelength__iter:3": 1472545,
"route__drc_errors__iter:4": 276,
"route__wirelength__iter:4": 1472338,
"route__drc_errors__iter:5": 96,
"route__wirelength__iter:5": 1472297,
"route__drc_errors__iter:6": 47,
"route__wirelength__iter:6": 1472257,
"route__drc_errors__iter:7": 23,
"route__wirelength__iter:7": 1472279,
"route__drc_errors__iter:8": 6,
"route__wirelength__iter:8": 1472267,
"route__drc_errors__iter:9": 6,
"route__wirelength__iter:9": 1472269,
"route__drc_errors__iter:10": 0,
"route__wirelength__iter:10": 1472267,
"route__drc_errors": 0,
"route__wirelength": 1472267,
"route__vias": 136232,
"route__vias__singlecut": 136232,
"route__vias__multicut": 0,
"DRT::drv": "0",
"DRT::ANT::errors": "348",
"DRT::worst_slack_min": "0.053947514649115666",
"DRT::worst_slack_max": "-5.297661126394565",
"DRT::tns_max": "-2305.0118413060486",
"DRT::clock_skew": "3.729098912991708",
"DRT::max_slew_slack": "-6.491149784663451",
"DRT::max_fanout_slack": "100.0",
"DRT::max_capacitance_slack": "-7.024823736426623",
"DRT::clock_period": "15.155000"
}
\ No newline at end of file
test/ibex_sky130hd.metrics_limits 0 → 100644
{
"IFP::instance_count" : "18835.2"
,"DPL::design_area" : "386245.2"
,"DPL::utilization" : "4.32"
,"RSZ::repair_design_buffer_count" : "636"
,"RSZ::max_slew_slack" : "0"
,"RSZ::max_capacitance_slack" : "0"
,"RSZ::max_fanout_slack" : "0"
,"RSZ::worst_slack_min" : "-1.562505067835184"
,"RSZ::worst_slack_max" : "-6.279850826488901"
,"RSZ::tns_max" : "-4086.4241809946916"
,"RSZ::hold_buffer_count" : "987"
,"GRT::ANT::errors" : "375"
,"DRT::drv" : "0"
,"DRT::worst_slack_min" : "-1.4615524853508843"
,"DRT::worst_slack_max" : "-6.813161126394565"
,"DRT::tns_max" : "-4683.740641306049"
,"DRT::clock_skew" : "4.474918695590049"
,"DRT::max_slew_slack" : "-7.78937974159614"
,"DRT::max_capacitance_slack" : "-8.429788483711947"
,"DRT::max_fanout_slack" : "0"
,"DRT::clock_period" : "15.155"
}
test/ibex_sky130hd.sdc 0 → 100644
create_clock -name core_clock -period 15.155 [get_ports clk_i]
set_all_input_output_delays
test/ibex_sky130hd.tcl 0 → 100644
# ibex sky130hd
source "helpers.tcl"
source "flow_helpers.tcl"
source "sky130hd/sky130hd.vars"
set design "ibex"
set top_module "ibex_core"
set synth_verilog "ibex_sky130hd.v"
set sdc_file "ibex_sky130hd.sdc"
set die_area {0 0 3000.08 2999.8}
set core_area {10.07 11.2 2990.01 2990}
set slew_margin 30
set cap_margin 25
source -echo "flow.tcl"
test/ibex_sky130hd.v 0 → 100644
This source diff could not be displayed because it is too large. You can view the blob instead.
test/ibex_sky130hs.metrics 0 → 100644
{
"IFP::ord_version" : ""
, "IFP::instance_count" : "13935"
, "RSZ::repair_design_buffer_count" : "807"
, "RSZ::max_slew_slack" : "30.75997233390808"
, "RSZ::max_fanout_slack" : "100.0"
, "RSZ::max_capacitance_slack" : "55.91200229060346"
, "RSZ::worst_slack_min" : "0.00025424107982958966"
, "RSZ::worst_slack_max" : "-0.8163345785965204"
, "RSZ::tns_max" : "-70.80616116064495"
, "RSZ::hold_buffer_count" : "4102"
, "DPL::utilization" : "5.0"
, "DPL::design_area" : "446475"
, "GRT::ANT::errors" : "0"
, "drt::wire length::total" : 1592711
, "drt::vias::total" : 135585
, "DRT::drv" : "0"
, "DRT::worst_slack_min" : "-0.05670397645261307"
, "DRT::worst_slack_max" : "-1.0639311954804151"
, "DRT::tns_max" : "-92.065522256142"
, "DRT::clock_skew" : "3.163785101228473"
, "DRT::max_slew_slack" : "10.246986895799637"
, "DRT::max_fanout_slack" : "100.0"
, "DRT::max_capacitance_slack" : "9.187145756817577"
, "DRT::clock_period" : "11.290000"
}
test/ibex_sky130hs.metrics_limits 0 → 100644
{
"IFP::instance_count" : "16722.0"
,"DPL::design_area" : "535770.0"
,"DPL::utilization" : "6.0"
,"RSZ::repair_design_buffer_count" : "968"
,"RSZ::max_slew_slack" : "0"
,"RSZ::max_capacitance_slack" : "0"
,"RSZ::max_fanout_slack" : "0"
,"RSZ::worst_slack_min" : "-1.1287457589201704"
,"RSZ::worst_slack_max" : "-1.9453345785965204"
,"RSZ::tns_max" : "-1644.067661160645"
,"RSZ::hold_buffer_count" : "4922"
,"GRT::ANT::errors" : "400"
,"DRT::drv" : "0"
,"DRT::worst_slack_min" : "-1.1857039764526132"
,"DRT::worst_slack_max" : "-2.192931195480415"
,"DRT::tns_max" : "-1665.327022256142"
,"DRT::clock_skew" : "3.7965421214741673"
,"DRT::max_slew_slack" : "-3"
,"DRT::max_capacitance_slack" : "-3"
,"DRT::max_fanout_slack" : "0"
,"DRT::clock_period" : "11.29"
}
test/ibex_sky130hs.sdc 0 → 100644
create_clock -name core_clock -period 11.29 [get_ports clk_i]
set_all_input_output_delays
test/ibex_sky130hs.tcl 0 → 100644
# ibex sky130hs
source "helpers.tcl"
source "flow_helpers.tcl"
source "sky130hs/sky130hs.vars"
set design "ibex"
set top_module "ibex_core"
set synth_verilog "ibex_sky130hs.v"
set sdc_file "ibex_sky130hs.sdc"
set die_area {0 0 3000.08 2999.8}
set core_area {10.07 11.2 2990.01 2990}
set slew_margin 30
set cap_margin 25
source -echo "flow.tcl"
test/ibex_sky130hs.v 0 → 100644
This source diff could not be displayed because it is too large. You can view the blob instead.
test/jpeg_sky130hd.metrics 0 → 100644
{
"IFP::ord_version" : ""
, "IFP::instance_count" : "45634"
, "RSZ::repair_design_buffer_count" : "332"
, "RSZ::max_slew_slack" : "24.9099957463552"
, "RSZ::max_fanout_slack" : "100.0"
, "RSZ::max_capacitance_slack" : "78.64325756295086"
, "RSZ::worst_slack_min" : "0.0018975932473569198"
, "RSZ::worst_slack_max" : "-0.9094156796136068"
, "RSZ::tns_max" : "-96.7951222127989"
, "RSZ::hold_buffer_count" : "141"
, "DPL::utilization" : "7.1"
, "DPL::design_area" : "632876"
, "GRT::ANT::errors" : "0"
, "drt::wire length::total" : 2228768
, "drt::vias::total" : 315031
, "DRT::drv" : "0"
, "DRT::worst_slack_min" : "0.07309797418709191"
, "DRT::worst_slack_max" : "-1.1343903915079483"
, "DRT::tns_max" : "-125.10782097742039"
, "DRT::clock_skew" : "0.9025287439524763"
, "DRT::max_slew_slack" : "-7.817331949869792"
, "DRT::max_fanout_slack" : "100.0"
, "DRT::max_capacitance_slack" : "9.517641866627246"
, "DRT::clock_period" : "8.000000"
}
test/jpeg_sky130hd.metrics_limits 0 → 100644
{
"IFP::instance_count" : "54760.799999999996"
,"DPL::design_area" : "759681.6"
,"DPL::utilization" : "8.52"
,"RSZ::repair_design_buffer_count" : "393"
,"RSZ::max_slew_slack" : "0"
,"RSZ::max_capacitance_slack" : "0"
,"RSZ::max_fanout_slack" : "0"
,"RSZ::worst_slack_min" : "-0.7784141551663286"
,"RSZ::worst_slack_max" : "-1.614215384827181"
,"RSZ::tns_max" : "-3749.6645495764005"
,"RSZ::hold_buffer_count" : "121"
,"GRT::ANT::errors" : "309"
,"DRT::drv" : "0"
,"DRT::worst_slack_min" : "-0.6796491561916197"
,"DRT::worst_slack_max" : "-1.8284609011081026"
,"DRT::tns_max" : "-3774.0935140080737"
,"DRT::clock_skew" : "1.0351767736007609"
,"DRT::max_slew_slack" : "-0.34976467490196234"
,"DRT::max_capacitance_slack" : "0"
,"DRT::max_fanout_slack" : "0"
,"DRT::clock_period" : "8.0"
}
test/jpeg_sky130hd.sdc 0 → 100644
create_clock -name clk -period 8.0 [get_ports clk]
set_all_input_output_delays
test/jpeg_sky130hd.tcl 0 → 100644
# jpeg sky130hs 96017 insts
source "helpers.tcl"
source "flow_helpers.tcl"
source "sky130hd/sky130hd.vars"
set design "jpeg"
set top_module "jpeg_encoder"
set synth_verilog "jpeg_sky130hd.v"
set sdc_file "jpeg_sky130hd.sdc"
# These values must be multiples of placement site
set die_area {0 0 3000.04 2999.8}
set core_area {10.07 9.8 2989.97 2990}
set slew_margin 20
set cap_margin 20
source -echo "flow.tcl"
test/jpeg_sky130hd.v 0 → 100644
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test/jpeg_sky130hs.metrics_limits 0 → 100644
{
"IFP::instance_count" : "59841.6"
,"DPL::design_area" : "1066203.5999999999"
,"DPL::utilization" : "12.0"
,"RSZ::repair_design_buffer_count" : "652"
,"RSZ::max_slew_slack" : "0"
,"RSZ::max_capacitance_slack" : "0"
,"RSZ::max_fanout_slack" : "0"
,"RSZ::worst_slack_min" : "-2.089076082509113"
,"RSZ::worst_slack_max" : "-0.6353355800510236"
,"RSZ::tns_max" : "-3185.0691600000005"
,"RSZ::hold_buffer_count" : "862"
,"GRT::ANT::errors" : "289"
,"DRT::drv" : "0"
,"DRT::worst_slack_min" : "-1.9128321691682397"
,"DRT::worst_slack_max" : "-2.136466397744737"
,"DRT::tns_max" : "-3646.8520623206887"
,"DRT::clock_skew" : "1.0944645499671986"
,"DRT::max_slew_slack" : "-14.339423775672913"
,"DRT::max_capacitance_slack" : "0"
,"DRT::max_fanout_slack" : "0"
,"DRT::clock_period" : "6.387"
}
test/jpeg_sky130hs.sdc 0 → 100644
create_clock -name clk -period 6.387 [get_ports clk]
set_all_input_output_delays
test/jpeg_sky130hs.tcl 0 → 100644
# jpeg sky130
source "helpers.tcl"
source "flow_helpers.tcl"
source "sky130hs/sky130hs.vars"
set design "jpeg"
set top_module "jpeg_encoder"
set synth_verilog "jpeg_sky130hs.v"
set sdc_file "jpeg_sky130hs.sdc"
# These values must be multiples of placement site
set die_area {0 0 3000.04 2999.8}
set core_area {10.07 9.8 2989.97 2990}
set slew_margin 20
set cap_margin 20
source -echo "flow.tcl"
test/jpeg_sky130hs.v 0 → 100644
This source diff could not be displayed because it is too large. You can view the blob instead.
test/pad.lef 0 → 100644
VERSION 5.8 ;
BUSBITCHARS "[]" ;
DIVIDERCHAR "/" ;
SITE IO_SITE
CLASS PAD ;
SIZE 1 BY 150 ;
END IO_SITE
MACRO PAD
CLASS PAD ;
ORIGIN 0 0 ;
SIZE 25 BY 100 ;
SYMMETRY X Y ;
SITE IO_SITE ;
PIN PAD
DIRECTION INOUT ;
USE SIGNAL ;
PORT
LAYER metal4 ;
RECT 1.15 0 28.85 0.5 ;
END
END PAD
PIN Y
DIRECTION OUTPUT ;
USE SIGNAL ;
PORT
LAYER metal4 ;
RECT 1.15 0 28.85 0.5 ;
END
END Y
PIN TRIEN
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER metal4 ;
RECT 1.15 0 28.85 0.5 ;
END
END TRIEN
PIN RXEN
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER metal4 ;
RECT 1.15 0 28.85 0.5 ;
END
END RXEN
PIN DATA
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER metal4 ;
RECT 1.15 0 28.85 0.5 ;
END
END DATA
PIN NDIN
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER metal4 ;
RECT 1.15 0 28.85 0.5 ;
END
END NDIN
END PAD
test/pad.lib 0 → 100644
This diff is collapsed. Click to expand it.
test/reg3.def 0 → 100644
# reg1 1 clock pin, placed
VERSION 5.8 ;
DIVIDERCHAR "/" ;
BUSBITCHARS "[]" ;
DESIGN reg1 ;
UNITS DISTANCE MICRONS 100 ;
DIEAREA ( 0 0 ) ( 40000 40000 ) ;
COMPONENTS 5 ;
- r1 DFF_X1 + PLACED ( 10000 20000 ) N ;
- r2 DFF_X1 + PLACED ( 20000 10000 ) N ;
- r3 DFF_X1 + PLACED ( 30000 30000 ) N ;
- u1 BUF_X1 + PLACED ( 40000 10000 ) N ;
- u2 AND2_X1 + PLACED ( 10000 40000 ) N ;
END COMPONENTS
PINS 3 ;
- in1 + NET in1 + DIRECTION INPUT + USE SIGNAL + FIXED ( 0 0 ) N + LAYER metal1 ( 0 0 ) ( 0 0 ) ;
- in2 + NET in2 + DIRECTION INPUT + USE SIGNAL + FIXED ( 0 0 ) N + LAYER metal1 ( 0 0 ) ( 0 0 ) ;
- clk + NET clk + DIRECTION INPUT + USE SIGNAL + FIXED ( 10000 3333 ) N + LAYER metal1 ( 0 0 ) ( 0 0 ) ;
- out + NET out + DIRECTION OUTPUT + USE SIGNAL + FIXED ( 3333 10000 ) N + LAYER metal1 ( 0 0 ) ( 0 0 ) ;
END PINS
SPECIALNETS 2 ;
- VSS ( * VSS )
+ USE GROUND ;
- VDD ( * VDD )
+ USE POWER ;
END SPECIALNETS
NETS 10 ;
- in1 ( PIN in1 ) ( r1 D ) + USE SIGNAL ;
- in2 ( PIN in2 ) ( r2 D ) + USE SIGNAL ;
- clk ( PIN clk ) ( r1 CK ) ( r2 CK ) ( r3 CK ) + USE SIGNAL ;
- r1q ( r1 Q ) ( u2 A1 ) + USE SIGNAL ;
- r2q ( r2 Q ) ( u1 A ) + USE SIGNAL ;
- u1z ( u2 A2 ) ( u1 Z ) + USE SIGNAL ;
- u2z ( u2 ZN ) ( r3 D ) + USE SIGNAL ;
- out ( r3 Q ) ( PIN out ) + USE SIGNAL ;
END NETS
END DESIGN
test/regression 0 → 100755
#!/bin/sh
# The next line is executed by /bin/sh, but not Tcl \
exec tclsh $0 ${1+"$@"}
###############################################################################
##
## BSD 3-Clause License
##
## Copyright (c) 2019, Parallax Software, Inc.
## All rights reserved.
##
## Redistribution and use in source and binary forms, with or without
## modification, are permitted provided that the following conditions are met:
##
## * Redistributions of source code must retain the above copyright notice, this
## list of conditions and the following disclaimer.
##
## * Redistributions in binary form must reproduce the above copyright notice,
## this list of conditions and the following disclaimer in the documentation
## and#or other materials provided with the distribution.
##
## * Neither the name of the copyright holder nor the names of its
## contributors may be used to endorse or promote products derived from
## this software without specific prior written permission.
##
## THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
## AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
## IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
## ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
## LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
## CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
## SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
## INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
## CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
## ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
## POSSIBILITY OF SUCH DAMAGE.
##
###############################################################################
# Usage: regression [openroad | openroad_test | flow | tool]...
# where tool is name of an openroad tool (see define_tool_scripts below).
# Directory containing tests.
set test_dir [file dirname [file normalize [info script]]]
set openroad_dir [file dirname $test_dir]
source [file join $test_dir "regression.tcl"]
source [file join $test_dir "regression_tests.tcl"]
proc define_tool_script { tool script } {
global tool_scripts
dict set tool_scripts [string tolower $tool] $script
}
# roughly flow order
define_tool_script "OpenDB" "src/odb/test/regression"
define_tool_script "dbSta" "src/dbSta/test/regression"
define_tool_script "stt" "src/stt/test/regression"
define_tool_script "ifp" "src/ifp/test/regression"
define_tool_script "tap" "src/tap/test/regression"
define_tool_script "ppl" "src/ppl/test/regression"
define_tool_script "pdn" "src/pdn/test/regression"
define_tool_script "pad" "src/pad/test/regression"
define_tool_script "mpl" "src/mpl/test/regression"
define_tool_script "mpl2" "src/mpl2/test/regression"
define_tool_script "par" "src/par/test/regression"
define_tool_script "gpl" "src/gpl/test/regression"
define_tool_script "rsz" "src/rsz/test/regression"
define_tool_script "cts" "src/cts/test/regression"
define_tool_script "dpl" "src/dpl/test/regression"
define_tool_script "dpo" "src/dpo/test/regression"
define_tool_script "grt" "src/grt/test/regression"
define_tool_script "ant" "src/ant/test/regression"
define_tool_script "rcx" "src/rcx/test/regression"
define_tool_script "psm" "src/psm/test/regression"
define_tool_script "drt" "src/drt/test/regression"
define_tool_script "rmp" "src/rmp/test/regression"
define_tool_script "utl" "src/utl/test/regression"
proc run_openroad_tests { } {
global tool_errors
puts "------------------------------------------------------"
puts "OpenROAD"
# Skip flow tests until triton route is installed on CI machines
incr tool_errors [regression_body "non_flow"]
}
proc run_tool_tests { tool } {
global tool_errors openroad_dir tool_scripts
puts "------------------------------------------------------"
puts $tool
set script [dict get $tool_scripts $tool]
set test [file join $openroad_dir $script]
if { ![file exists $test] } {
puts "Error: $script not found."
incr tool_errors
} elseif { [catch "exec $test >@stdout"] } {
incr tool_errors
}
}
proc run_flow_tests { } {
global tool_errors
puts "------------------------------------------------------"
puts "Flow"
set flow_tests [group_tests "flow"]
if { $flow_tests != {} } {
incr tool_errors [regression_body $flow_tests]
}
}
################################################################
set tool_errors 0
if { $argv == {} } {
# Run all tool Unit tests
dict for {tool script} $tool_scripts {
run_tool_tests $tool
}
run_openroad_tests
} else {
foreach arg $argv {
set arg [string tolower $arg]
set matched 0
# openroad
if { [string equal -nocase $arg "openroad"] } {
run_openroad_tests
set matched 1
}
# flow
if { [string equal -nocase $arg "flow"] } {
run_flow_tests
set matched 1
}
# <openroad_test>
set ord_tests {}
foreach test [group_tests "all"] {
if { [string match -nocase $arg $test] } {
lappend ord_tests $test
set matched 1
}
}
if { $ord_tests != {} } {
incr tool_errors [regression_body $ord_tests]
}
# <tool>
dict for {tool script} $tool_scripts {
if { [string match -nocase $arg $tool] } {
run_tool_tests $tool
set matched 1
}
}
if { !$matched } {
puts "$arg is not an openroad test or tool name."
incr tool_errors
}
}
}
puts "------------------------------------------------------"
if { $tool_errors } {
puts "Found $tool_errors tool regression failures."
} else {
puts "Passed all tool regressions."
}
exit $tool_errors
# Local Variables:
# mode:tcl
# End:
test/regression_tests.tcl 0 → 100644
record_tests {
error1
get_core_die_areas
}
define_test_group "non_flow" {
error1
get_core_die_areas
}
# Flow tests only check the last line in the log (pass/fail).
# Ordered by instance count.
record_flow_tests {
gcd_nangate45
gcd_sky130hd
gcd_sky130hs
ibex_sky130hd
ibex_sky130hs
aes_nangate45
aes_sky130hd
aes_sky130hs
tinyRocket_nangate45
jpeg_sky130hs
jpeg_sky130hd
}
# sidelined because drt blows chow
test/regression_vars.tcl 0 → 100644
###############################################################################
##
## BSD 3-Clause License
##
## Copyright (c) 2019, Parallax Software, Inc.
## All rights reserved.
##
## Redistribution and use in source and binary forms, with or without
## modification, are permitted provided that the following conditions are met:
##
## * Redistributions of source code must retain the above copyright notice, this
## list of conditions and the following disclaimer.
##
## * Redistributions in binary form must reproduce the above copyright notice,
## this list of conditions and the following disclaimer in the documentation
## and#or other materials provided with the distribution.
##
## * Neither the name of the copyright holder nor the names of its
## contributors may be used to endorse or promote products derived from
## this software without specific prior written permission.
##
## THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
## AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
## IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
## ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
## LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
## CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
## SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
## INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
## CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
## ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
## POSSIBILITY OF SUCH DAMAGE.
##
###############################################################################
# regression.tcl variables for OpenROAD.
# Application program to run tests on.
set app "openroad"
set app_path [file join $openroad_dir "build" "src" $app]
# Application options.
set app_options "-no_init -no_splash -exit"
# Log files for each test are placed in result_dir.
set result_dir [file join $test_dir "results"]
# Collective diffs.
set diff_file [file join $result_dir "diffs"]
# File containing list of failed tests.
set failure_file [file join $result_dir "failures"]
# Use the DIFF_OPTIONS envar to change the diff options
# (Solaris diff doesn't support this envar)
set diff_options "-c"
if [info exists env(DIFF_OPTIONS)] {
set diff_options $env(DIFF_OPTIONS)
}
set valgrind_suppress [file join $openroad_dir "test" valgrind.suppress]
set valgrind_options "--num-callers=20 --leak-check=full --freelist-vol=100000000 --leak-resolution=high --suppressions=$valgrind_suppress"
if { [exec "uname"] == "Darwin" } {
append valgrind_options " --dsymutil=yes"
}
proc cleanse_logfile { test log_file } {
# Nothing to be done here.
}
################################################################
# Record tests in the /test directory.
# Compare results/<test>.log to <test>.ok for pass/fail.
proc record_tests { tests } {
record_tests1 $tests "compare_logfile"
}
# Record tests in the /test directory.
# Last line of results/<test>.log should be pass/fail.
proc record_pass_fail_tests { tests } {
record_tests1 $tests "pass_fail"
}
proc record_flow_tests { tests } {
record_tests1 $tests "check_metrics"
define_test_group "flow" $tests
}
proc record_tests1 { tests cmp_logfile } {
global test_dir
foreach test $tests {
# Prune commented tests from the list.
if { [string index $test 0] != "#" } {
record_test $test $test_dir $cmp_logfile
}
}
}
# Record a test in the regression suite.
proc record_test { test cmd_dir pass_criteria } {
global cmd_dirs test_groups test_pass_criteria test_langs
set cmd_dirs($test) $cmd_dir
lappend test_groups(all) $test
set test_pass_criteria($test) $pass_criteria
set test_langs($test) [list]
if {[file exists [file join $cmd_dir "$test.tcl"]]} {
lappend test_langs($test) tcl
}
if {[file exists [file join $cmd_dir "$test.py"]]} {
lappend test_langs($test) py
}
return $test
}
################################################################
proc define_test_group { group tests } {
global test_groups
set test_groups($group) $tests
}
proc group_tests { group } {
global test_groups
if { [info exists test_groups($group)] } {
return $test_groups($group)
} else {
return {}
}
}
# Clear the test lists.
proc clear_tests {} {
global test_groups
unset test_groups
}
proc list_delete { list delete } {
set result {}
foreach item $list {
if { [lsearch $delete $item] == -1 } {
lappend result $item
}
}
return $result
}
test/report_flow_metric_limits 0 → 100755
#!/bin/sh
# The next line is executed by /bin/sh, but not Tcl \
exec tclsh $0 ${1+"$@"}
# Directory containing tests.
set test_dir [file dirname [file normalize [info script]]]
set openroad_dir [file dirname $test_dir]
source [file join $test_dir "regression.tcl"]
source [file join $test_dir "regression_tests.tcl"]
source [file join $test_dir "flow_metrics.tcl"]
report_flow_metric_limits_main
# Local Variables:
# mode:tcl
# End:
test/report_flow_metrics 0 → 100755
#!/bin/sh
# The next line is executed by /bin/sh, but not Tcl \
exec tclsh $0 ${1+"$@"}
# Directory containing tests.
set test_dir [file dirname [file normalize [info script]]]
set openroad_dir [file dirname $test_dir]
source [file join $test_dir "regression.tcl"]
source [file join $test_dir "regression_tests.tcl"]
source [file join $test_dir "flow_metrics.tcl"]
report_flow_metrics_main
# Local Variables:
# mode:tcl
# End:
test/save_flow_metrics 0 → 100755
#! /bin/sh
# The next line is executed by /bin/sh, but not Tcl \
exec tclsh $0 ${1+"$@"}
############################################################################
##
## Copyright (c) 2019, The Regents of the University of California
## All rights reserved.
##
## BSD 3-Clause License
##
## Redistribution and use in source and binary forms, with or without
## modification, are permitted provided that the following conditions are met:
##
## * Redistributions of source code must retain the above copyright notice, this
## list of conditions and the following disclaimer.
##
## * Redistributions in binary form must reproduce the above copyright notice,
## this list of conditions and the following disclaimer in the documentation
## and/or other materials provided with the distribution.
##
## * Neither the name of the copyright holder nor the names of its
## contributors may be used to endorse or promote products derived from
## this software without specific prior written permission.
##
## THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
## AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
## IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
## ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
## LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
## CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
## SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
## INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
## CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
## ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
## POSSIBILITY OF SUCH DAMAGE.
##
############################################################################
# Usage: save_flow_metrics | test1 [test2...]
# Directory containing tests.
set test_dir [file dirname [file normalize [info script]]]
set openroad_dir [file dirname $test_dir]
source [file join $test_dir "regression.tcl"]
source [file join $test_dir "regression_tests.tcl"]
source [file join $test_dir "flow_metrics.tcl"]
save_flow_metrics_main
# Local Variables:
# mode:tcl
# End:
test/save_flow_metrics_limits 0 → 100755
#! /bin/sh
# The next line is executed by /bin/sh, but not Tcl \
exec tclsh $0 ${1+"$@"}
############################################################################
##
## Copyright (c) 2019, The Regents of the University of California
## All rights reserved.
##
## BSD 3-Clause License
##
## Redistribution and use in source and binary forms, with or without
## modification, are permitted provided that the following conditions are met:
##
## * Redistributions of source code must retain the above copyright notice, this
## list of conditions and the following disclaimer.
##
## * Redistributions in binary form must reproduce the above copyright notice,
## this list of conditions and the following disclaimer in the documentation
## and/or other materials provided with the distribution.
##
## * Neither the name of the copyright holder nor the names of its
## contributors may be used to endorse or promote products derived from
## this software without specific prior written permission.
##
## THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
## AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
## IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
## ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
## LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
## CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
## SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
## INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
## CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
## ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
## POSSIBILITY OF SUCH DAMAGE.
##
############################################################################
# Usage: save_flow_metrics | test1 [test2...]
# Directory containing tests.
set test_dir [file dirname [file normalize [info script]]]
set openroad_dir [file dirname $test_dir]
source [file join $test_dir "regression.tcl"]
source [file join $test_dir "regression_tests.tcl"]
source [file join $test_dir "flow_metrics.tcl"]
save_flow_metric_limits_main
# Local Variables:
# mode:tcl
# End:
test/save_ok 0 → 100755
#!/bin/sh
# The next line is executed by /bin/sh, but not Tcl \
exec tclsh $0 ${1+"$@"}
###############################################################################
##
## BSD 3-Clause License
##
## Copyright (c) 2019, Parallax Software, Inc.
## All rights reserved.
##
## Redistribution and use in source and binary forms, with or without
## modification, are permitted provided that the following conditions are met:
##
## * Redistributions of source code must retain the above copyright notice, this
## list of conditions and the following disclaimer.
##
## * Redistributions in binary form must reproduce the above copyright notice,
## this list of conditions and the following disclaimer in the documentation
## and#or other materials provided with the distribution.
##
## * Neither the name of the copyright holder nor the names of its
## contributors may be used to endorse or promote products derived from
## this software without specific prior written permission.
##
## THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
## AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
## IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
## ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
## LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
## CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
## SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
## INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
## CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
## ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
## POSSIBILITY OF SUCH DAMAGE.
##
###############################################################################
# Usage: save_ok | test1 [test2...] | failures
# Where test1 is all or the name of a tcl script in /test
# Wildcard matching with '*' and '?' in test names is supported.
# Directory containing tests.
set test_dir [file dirname [file normalize [info script]]]
set openroad_dir [file dirname [file dirname [file dirname $test_dir]]]
source [file join $openroad_dir "test" "regression.tcl"]
source [file join $test_dir "regression_tests.tcl"]
save_ok_main
# Local Variables:
# mode:tcl
# End:
test/shared/regression 0 → 100755
#!/bin/sh
# The next line is executed by /bin/sh, but not Tcl \
exec tclsh $0 ${1+"$@"}
###############################################################################
##
## BSD 3-Clause License
##
## Copyright (c) 2019, Parallax Software, Inc.
## All rights reserved.
##
## Redistribution and use in source and binary forms, with or without
## modification, are permitted provided that the following conditions are met:
##
## * Redistributions of source code must retain the above copyright notice, this
## list of conditions and the following disclaimer.
##
## * Redistributions in binary form must reproduce the above copyright notice,
## this list of conditions and the following disclaimer in the documentation
## and/or other materials provided with the distribution.
##
## * Neither the name of the copyright holder nor the names of its
## contributors may be used to endorse or promote products derived from
## this software without specific prior written permission.
##
## THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
## AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
## IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
## ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
## LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
## CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
## SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
## INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
## CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
## ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
## POSSIBILITY OF SUCH DAMAGE.
##
###############################################################################
# Usage: regression [test1 [test2...]]
# Where test1 is all or the name of a tcl script in /test
# Wildcard matching with '*' and '?' in test names is supported.
# Directory containing tests.
set test_dir [file dirname [file normalize [info script]]]
set openroad_dir [file dirname [file dirname [file dirname $test_dir]]]
source [file join $openroad_dir "test" "regression.tcl"]
source [file join $test_dir "regression_tests.tcl"]
regression_main
# Local Variables:
# mode:tcl
# End:
test/sky130hd/sky130_fd_sc_hd__ff_n40C_1v95.lib 0 → 100644
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test/sky130hd/sky130_fd_sc_hd__ss_n40C_1v40.lib 0 → 100644
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test/sky130hd/sky130_fd_sc_hd__tt_025C_1v80.lib 0 → 100644
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test/sky130hd/sky130_fd_sc_hd_merged.lef 0 → 100644
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test/sky130hs/sky130_fd_sc_hs__tt_025C_1v80.lib 0 → 100644
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test/sky130hs/sky130_fd_sc_hs_merged.lef 0 → 100644
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test/sky130hvl/sky130_fd_sc_hvl_merged.lef 0 → 100644
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test/tinyRocket_nangate45.v 0 → 100644
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