the first init

3ae3eba4 · 尚浩然 · 3ae3eba4 · 3ae3eba4 · 3ae3eba4 · 3ae3eba4
Commit 3ae3eba4 authored Mar 08, 2022 by 尚浩然
259 changed files
--- a/ALU.v
+++ b/ALU.v
+`timescale 1ns / 1ps
+module ALU#(
+   parameter alu_ram   =  6'b000000,
+   parameter alu_add   =  6'b000001,
+   parameter alu_sub   =  6'b001010,
+   parameter alu_slt   =  6'b000010,
+   parameter alu_sltu  =  6'b000011,
+   parameter alu_sll   =  6'b000100,
+   parameter alu_srl   =  6'b000101,
+   parameter alu_sra   =  6'b000110,
+   parameter alu_xor   =  6'b000111,
+   parameter alu_or    =  6'b001000,
+   parameter alu_and   =  6'b001001,
+   parameter alu_nop   =  6'b111111,
+	parameter DATA_WIDTH=  32
+  )
+  (
+    input  [5 : 0]            opcode,
+    input  [DATA_WIDTH-1 : 0] oprand_a,
+    input  [DATA_WIDTH-1 : 0] oprand_b,
+    output reg [DATA_WIDTH-1 : 0] result
+  );
+  wire [4 : 0] shamt;
+  assign shamt = oprand_b[4 : 0];
+  //alu
+  always@(*)
+  begin
+    case(opcode)
+      alu_nop:  result = 32'h0;
+      alu_ram:  result = oprand_a + oprand_b;
+      alu_add:  result = $signed(oprand_a) + $signed(oprand_b);
+      alu_sub:  result = $signed(oprand_a) - $signed(oprand_b);
+      alu_slt:  if($signed(oprand_a) < $signed(oprand_b))//decoderbracherй?
+                  result = 1;
+                else
+                  result = 0;
+      alu_sltu: if(oprand_a < oprand_b)
+                  result = 1;
+                else
+                  result = 0;
+      alu_sll:  result = oprand_a << shamt;
+      alu_srl:  result = oprand_a >> shamt;
+      alu_sra:  result = $signed(oprand_a) >>> shamt;
+      alu_xor:  result = oprand_a ^ oprand_b;
+      alu_or:   result = oprand_a | oprand_b;
+      alu_and:  result = oprand_a & oprand_b;
+      default:  result = 32'h0;
+    endcase
+  end
+endmodule
--- a/AXI_BUS.v
+++ b/AXI_BUS.v
--- a/AXI_BUS_summary.html
+++ b/AXI_BUS_summary.html
+<HTML><HEAD><TITLE>Xilinx Design Summary</TITLE></HEAD>
+<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
+<TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
+<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
+<TD ALIGN=CENTER COLSPAN='4'><B>AXI_BUS Project Status</B></TD></TR>
+<TR ALIGN=LEFT>
+<TD BGCOLOR='#FFFF99'><B>Project File:</B></TD>
+<TD>RISCV_CPU.xise</TD>
+<TD BGCOLOR='#FFFF99'><b>Parser Errors:</b></TD>
+<TD> No Errors </TD>
+</TR>
+<TR ALIGN=LEFT>
+<TD BGCOLOR='#FFFF99'><B>Module Name:</B></TD>
+<TD>AXI_BUS</TD>
+<TD BGCOLOR='#FFFF99'><B>Implementation State:</B></TD>
+<TD>New</TD>
+</TR>
+<TR ALIGN=LEFT>
+<TD BGCOLOR='#FFFF99'><B>Target Device:</B></TD>
+<TD>xc3s500e-4vq100</TD>
+<TD BGCOLOR='#FFFF99'><UL><LI><B>Errors:</B></LI></UL></TD>
+<TD>&nbsp;</TD>
+</TR>
+<TR ALIGN=LEFT>
+<TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD><TD>ISE 14.7</TD>
+<TD BGCOLOR='#FFFF99'><UL><LI><B>Warnings:</B></LI></UL></TD>
+<TD>&nbsp;</TD>
+</TR>
+<TR ALIGN=LEFT>
+<TD BGCOLOR='#FFFF99'><B>Design Goal:</B></dif></TD>
+<TD>Balanced</TD>
+<TD BGCOLOR='#FFFF99'><UL><LI><B>Routing Results:</B></LI></UL></TD>
+<TD>
+&nbsp;</TD>
+</TR>
+<TR ALIGN=LEFT>
+<TD BGCOLOR='#FFFF99'><B>Design Strategy:</B></dif></TD>
+<TD><A HREF_DISABLED='Xilinx Default (unlocked)?&DataKey=Strategy'>Xilinx Default (unlocked)</A></TD>
+<TD BGCOLOR='#FFFF99'><UL><LI><B>Timing Constraints:</B></LI></UL></TD>
+<TD>&nbsp;</TD>
+</TR>
+<TR ALIGN=LEFT>
+<TD BGCOLOR='#FFFF99'><B>Environment:</B></dif></TD>
+<TD>&nbsp;</TD>
+<TD BGCOLOR='#FFFF99'><UL><LI><B>Final Timing Score:</B></LI></UL></TD>
+<TD>&nbsp;&nbsp;</TD>
+</TR>
+</TABLE>
+&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
+<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>Detailed Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DetailedReports"><B>[-]</B></a></TD></TR>
+<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD>
+<TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR>
+<TR ALIGN=LEFT><TD>Synthesis Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
+<TR ALIGN=LEFT><TD>Translation Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
+<TR ALIGN=LEFT><TD>Map Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
+<TR ALIGN=LEFT><TD>Place and Route Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
+<TR ALIGN=LEFT><TD>Power Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
+<TR ALIGN=LEFT><TD>Post-PAR Static Timing Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
+<TR ALIGN=LEFT><TD>Bitgen Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
+</TABLE>
+&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
+<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='3'><B>Secondary Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=SecondaryReports"><B>[-]</B></a></TD></TR>
+<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD COLSPAN='2'><B>Generated</B></TD></TR>
+<TR ALIGN=LEFT><TD><A HREF_DISABLED='E:/verilogtest/RISCV_CPU\isim.log'>ISIM Simulator Log</A></TD><TD>Current</TD><TD COLSPAN='2'>һ 3 7 15:48:26 2022</TD></TR>
+</TABLE>
+<br><center><b>Date Generated:</b> 03/08/2022 - 23:08:44</center>
+</BODY></HT
\ No newline at end of file
--- a/AXI_BUS_tb1.v
+++ b/AXI_BUS_tb1.v
+`timescale 1ns / 1ps
+////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer:
+//
+// Create Date:   08:56:13 03/01/2022
+// Design Name:   AXI_BUS
+// Module Name:   E:/verilogtest/RISCV_CPU/AXI_BUS_tb1.v
+// Project Name:  RISCV_CPU
+// Target Device:  
+// Tool versions:  
+// Description: 
+//
+// Verilog Test Fixture created by ISE for module: AXI_BUS
+//
+// Dependencies:
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+////////////////////////////////////////////////////////////////////////////////
+module AXI_BUS_tb1;
+	// Inputs
+	reg clk;
+	reg rst_n;
+	// Instantiate the Unit Under Test (UUT)
+	AXI_BUS uut (
+		.clk(clk), 
+		.rst_n(rst_n)
+	);
+	initial begin
+		// Initialize Inputs
+		clk = 0;
+		rst_n = 0;
+		// Wait 100 ns for global reset to finish
+		#10 rst_n = 1;
+		// Add stimulus here
+	end
+   always #5 clk = ~clk; 
+endmodule
--- a/AXI_BUS_tb1_beh.prj
+++ b/AXI_BUS_tb1_beh.prj
+verilog work "ROM.v"
+verilog work "Registers.v"
+verilog work "myreg.v"
+verilog work "mux4.v"
+verilog work "forward.v"
+verilog work "decoder.v"
+verilog work "ALU.v"
+verilog work "RAM.v"
+verilog work "NVDLA.v"
+verilog work "CPU.v"
+verilog work "RAM_CONTROL.v"
+verilog work "NVDLA_CONTROL.v"
+verilog work "CPU_CONTROL.v"
+verilog work "AXI_BUS.v"
+verilog work "AXI_BUS_tb1.v"
+verilog work "E:/ISE/14.7/ISE_DS/ISE//verilog/src/glbl.v"
--- a/AXI_BUS_tb1_isim_beh.exe
+++ b/AXI_BUS_tb1_isim_beh.exe
--- a/AXI_BUS_tb1_isim_beh.wdb
+++ b/AXI_BUS_tb1_isim_beh.wdb
--- a/AXI_BUS_tb1_isim_beh1.wdb
+++ b/AXI_BUS_tb1_isim_beh1.wdb
--- a/AXI_BUS_tb1_stx_beh.prj
+++ b/AXI_BUS_tb1_stx_beh.prj
+verilog isim_temp "ROM.v"
+verilog isim_temp "Registers.v"
+verilog isim_temp "myreg.v"
+verilog isim_temp "mux4.v"
+verilog isim_temp "forward.v"
+verilog isim_temp "decoder.v"
+verilog isim_temp "ALU.v"
+verilog isim_temp "RAM.v"
+verilog isim_temp "NVDLA.v"
+verilog isim_temp "CPU.v"
+verilog isim_temp "RAM_CONTROL.v"
+verilog isim_temp "NVDLA_CONTROL.v"
+verilog isim_temp "CPU_CONTROL.v"
+verilog isim_temp "AXI_BUS.v"
+verilog isim_temp "AXI_BUS_tb1.v"
+verilog isim_temp "E:/ISE/14.7/ISE_DS/ISE//verilog/src/glbl.v"
--- a/CPU.cmd_log
+++ b/CPU.cmd_log
+xst -intstyle ise -ifn "E:/verilogtest/RISCV_CPU/CPU.xst" -ofn "E:/verilogtest/RISCV_CPU/CPU.syr" 
+xst -intstyle ise -ifn "E:/verilogtest/RISCV_CPU/CPU.xst" -ofn "E:/verilogtest/RISCV_CPU/CPU.syr" 
+xst -intstyle ise -ifn "E:/verilogtest/RISCV_CPU/CPU.xst" -ofn "E:/verilogtest/RISCV_CPU/CPU.syr" 
+xst -intstyle ise -ifn "E:/verilogtest/RISCV_CPU/CPU.xst" -ofn "E:/verilogtest/RISCV_CPU/CPU.syr" 
+xst -intstyle ise -ifn "E:/verilogtest/RISCV_CPU/CPU.xst" -ofn "E:/verilogtest/RISCV_CPU/CPU.syr" 
+xst -intstyle ise -ifn "E:/verilogtest/RISCV_CPU/CPU.xst" -ofn "E:/verilogtest/RISCV_CPU/CPU.syr" 
--- a/CPU.lso
+++ b/CPU.lso
+work
--- a/CPU.prj
+++ b/CPU.prj
+verilog work "ROM.v"
+verilog work "Registers.v"
+verilog work "RAM.v"
+verilog work "myreg.v"
+verilog work "mux4.v"
+verilog work "forward.v"
+verilog work "decoder.v"
+verilog work "ALU.v"
+verilog work "CPU.v"
--- a/CPU.syr
+++ b/CPU.syr
+Release 14.7 - xst P.20131013 (nt64)
+Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.
+--> Parameter TMPDIR set to xst/projnav.tmp
+Total REAL time to Xst completion: 0.00 secs
+Total CPU time to Xst completion: 0.07 secs
+--> Parameter xsthdpdir set to xst
+Total REAL time to Xst completion: 0.00 secs
+Total CPU time to Xst completion: 0.07 secs
+--> Reading design: CPU.prj
+TABLE OF CONTENTS
+  1) Synthesis Options Summary
+  2) HDL Compilation
+  3) Design Hierarchy Analysis
+  4) HDL Analysis
+  5) HDL Synthesis
+     5.1) HDL Synthesis Report
+  6) Advanced HDL Synthesis
+     6.1) Advanced HDL Synthesis Report
+  7) Low Level Synthesis
+  8) Partition Report
+  9) Final Report
+	9.1) Device utilization summary
+	9.2) Partition Resource Summary
+	9.3) TIMING REPORT
+=========================================================================
+*                      Synthesis Options Summary                        *
+=========================================================================
+---- Source Parameters
+Input File Name                    : "CPU.prj"
+Input Format                       : mixed
+Ignore Synthesis Constraint File   : NO
+---- Target Parameters
+Output File Name                   : "CPU"
+Output Format                      : NGC
+Target Device                      : xc3s500e-4-vq100
+---- Source Options
+Top Module Name                    : CPU
+Automatic FSM Extraction           : YES
+FSM Encoding Algorithm             : Auto
+Safe Implementation                : No
+FSM Style                          : LUT
+RAM Extraction                     : Yes
+RAM Style                          : Auto
+ROM Extraction                     : Yes
+Mux Style                          : Auto
+Decoder Extraction                 : YES
+Priority Encoder Extraction        : Yes
+Shift Register Extraction          : YES
+Logical Shifter Extraction         : YES
+XOR Collapsing                     : YES
+ROM Style                          : Auto
+Mux Extraction                     : Yes
+Resource Sharing                   : YES
+Asynchronous To Synchronous        : NO
+Multiplier Style                   : Auto
+Automatic Register Balancing       : No
+---- Target Options
+Add IO Buffers                     : YES
+Global Maximum Fanout              : 100000
+Add Generic Clock Buffer(BUFG)     : 24
+Register Duplication               : YES
+Slice Packing                      : YES
+Optimize Instantiated Primitives   : NO
+Use Clock Enable                   : Yes
+Use Synchronous Set                : Yes
+Use Synchronous Reset              : Yes
+Pack IO Registers into IOBs        : Auto
+Equivalent register Removal        : YES
+---- General Options
+Optimization Goal                  : Speed
+Optimization Effort                : 1
+Keep Hierarchy                     : No
+Netlist Hierarchy                  : As_Optimized
+RTL Output                         : Yes
+Global Optimization                : AllClockNets
+Read Cores                         : YES
+Write Timing Constraints           : NO
+Cross Clock Analysis               : NO
+Hierarchy Separator                : /
+Bus Delimiter                      : <>
+Case Specifier                     : Maintain
+Slice Utilization Ratio            : 100
+BRAM Utilization Ratio             : 100
+Verilog 2001                       : YES
+Auto BRAM Packing                  : NO
+Slice Utilization Ratio Delta      : 5
+=========================================================================
+=========================================================================
+*                          HDL Compilation                              *
+=========================================================================
+Compiling verilog file "ROM.v" in library work
+Compiling verilog file "Registers.v" in library work
+Module <ROM> compiled
+Compiling verilog file "RAM.v" in library work
+Module <Registers> compiled
+Compiling verilog file "myreg.v" in library work
+Module <RAM> compiled
+Compiling verilog file "mux4.v" in library work
+Module <myreg> compiled
+Compiling verilog file "forward.v" in library work
+Module <mux4> compiled
+Compiling verilog file "decoder.v" in library work
+Module <forward> compiled
+Compiling verilog file "ALU.v" in library work
+Module <decoder> compiled
+Compiling verilog file "CPU.v" in library work
+Module <ALU> compiled
+ERROR:HDLCompilers:27 - "CPU.v" line 293 Illegal redeclaration of 'ram_out_mem'
+Module <CPU> compiled
+Analysis of file <"CPU.prj"> failed.
+--> 
+Total memory usage is 4495300 kilobytes
+Number of errors   :    1 (   0 filtered)
+Number of warnings :    0 (   0 filtered)
+Number of infos    :    0 (   0 filtered)
--- a/CPU.v
+++ b/CPU.v
--- a/CPU.xst
+++ b/CPU.xst
+set -tmpdir "xst/projnav.tmp"
+set -xsthdpdir "xst"
+run
+-ifn CPU.prj
+-ifmt mixed
+-ofn CPU
+-ofmt NGC
+-p xc3s500e-4-vq100
+-top CPU
+-opt_mode Speed
+-opt_level 1
+-iuc NO
+-keep_hierarchy No
+-netlist_hierarchy As_Optimized
+-rtlview Yes
+-glob_opt AllClockNets
+-read_cores YES
+-write_timing_constraints NO
+-cross_clock_analysis NO
+-hierarchy_separator /
+-bus_delimiter <>
+-case Maintain
+-slice_utilization_ratio 100
+-bram_utilization_ratio 100
+-verilog2001 YES
+-fsm_extract YES -fsm_encoding Auto
+-safe_implementation No
+-fsm_style LUT
+-ram_extract Yes
+-ram_style Auto
+-rom_extract Yes
+-mux_style Auto
+-decoder_extract YES
+-priority_extract Yes
+-shreg_extract YES
+-shift_extract YES
+-xor_collapse YES
+-rom_style Auto
+-auto_bram_packing NO
+-mux_extract Yes
+-resource_sharing YES
+-async_to_sync NO
+-mult_style Auto
+-iobuf YES
+-max_fanout 100000
+-bufg 24
+-register_duplication YES
+-register_balancing No
+-slice_packing YES
+-optimize_primitives NO
+-use_clock_enable Yes
+-use_sync_set Yes
+-use_sync_reset Yes
+-iob Auto
+-equivalent_register_removal YES
+-slice_utilization_ratio_maxmargin 5
--- a/CPU_CONTROL.v
+++ b/CPU_CONTROL.v
--- a/CPU_CONTROL_isim_beh.exe
+++ b/CPU_CONTROL_isim_beh.exe
--- a/CPU_CONTROL_stx_beh.prj
+++ b/CPU_CONTROL_stx_beh.prj
+verilog isim_temp "ROM.v"
+verilog isim_temp "Registers.v"
+verilog isim_temp "myreg.v"
+verilog isim_temp "mux4.v"
+verilog isim_temp "forward.v"
+verilog isim_temp "decoder.v"
+verilog isim_temp "ALU.v"
+verilog isim_temp "CPU.v"
+verilog isim_temp "CPU_CONTROL.v"
+verilog isim_temp "E:/ISE/14.7/ISE_DS/ISE//verilog/src/glbl.v"
--- a/CPU_CONTROL_summary.html
+++ b/CPU_CONTROL_summary.html
+<HTML><HEAD><TITLE>Xilinx Design Summary</TITLE></HEAD>
+<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
+<TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
+<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
+<TD ALIGN=CENTER COLSPAN='4'><B>CPU Project Status</B></TD></TR>
+<TR ALIGN=LEFT>
+<TD BGCOLOR='#FFFF99'><B>Project File:</B></TD>
+<TD>RISCV_CPU.xise</TD>
+<TD BGCOLOR='#FFFF99'><b>Parser Errors:</b></TD>
+<TD> No Errors </TD>
+</TR>
+<TR ALIGN=LEFT>
+<TD BGCOLOR='#FFFF99'><B>Module Name:</B></TD>
+<TD>CPU_CONTROL</TD>
+<TD BGCOLOR='#FFFF99'><B>Implementation State:</B></TD>
+<TD>New</TD>
+</TR>
+<TR ALIGN=LEFT>
+<TD BGCOLOR='#FFFF99'><B>Target Device:</B></TD>
+<TD>xc3s500e-4vq100</TD>
+<TD BGCOLOR='#FFFF99'><UL><LI><B>Errors:</B></LI></UL></TD>
+<TD>&nbsp;</TD>
+</TR>
+<TR ALIGN=LEFT>
+<TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD><TD>ISE 14.7</TD>
+<TD BGCOLOR='#FFFF99'><UL><LI><B>Warnings:</B></LI></UL></TD>
+<TD>&nbsp;</TD>
+</TR>
+<TR ALIGN=LEFT>
+<TD BGCOLOR='#FFFF99'><B>Design Goal:</B></dif></TD>
+<TD>Balanced</TD>
+<TD BGCOLOR='#FFFF99'><UL><LI><B>Routing Results:</B></LI></UL></TD>
+<TD>
+&nbsp;</TD>
+</TR>
+<TR ALIGN=LEFT>
+<TD BGCOLOR='#FFFF99'><B>Design Strategy:</B></dif></TD>
+<TD><A HREF_DISABLED='Xilinx Default (unlocked)?&DataKey=Strategy'>Xilinx Default (unlocked)</A></TD>
+<TD BGCOLOR='#FFFF99'><UL><LI><B>Timing Constraints:</B></LI></UL></TD>
+<TD>&nbsp;</TD>
+</TR>
+<TR ALIGN=LEFT>
+<TD BGCOLOR='#FFFF99'><B>Environment:</B></dif></TD>
+<TD>&nbsp;</TD>
+<TD BGCOLOR='#FFFF99'><UL><LI><B>Final Timing Score:</B></LI></UL></TD>
+<TD>&nbsp;&nbsp;</TD>
+</TR>
+</TABLE>
+&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
+<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>Detailed Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DetailedReports"><B>[-]</B></a></TD></TR>
+<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD>
+<TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR>
+<TR ALIGN=LEFT><TD>Synthesis Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
+<TR ALIGN=LEFT><TD>Translation Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
+<TR ALIGN=LEFT><TD>Map Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
+<TR ALIGN=LEFT><TD>Place and Route Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
+<TR ALIGN=LEFT><TD>Power Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
+<TR ALIGN=LEFT><TD>Post-PAR Static Timing Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
+<TR ALIGN=LEFT><TD>Bitgen Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
+</TABLE>
+&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
+<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='3'><B>Secondary Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=SecondaryReports"><B>[-]</B></a></TD></TR>
+<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD COLSPAN='2'><B>Generated</B></TD></TR>
+<TR ALIGN=LEFT><TD><A HREF_DISABLED='E:/verilogtest/RISCV_CPU\isim.log'>ISIM Simulator Log</A></TD><TD>Current</TD><TD COLSPAN='2'> 1 22 18:37:43 2022</TD></TR>
+</TABLE>
+<br><center><b>Date Generated:</b> 03/01/2022 - 08:38:31</center>
+</BODY></HT
\ No newline at end of file
--- a/CPU_envsettings.html
+++ b/CPU_envsettings.html
+<HTML><HEAD><TITLE>Xilinx System Settings Report</TITLE></HEAD>
+<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
+<center><big><big><b>System Settings</b></big></big></center><br>
+<A NAME="Environment Settings"></A>
+&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
+<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
+<TD ALIGN=CENTER COLSPAN='5'><B> Environment Settings </B></TD>
+</tr>
+<tr bgcolor='#ffff99'>
+<td><b>Environment Variable</b></td>
+<td><b>xst</b></td>
+<td><b>ngdbuild</b></td>
+<td><b>map</b></td>
+<td><b>par</b></td>
+</tr>
+<tr>
+<td>PATHEXT</td>
+<td>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH;<br>.MSC</td>
+<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
+<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
+<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
+</tr>
+<tr>
+<td>Path</td>
+<td>E:\ISE\14.7\ISE_DS\ISE\\lib\nt64;<br>E:\ISE\14.7\ISE_DS\ISE\\bin\nt64;<br>E:\ISE\14.7\ISE_DS\ISE\bin\nt64;<br>E:\ISE\14.7\ISE_DS\ISE\lib\nt64;<br>E:\ISE\14.7\ISE_DS\ISE\..\..\..\DocNav;<br>E:\ISE\14.7\ISE_DS\PlanAhead\bin;<br>E:\ISE\14.7\ISE_DS\EDK\bin\nt64;<br>E:\ISE\14.7\ISE_DS\EDK\lib\nt64;<br>E:\ISE\14.7\ISE_DS\EDK\gnu\microblaze\nt\bin;<br>E:\ISE\14.7\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;<br>E:\ISE\14.7\ISE_DS\EDK\gnuwin\bin;<br>E:\ISE\14.7\ISE_DS\EDK\gnu\arm\nt\bin;<br>E:\ISE\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_be\bin;<br>E:\ISE\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_le\bin;<br>E:\ISE\14.7\ISE_DS\common\bin\nt64;<br>E:\ISE\14.7\ISE_DS\common\lib\nt64;<br>C:\Program Files (x86)\VMware\VMware Player\bin\;<br>C:\Windows\system32;<br>C:\Windows;<br>C:\Windows\System32\Wbem;<br>C:\Windows\System32\WindowsPowerShell\v1.0\;<br>C:\Windows\System32\OpenSSH\;<br>C:\Program Files (x86)\Intel\Intel(R) Management Engine Components\DAL;<br>C:\Program Files\Intel\Intel(R) Management Engine Components\DAL;<br>E:\node.js\;<br>E:\matlabr2020b\runtime\win64;<br>E:\matlabr2020b\bin;<br>E:\matlabr2020b\polyspace\bin;<br>E:\minGW\x86_64-8.1.0-release-win32-seh-rt_v6-rev0\mingw64\bin;<br>C:\Users\PC\AppData\Local\Microsoft\WindowsApps;<br>E:\visual studio code\Microsoft VS Code\bin;<br>C:\Users\PC\AppData\Roaming\npm;<br>E:\modelsim\win64</td>
+<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
+<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
+<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
+</tr>
+<tr>
+<td>XILINX</td>
+<td>E:\ISE\14.7\ISE_DS\ISE\</td>
+<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
+<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
+<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
+</tr>
+<tr>
+<td>XILINX_DSP</td>
+<td>E:\ISE\14.7\ISE_DS\ISE</td>
+<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
+<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
+<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
+</tr>
+<tr>
+<td>XILINX_EDK</td>
+<td>E:\ISE\14.7\ISE_DS\EDK</td>
+<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
+<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
+<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
+</tr>
+<tr>
+<td>XILINX_PLANAHEAD</td>
+<td>E:\ISE\14.7\ISE_DS\PlanAhead</td>
+<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
+<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
+<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
+</tr>
+</TABLE>
+<A NAME="Synthesis Property Settings"></A>
+&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
+<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
+<TD ALIGN=CENTER COLSPAN='4'><B>Synthesis Property Settings </B></TD>
+</tr>
+<tr bgcolor='#ffff99'>
+<td><b>Switch Name</b></td>
+<td><b>Property Name</b></td>
+<td><b>Value</b></td>
+<td><b>Default Value</b></td>
+</tr>
+<tr>
+<td>-ifn</td>
+<td>&nbsp;</td>
+<td>CPU.prj</td>
+<td>&nbsp;</td>
+</tr>
+<tr>
+<td>-ifmt</td>
+<td>&nbsp;</td>
+<td>mixed</td>
+<td>MIXED</td>
+</tr>
+<tr>
+<td>-ofn</td>
+<td>&nbsp;</td>
+<td>CPU</td>
+<td>&nbsp;</td>
+</tr>
+<tr>
+<td>-ofmt</td>
+<td>&nbsp;</td>
+<td>NGC</td>
+<td>NGC</td>
+</tr>
+<tr>
+<td>-p</td>
+<td>&nbsp;</td>
+<td>xc3s500e-4-vq100</td>
+<td>&nbsp;</td>
+</tr>
+<tr>
+<td>-top</td>
+<td>&nbsp;</td>
+<td>CPU</td>
+<td>&nbsp;</td>
+</tr>
+<tr>
+<td>-opt_mode</td>
+<td>Optimization Goal</td>
+<td>Speed</td>
+<td>SPEED</td>
+</tr>
+<tr>
+<td>-opt_level</td>
+<td>Optimization Effort</td>
+<td>1</td>
+<td>1</td>
+</tr>
+<tr>
+<td>-iuc</td>
+<td>Use synthesis Constraints File</td>
+<td>NO</td>
+<td>NO</td>
+</tr>
+<tr>
+<td>-keep_hierarchy</td>
+<td>Keep Hierarchy</td>
+<td>No</td>
+<td>NO</td>
+</tr>
+<tr>
+<td>-netlist_hierarchy</td>
+<td>Netlist Hierarchy</td>
+<td>As_Optimized</td>
+<td>as_optimized</td>
+</tr>
+<tr>
+<td>-rtlview</td>
+<td>Generate RTL Schematic</td>
+<td>Yes</td>
+<td>NO</td>
+</tr>
+<tr>
+<td>-glob_opt</td>
+<td>Global Optimization Goal</td>
+<td>AllClockNets</td>
+<td>ALLCLOCKNETS</td>
+</tr>
+<tr>
+<td>-read_cores</td>
+<td>Read Cores</td>
+<td>YES</td>
+<td>YES</td>
+</tr>
+<tr>
+<td>-write_timing_constraints</td>
+<td>Write Timing Constraints</td>
+<td>NO</td>
+<td>NO</td>
+</tr>
+<tr>
+<td>-cross_clock_analysis</td>
+<td>Cross Clock Analysis</td>
+<td>NO</td>
+<td>NO</td>
+</tr>
+<tr>
+<td>-bus_delimiter</td>
+<td>Bus Delimiter</td>
+<td>&lt;&gt;</td>
+<td>&lt;&gt;</td>
+</tr>
+<tr>
+<td>-slice_utilization_ratio</td>
+<td>Slice Utilization Ratio</td>
+<td>100</td>
+<td>100%</td>
+</tr>
+<tr>
+<td>-bram_utilization_ratio</td>
+<td>BRAM Utilization Ratio</td>
+<td>100</td>
+<td>100%</td>
+</tr>
+<tr>
+<td>-verilog2001</td>
+<td>Verilog 2001</td>
+<td>YES</td>
+<td>YES</td>
+</tr>
+<tr>
+<td>-fsm_extract</td>
+<td>&nbsp;</td>
+<td>YES</td>
+<td>YES</td>
+</tr>
+<tr>
+<td>-fsm_encoding</td>
+<td>&nbsp;</td>
+<td>Auto</td>
+<td>AUTO</td>
+</tr>
+<tr>
+<td>-safe_implementation</td>
+<td>&nbsp;</td>
+<td>No</td>
+<td>NO</td>
+</tr>
+<tr>
+<td>-fsm_style</td>
+<td>&nbsp;</td>
+<td>LUT</td>
+<td>LUT</td>
+</tr>
+<tr>
+<td>-ram_extract</td>
+<td>&nbsp;</td>
+<td>Yes</td>
+<td>YES</td>
+</tr>
+<tr>
+<td>-ram_style</td>
+<td>&nbsp;</td>
+<td>Auto</td>
+<td>AUTO</td>
+</tr>
+<tr>
+<td>-rom_extract</td>
+<td>&nbsp;</td>
+<td>Yes</td>
+<td>YES</td>
+</tr>
+<tr>
+<td>-shreg_extract</td>
+<td>&nbsp;</td>
+<td>YES</td>
+<td>YES</td>
+</tr>
+<tr>
+<td>-rom_style</td>
+<td>&nbsp;</td>
+<td>Auto</td>
+<td>AUTO</td>
+</tr>
+<tr>
+<td>-auto_bram_packing</td>
+<td>&nbsp;</td>
+<td>NO</td>
+<td>NO</td>
+</tr>
+<tr>
+<td>-resource_sharing</td>
+<td>&nbsp;</td>
+<td>YES</td>
+<td>YES</td>
+</tr>
+<tr>
+<td>-async_to_sync</td>
+<td>&nbsp;</td>
+<td>NO</td>
+<td>NO</td>
+</tr>
+<tr>
+<td>-mult_style</td>
+<td>&nbsp;</td>
+<td>Auto</td>
+<td>AUTO</td>
+</tr>
+<tr>
+<td>-iobuf</td>
+<td>&nbsp;</td>
+<td>YES</td>
+<td>YES</td>
+</tr>
+<tr>
+<td>-max_fanout</td>
+<td>&nbsp;</td>
+<td>100000</td>
+<td>500</td>
+</tr>
+<tr>
+<td>-bufg</td>
+<td>&nbsp;</td>
+<td>24</td>
+<td>24</td>
+</tr>
+<tr>
+<td>-register_duplication</td>
+<td>&nbsp;</td>
+<td>YES</td>
+<td>YES</td>
+</tr>
+<tr>
+<td>-register_balancing</td>
+<td>&nbsp;</td>
+<td>No</td>
+<td>NO</td>
+</tr>
+<tr>
+<td>-optimize_primitives</td>
+<td>&nbsp;</td>
+<td>NO</td>
+<td>NO</td>
+</tr>
+<tr>
+<td>-use_clock_enable</td>
+<td>&nbsp;</td>
+<td>Yes</td>
+<td>YES</td>
+</tr>
+<tr>
+<td>-use_sync_set</td>
+<td>&nbsp;</td>
+<td>Yes</td>
+<td>YES</td>
+</tr>
+<tr>
+<td>-use_sync_reset</td>
+<td>&nbsp;</td>
+<td>Yes</td>
+<td>YES</td>
+</tr>
+<tr>
+<td>-iob</td>
+<td>&nbsp;</td>
+<td>Auto</td>
+<td>AUTO</td>
+</tr>
+<tr>
+<td>-equivalent_register_removal</td>
+<td>&nbsp;</td>
+<td>YES</td>
+<td>YES</td>
+</tr>
+<tr>
+<td>-slice_utilization_ratio_maxmargin</td>
+<td>&nbsp;</td>
+<td>5</td>
+<td>0%</td>
+</tr>
+</TABLE>
+<A NAME="Operating System Information"></A>
+&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
+<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
+<TD ALIGN=CENTER COLSPAN='5'><B> Operating System Information </B></TD>
+</tr>
+<tr bgcolor='#ffff99'>
+<td><b>Operating System Information</b></td>
+<td><b>xst</b></td>
+<td><b>ngdbuild</b></td>
+<td><b>map</b></td>
+<td><b>par</b></td>
+</tr>
+<tr>
+<td>CPU Architecture/Speed</td>
+<td>Intel(R) Core(TM) i7-8650U CPU @ 1.90GHz/2112 MHz</td>
+<td><font color=gray>&lt;&nbsp; data not available &nbsp;&gt;</font></td>
+<td><font color=gray>&lt;&nbsp; data not available &nbsp;&gt;</font></td>
+<td><font color=gray>&lt;&nbsp; data not available &nbsp;&gt;</font></td>
+</tr>
+<tr>
+<td>Host</td>
+<td>PC-20210820RYDZ</td>
+<td><font color=gray>&lt;&nbsp; data not available &nbsp;&gt;</font></td>
+<td><font color=gray>&lt;&nbsp; data not available &nbsp;&gt;</font></td>
+<td><font color=gray>&lt;&nbsp; data not available &nbsp;&gt;</font></td>
+</tr>
+<tr>
+<td>OS Name</td>
+<td>Microsoft , 64-bit</td>
+<td><font color=gray>&lt;&nbsp; data not available &nbsp;&gt;</font></td>
+<td><font color=gray>&lt;&nbsp; data not available &nbsp;&gt;</font></td>
+<td><font color=gray>&lt;&nbsp; data not available &nbsp;&gt;</font></td>
+</tr>
+<tr>
+<td>OS Release</td>
+<td>major release  (build 9200)</td>
+<td><font color=gray>&lt;&nbsp; data not available &nbsp;&gt;</font></td>
+<td><font color=gray>&lt;&nbsp; data not available &nbsp;&gt;</font></td>
+<td><font color=gray>&lt;&nbsp; data not available &nbsp;&gt;</font></td>
+</tr>
+</TABLE>
+</BODY> </HTML>
\ No newline at end of file
--- a/CPU_isim_beh.exe
+++ b/CPU_isim_beh.exe
--- a/CPU_stx_beh.prj
+++ b/CPU_stx_beh.prj
+verilog isim_temp "ROM.v"
+verilog isim_temp "Registers.v"
+verilog isim_temp "RAM.v"
+verilog isim_temp "myreg.v"
+verilog isim_temp "mux4.v"
+verilog isim_temp "forward.v"
+verilog isim_temp "decoder.v"
+verilog isim_temp "ALU.v"
+verilog isim_temp "CPU.v"
+verilog isim_temp "E:/ISE/14.7/ISE_DS/ISE//verilog/src/glbl.v"
--- a/CPU_summary.html
+++ b/CPU_summary.html
+<HTML><HEAD><TITLE>Xilinx Design Summary</TITLE></HEAD>
+<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
+<TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
+<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
+<TD ALIGN=CENTER COLSPAN='4'><B>CPU Project Status (01/22/2022 - 12:33:25)</B></TD></TR>
+<TR ALIGN=LEFT>
+<TD BGCOLOR='#FFFF99'><B>Project File:</B></TD>
+<TD>RISCV_CPU.xise</TD>
+<TD BGCOLOR='#FFFF99'><b>Parser Errors:</b></TD>
+<TD> No Errors </TD>
+</TR>
+<TR ALIGN=LEFT>
+<TD BGCOLOR='#FFFF99'><B>Module Name:</B></TD>
+<TD>CPU</TD>
+<TD BGCOLOR='#FFFF99'><B>Implementation State:</B></TD>
+<TD>Synthesized</TD>
+</TR>
+<TR ALIGN=LEFT>
+<TD BGCOLOR='#FFFF99'><B>Target Device:</B></TD>
+<TD>xc3s500e-4vq100</TD>
+<TD BGCOLOR='#FFFF99'><UL><LI><B>Errors:</B></LI></UL></TD>
+<TD>
+<font color="red"; face="Arial"><b>X </b></font>
+<A HREF_DISABLED='E:/verilogtest/RISCV_CPU\_xmsgs/*.xmsgs?&DataKey=Error'>1 Error (0 new)</A></TD>
+</TR>
+<TR ALIGN=LEFT>
+<TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD><TD>ISE 14.7</TD>
+<TD BGCOLOR='#FFFF99'><UL><LI><B>Warnings:</B></LI></UL></TD>
+<TD ALIGN=LEFT>No Warnings</TD>
+</TR>
+<TR ALIGN=LEFT>
+<TD BGCOLOR='#FFFF99'><B>Design Goal:</B></dif></TD>
+<TD>Balanced</TD>
+<TD BGCOLOR='#FFFF99'><UL><LI><B>Routing Results:</B></LI></UL></TD>
+<TD>
+&nbsp;</TD>
+</TR>
+<TR ALIGN=LEFT>
+<TD BGCOLOR='#FFFF99'><B>Design Strategy:</B></dif></TD>
+<TD><A HREF_DISABLED='Xilinx Default (unlocked)?&DataKey=Strategy'>Xilinx Default (unlocked)</A></TD>
+<TD BGCOLOR='#FFFF99'><UL><LI><B>Timing Constraints:</B></LI></UL></TD>
+<TD>&nbsp;</TD>
+</TR>
+<TR ALIGN=LEFT>
+<TD BGCOLOR='#FFFF99'><B>Environment:</B></dif></TD>
+<TD>
+<A HREF_DISABLED='E:/verilogtest/RISCV_CPU\CPU_envsettings.html'>
+System Settings</A>
+</TD>
+<TD BGCOLOR='#FFFF99'><UL><LI><B>Final Timing Score:</B></LI></UL></TD>
+<TD>&nbsp;&nbsp;</TD>
+</TR>
+</TABLE>
+&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
+<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>Detailed Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DetailedReports"><B>[-]</B></a></TD></TR>
+<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD>
+<TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR>
+<TR ALIGN=LEFT><TD><A HREF_DISABLED='E:/verilogtest/RISCV_CPU\CPU.syr'>Synthesis Report</A></TD><TD>Current</TD><TD> 1 22 12:35:36 2022</TD><TD ALIGN=LEFT><font color="red"; face="Arial"><b>X </b></font><A HREF_DISABLED='E:/verilogtest/RISCV_CPU\_xmsgs/xst.xmsgs?&DataKey=Error'>1 Error (0 new)</A></TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
+<TR ALIGN=LEFT><TD>Translation Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
+<TR ALIGN=LEFT><TD>Map Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
+<TR ALIGN=LEFT><TD>Place and Route Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
+<TR ALIGN=LEFT><TD>Power Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
+<TR ALIGN=LEFT><TD>Post-PAR Static Timing Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
+<TR ALIGN=LEFT><TD>Bitgen Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
+</TABLE>
+&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
+<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='3'><B>Secondary Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=SecondaryReports"><B>[-]</B></a></TD></TR>
+<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD COLSPAN='2'><B>Generated</B></TD></TR>
+<TR ALIGN=LEFT><TD><A HREF_DISABLED='E:/verilogtest/RISCV_CPU\isim.log'>ISIM Simulator Log</A></TD><TD>Current</TD><TD COLSPAN='2'> 1 22 18:37:43 2022</TD></TR>
+</TABLE>
+<br><center><b>Date Generated:</b> 03/01/2022 - 08:38:30</center>
+</BODY><
\ No newline at end of file
--- a/CPU_tb1.v
+++ b/CPU_tb1.v
+`timescale 1ns / 1ps
+module CPU_tb1;
+	// Inputs
+	reg clk;
+	// Instantiate the Unit Under Test (UUT)
+	CPU uut (
+		.clk(clk)
+	);
+	initial begin
+		// Initialize Inputs
+		clk = 0;
+		// Wait 100 ns for global reset to finish
+		// Add stimulus here
+	end
+   always #10 clk=~clk;   
+endmodule
--- a/CPU_tb1_isim_beh.exe
+++ b/CPU_tb1_isim_beh.exe
--- a/CPU_tb1_isim_beh1.wdb
+++ b/CPU_tb1_isim_beh1.wdb
--- a/CPU_tb1_stx_beh.prj
+++ b/CPU_tb1_stx_beh.prj
+verilog isim_temp "ROM.v"
+verilog isim_temp "Registers.v"
+verilog isim_temp "RAM.v"
+verilog isim_temp "myreg.v"
+verilog isim_temp "mux4.v"
+verilog isim_temp "forward.v"
+verilog isim_temp "decoder.v"
+verilog isim_temp "ALU.v"
+verilog isim_temp "CPU.v"
+verilog isim_temp "CPU_tb1.v"
+verilog isim_temp "E:/ISE/14.7/ISE_DS/ISE//verilog/src/glbl.v"
--- a/CPU_tb1_stx_translate.prj
+++ b/CPU_tb1_stx_translate.prj
+verilog isim_temp "CPU_tb1.v"
--- a/CPU_xst.xrpt
+++ b/CPU_xst.xrpt
+<?xml version="1.0" encoding="UTF-8" standalone="yes" ?>
+<document OS="nt64" product="ISE" version="14.7">
+  <!--The data in this file is primarily intended for consumption by Xilinx tools.
+    The structure and the elements are likely to change over the next few releases.
+    This means code written to parse this file will need to be revisited each subsequent release.-->
+  <application stringID="Xst" timeStamp="Sat Jan 22 12:35:35 2022">
+    <section stringID="User_Env">
+      <table stringID="User_EnvVar">
+        <column stringID="variable"/>
+        <column stringID="value"/>
+        <row stringID="row" value="0">
+          <item stringID="variable" value="Path"/>
+          <item stringID="value" value="E:\ISE\14.7\ISE_DS\ISE\\lib\nt64;E:\ISE\14.7\ISE_DS\ISE\\bin\nt64;E:\ISE\14.7\ISE_DS\ISE\bin\nt64;E:\ISE\14.7\ISE_DS\ISE\lib\nt64;E:\ISE\14.7\ISE_DS\ISE\..\..\..\DocNav;E:\ISE\14.7\ISE_DS\PlanAhead\bin;E:\ISE\14.7\ISE_DS\EDK\bin\nt64;E:\ISE\14.7\ISE_DS\EDK\lib\nt64;E:\ISE\14.7\ISE_DS\EDK\gnu\microblaze\nt\bin;E:\ISE\14.7\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;E:\ISE\14.7\ISE_DS\EDK\gnuwin\bin;E:\ISE\14.7\ISE_DS\EDK\gnu\arm\nt\bin;E:\ISE\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_be\bin;E:\ISE\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_le\bin;E:\ISE\14.7\ISE_DS\common\bin\nt64;E:\ISE\14.7\ISE_DS\common\lib\nt64;C:\Program Files (x86)\VMware\VMware Player\bin\;C:\Windows\system32;C:\Windows;C:\Windows\System32\Wbem;C:\Windows\System32\WindowsPowerShell\v1.0\;C:\Windows\System32\OpenSSH\;C:\Program Files (x86)\Intel\Intel(R) Management Engine Components\DAL;C:\Program Files\Intel\Intel(R) Management Engine Components\DAL;E:\node.js\;E:\matlabr2020b\runtime\win64;E:\matlabr2020b\bin;E:\matlabr2020b\polyspace\bin;E:\minGW\x86_64-8.1.0-release-win32-seh-rt_v6-rev0\mingw64\bin;C:\Users\PC\AppData\Local\Microsoft\WindowsApps;E:\visual studio code\Microsoft VS Code\bin;C:\Users\PC\AppData\Roaming\npm;E:\modelsim\win64"/>
+        </row>
+        <row stringID="row" value="1">
+          <item stringID="variable" value="PATHEXT"/>
+          <item stringID="value" value=".COM;.EXE;.BAT;.CMD;.VBS;.VBE;.JS;.JSE;.WSF;.WSH;.MSC"/>
+        </row>
+        <row stringID="row" value="2">
+          <item stringID="variable" value="XILINX"/>
+          <item stringID="value" value="E:\ISE\14.7\ISE_DS\ISE\"/>
+        </row>
+        <row stringID="row" value="3">
+          <item stringID="variable" value="XILINX_DSP"/>
+          <item stringID="value" value="E:\ISE\14.7\ISE_DS\ISE"/>
+        </row>
+        <row stringID="row" value="4">
+          <item stringID="variable" value="XILINX_EDK"/>
+          <item stringID="value" value="E:\ISE\14.7\ISE_DS\EDK"/>
+        </row>
+        <row stringID="row" value="5">
+          <item stringID="variable" value="XILINX_PLANAHEAD"/>
+          <item stringID="value" value="E:\ISE\14.7\ISE_DS\PlanAhead"/>
+        </row>
+      </table>
+      <item stringID="User_EnvOs" value="OS Information">
+        <item stringID="User_EnvOsname" value="Microsoft , 64-bit"/>
+        <item stringID="User_EnvOsrelease" value="major release  (build 9200)"/>
+      </item>
+      <item stringID="User_EnvHost" value="PC-20210820RYDZ"/>
+      <table stringID="User_EnvCpu">
+        <column stringID="arch"/>
+        <column stringID="speed"/>
+        <row stringID="row" value="0">
+          <item stringID="arch" value="Intel(R) Core(TM) i7-8650U CPU @ 1.90GHz"/>
+          <item stringID="speed" value="2112 MHz"/>
+        </row>
+      </table>
+    </section>
+    <section stringID="XST_OPTION_SUMMARY">
+      <item DEFAULT="" label="-ifn" stringID="XST_IFN" value="CPU.prj"/>
+      <item DEFAULT="MIXED" label="-ifmt" stringID="XST_IFMT" value="mixed"/>
+      <item DEFAULT="" label="-ofn" stringID="XST_OFN" value="CPU"/>
+      <item DEFAULT="NGC" label="-ofmt" stringID="XST_OFMT" value="NGC"/>
+      <item DEFAULT="" label="-p" stringID="XST_P" value="xc3s500e-4-vq100"/>
+      <item DEFAULT="" label="-top" stringID="XST_TOP" value="CPU"/>
+      <item DEFAULT="SPEED" label="-opt_mode" stringID="XST_OPTMODE" value="Speed"/>
+      <item DEFAULT="1" label="-opt_level" stringID="XST_OPTLEVEL" value="1"/>
+      <item DEFAULT="NO" label="-iuc" stringID="XST_IUC" value="NO"/>
+      <item DEFAULT="NO" label="-keep_hierarchy" stringID="XST_KEEPHIERARCHY" value="No"/>
+      <item DEFAULT="as_optimized" label="-netlist_hierarchy" stringID="XST_NETLISTHIERARCHY" value="As_Optimized"/>
+      <item DEFAULT="NO" label="-rtlview" stringID="XST_RTLVIEW" value="Yes"/>
+      <item DEFAULT="ALLCLOCKNETS" label="-glob_opt" stringID="XST_GLOBOPT" value="AllClockNets"/>
+      <item DEFAULT="YES" label="-read_cores" stringID="XST_READCORES" value="YES"/>
+      <item DEFAULT="NO" label="-write_timing_constraints" stringID="XST_WRITETIMINGCONSTRAINTS" value="NO"/>
+      <item DEFAULT="NO" label="-cross_clock_analysis" stringID="XST_CROSSCLOCKANALYSIS" value="NO"/>
+      <item DEFAULT="/" stringID="XST_HIERARCHYSEPARATOR" value="/"/>
+      <item DEFAULT="&lt;>" label="-bus_delimiter" stringID="XST_BUSDELIMITER" value="&lt;>"/>
+      <item DEFAULT="MAINTAIN" stringID="XST_CASE" value="Maintain"/>
+      <item DEFAULT="100%" label="-slice_utilization_ratio" stringID="XST_SLICEUTILIZATIONRATIO" value="100"/>
+      <item DEFAULT="100%" label="-bram_utilization_ratio" stringID="XST_BRAMUTILIZATIONRATIO" value="100"/>
+      <item DEFAULT="YES" label="-verilog2001" stringID="XST_VERILOG2001" value="YES"/>
+      <item DEFAULT="YES" label="-fsm_extract" stringID="XST_FSMEXTRACT" value="YES"/>
+      <item DEFAULT="AUTO" label="-fsm_encoding" stringID="XST_FSMENCODING" value="Auto"/>
+      <item DEFAULT="NO" label="-safe_implementation" stringID="XST_SAFEIMPLEMENTATION" value="No"/>
+      <item DEFAULT="LUT" label="-fsm_style" stringID="XST_FSMSTYLE" value="LUT"/>
+      <item DEFAULT="YES" label="-ram_extract" stringID="XST_RAMEXTRACT" value="Yes"/>
+      <item DEFAULT="AUTO" label="-ram_style" stringID="XST_RAMSTYLE" value="Auto"/>
+      <item DEFAULT="YES" label="-rom_extract" stringID="XST_ROMEXTRACT" value="Yes"/>
+      <item DEFAULT="AUTO" stringID="XST_MUXSTYLE" value="Auto"/>
+      <item DEFAULT="NO" stringID="XST_DECODEREXTRACT" value="YES"/>
+      <item DEFAULT="NO" stringID="XST_PRIORITYEXTRACT" value="Yes"/>
+      <item DEFAULT="YES" label="-shreg_extract" stringID="XST_SHREGEXTRACT" value="YES"/>
+      <item DEFAULT="YES" stringID="XST_SHIFTEXTRACT" value="YES"/>
+      <item DEFAULT="YES" stringID="XST_XORCOLLAPSE" value="YES"/>
+      <item DEFAULT="AUTO" label="-rom_style" stringID="XST_ROMSTYLE" value="Auto"/>
+      <item DEFAULT="NO" label="-auto_bram_packing" stringID="XST_AUTOBRAMPACKING" value="NO"/>
+      <item DEFAULT="YES" stringID="XST_MUXEXTRACT" value="Yes"/>
+      <item DEFAULT="YES" label="-resource_sharing" stringID="XST_RESOURCESHARING" value="YES"/>
+      <item DEFAULT="NO" label="-async_to_sync" stringID="XST_ASYNCTOSYNC" value="NO"/>
+      <item DEFAULT="AUTO" label="-mult_style" stringID="XST_MULTSTYLE" value="Auto"/>
+      <item DEFAULT="YES" label="-iobuf" stringID="XST_IOBUF" value="YES"/>
+      <item DEFAULT="500" label="-max_fanout" stringID="XST_MAXFANOUT" value="100000"/>
+      <item DEFAULT="24" label="-bufg" stringID="XST_BUFG" value="24"/>
+      <item DEFAULT="YES" label="-register_duplication" stringID="XST_REGISTERDUPLICATION" value="YES"/>
+      <item DEFAULT="NO" label="-register_balancing" stringID="XST_REGISTERBALANCING" value="No"/>
+      <item DEFAULT="YES" stringID="XST_SLICEPACKING" value="YES"/>
+      <item DEFAULT="NO" label="-optimize_primitives" stringID="XST_OPTIMIZEPRIMITIVES" value="NO"/>
+      <item DEFAULT="YES" label="-use_clock_enable" stringID="XST_USECLOCKENABLE" value="Yes"/>
+      <item DEFAULT="YES" label="-use_sync_set" stringID="XST_USESYNCSET" value="Yes"/>
+      <item DEFAULT="YES" label="-use_sync_reset" stringID="XST_USESYNCRESET" value="Yes"/>
+      <item DEFAULT="AUTO" label="-iob" stringID="XST_IOB" value="Auto"/>
+      <item DEFAULT="YES" label="-equivalent_register_removal" stringID="XST_EQUIVALENTREGISTERREMOVAL" value="YES"/>
+      <item DEFAULT="0%" label="-slice_utilization_ratio_maxmargin" stringID="XST_SLICEUTILIZATIONRATIOMAXMARGIN" value="5"/>
+    </section>
+    <section stringID="XST_ERRORS_STATISTICS">
+      <item dataType="int" filtered="0" stringID="XST_NUMBER_OF_ERRORS" value="1"/>
+      <item dataType="int" filtered="0" stringID="XST_NUMBER_OF_WARNINGS" value="0"/>
+      <item dataType="int" filtered="0" stringID="XST_NUMBER_OF_INFOS" value="0"/>
+    </section>
+  </application>
+</document>
--- a/NVDLA.v
+++ b/NVDLA.v
--- a/NVDLA_CONTROL.v
+++ b/NVDLA_CONTROL.v
--- a/RAM.v
+++ b/RAM.v
+`timescale 1ns / 1ps
+module RAM #(
+    parameter DATAWIDTH = 32,
+    parameter ADDRWIDTH = 6
+)
+(
+    input clk,
+    input wr_en,
+    input [ADDRWIDTH-1 : 0] addr,
+    input [DATAWIDTH-1 : 0] wr_data,
+    input rd_en,
+    input [(DATAWIDTH/8)-1 : 0] wstrb,
+    output reg [DATAWIDTH-1 :0] rd_data
+);
+	initial begin
+		mem[0]=0;
+		mem[1]=1;
+		mem[2]=2;
+		mem[3]=3;
+		mem[4]=4;
+		mem[5]=5;
+		mem[6]=6;
+		mem[7]=7;
+		mem[8]=8;
+		mem[9]=9;
+		mem[10]=10;
+		mem[11]=11;
+		mem[12]=12;
+		mem[13]=13;
+		mem[14]=14;
+		mem[15]=15;
+		mem[16]=16;
+		mem[17]=17;
+		mem[18]=18;
+		mem[19]=19;
+		mem[20]=20;
+		mem[21]=21;
+		mem[22]=22;
+		mem[23]=23;
+		mem[24]=24;
+		mem[25]=25;
+		mem[26]=26;
+		mem[27]=27;
+		mem[28]=28;
+		mem[29]=29;
+	end
+    reg [DATAWIDTH-1 : 0] mem [0 : (1<<ADDRWIDTH)-1];
+    // write data to memory
+    wire [DATAWIDTH-1 : 0] strb_data;
+    genvar i; 
+    generate for(i = 0; i < (DATAWIDTH/8); i = i + 1) begin :RAM_GEN
+        assign strb_data[8*i+:8] = (wstrb[i]) ? wr_data[8*i+:8] : mem[addr][8*i+:8];
+    end
+    endgenerate
+    always@(posedge clk)begin
+        if(wr_en)
+            mem[addr] <= strb_data;
+    end
+    // read data from memory
+    always @(rd_en , addr) begin
+        if(rd_en) rd_data = mem[addr];
+        else rd_data = 0;
+    end
+endmodule 
\ No newline at end of file
--- a/RAM_CONTROL.v
+++ b/RAM_CONTROL.v
--- a/RISCV_CPU.gise
+++ b/RISCV_CPU.gise
--- a/RISCV_CPU.xise
+++ b/RISCV_CPU.xise
--- a/RISCV_CPU/RISCV_CPU.cache/wt/gui_handlers.wdf
+++ b/RISCV_CPU/RISCV_CPU.cache/wt/gui_handlers.wdf
+version:1
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+eof:143356215
--- a/RISCV_CPU/RISCV_CPU.cache/wt/java_command_handlers.wdf
+++ b/RISCV_CPU/RISCV_CPU.cache/wt/java_command_handlers.wdf
+version:1
+70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6f70656e70726f6a656374:31:00:00
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+eof:3843515271
--- a/RISCV_CPU/RISCV_CPU.cache/wt/project.wpc
+++ b/RISCV_CPU/RISCV_CPU.cache/wt/project.wpc
+version:1
+6d6f64655f636f756e7465727c4755494d6f6465:1
+eof:
--- a/RISCV_CPU/RISCV_CPU.cache/wt/synthesis.wdf
+++ b/RISCV_CPU/RISCV_CPU.cache/wt/synthesis.wdf
+version:1
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+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d617373657274:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e6f5f74696d696e675f64726976656e:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73666375:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
+eof:177282686
--- a/RISCV_CPU/RISCV_CPU.cache/wt/webtalk_pa.xml
+++ b/RISCV_CPU/RISCV_CPU.cache/wt/webtalk_pa.xml
+<?xml version="1.0" encoding="UTF-8" ?>
+<document>
+<!--The data in this file is primarily intended for consumption by Xilinx tools.
+The structure and the elements are likely to change over the next few releases.
+This means code written to parse this file will need to be revisited each subsequent release.-->
+<application name="pa" timeStamp="Wed Dec 22 22:46:59 2021">
+<section name="Project Information" visible="false">
+<property name="ProjectID" value="d604f8545ebb415cbef8761c84005371" type="ProjectID"/>
+<property name="ProjectIteration" value="1" type="ProjectIteration"/>
+</section>
+<section name="PlanAhead Usage" visible="true">
+<item name="Project Data">
+<property name="SrcSetCount" value="1" type="SrcSetCount"/>
+<property name="ConstraintSetCount" value="1" type="ConstraintSetCount"/>
+<property name="DesignMode" value="RTL" type="DesignMode"/>
+<property name="SynthesisStrategy" value="Vivado Synthesis Defaults" type="SynthesisStrategy"/>
+<property name="ImplStrategy" value="Vivado Implementation Defaults" type="ImplStrategy"/>
+</item>
+<item name="Java Command Handlers">
+<property name="OpenProject" value="1" type="JavaHandler"/>
+<property name="RunSynthesis" value="1" type="JavaHandler"/>
+<property name="ShowView" value="1" type="JavaHandler"/>
+</item>
+<item name="Gui Handlers">
+<property name="BaseDialog_OK" value="4" type="GuiHandlerData"/>
+<property name="FileSetPanel_FILE_SET_PANEL_TREE" value="2" type="GuiHandlerData"/>
+<property name="GettingStartedView_OPEN_PROJECT" value="1" type="GuiHandlerData"/>
+<property name="HJFileChooserRecentListPreview_RECENT_DIRECTORIES" value="1" type="GuiHandlerData"/>
+<property name="MainMenuMgr_EDIT" value="2" type="GuiHandlerData"/>
+<property name="MainMenuMgr_FILE" value="4" type="GuiHandlerData"/>
+<property name="MainMenuMgr_FLOW" value="14" type="GuiHandlerData"/>
+<property name="MainMenuMgr_REPORTS" value="2" type="GuiHandlerData"/>
+<property name="MainMenuMgr_SETTINGS" value="1" type="GuiHandlerData"/>
+<property name="MainMenuMgr_TOOLS" value="8" type="GuiHandlerData"/>
+<property name="MainMenuMgr_VIEW" value="2" type="GuiHandlerData"/>
+<property name="MainMenuMgr_WINDOW" value="6" type="GuiHandlerData"/>
+<property name="MainWinMenuMgr_LAYOUT" value="4" type="GuiHandlerData"/>
+<property name="MsgTreePanel_MESSAGE_VIEW_TREE" value="7" type="GuiHandlerData"/>
+<property name="PACommandNames_RUN_SYNTHESIS" value="1" type="GuiHandlerData"/>
+<property name="PACommandNames_SIMULATION_RUN" value="1" type="GuiHandlerData"/>
+<property name="ProjectNameChooser_PROJECT_NAME" value="1" type="GuiHandlerData"/>
+</item>
+<item name="Other">
+<property name="GuiMode" value="4" type="GuiMode"/>
+<property name="BatchMode" value="0" type="BatchMode"/>
+<property name="TclMode" value="3" type="TclMode"/>
+</item>
+</section>
+</application>
+</document>
--- a/RISCV_CPU/RISCV_CPU.hw/RISCV_CPU.lpr
+++ b/RISCV_CPU/RISCV_CPU.hw/RISCV_CPU.lpr
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- Product Version: Vivado v2018.1 (64-bit)                     -->
+<!--                                                              -->
+<!-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.        -->
+<labtools version="1" minor="0"/>
--- a/RISCV_CPU/RISCV_CPU.runs/.jobs/vrs_config_1.xml
+++ b/RISCV_CPU/RISCV_CPU.runs/.jobs/vrs_config_1.xml
+<?xml version="1.0"?>
+<Runs Version="1" Minor="0">
+	<Run Id="synth_1" LaunchDir="E:/verilogtest/RISCV_CPU/RISCV_CPU/RISCV_CPU.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
+</Runs>
--- a/RISCV_CPU/RISCV_CPU.runs/synth_1/.Vivado_Synthesis.queue.rst
+++ b/RISCV_CPU/RISCV_CPU.runs/synth_1/.Vivado_Synthesis.queue.rst
--- a/RISCV_CPU/RISCV_CPU.runs/synth_1/.vivado.begin.rst
+++ b/RISCV_CPU/RISCV_CPU.runs/synth_1/.vivado.begin.rst
+<?xml version="1.0"?>
+<ProcessHandle Version="1" Minor="0">
+    <Process Command="vivado.bat" Owner="PC" Host="PC-20210820RYDZ" Pid="8680">
+    </Process>
+</ProcessHandle>
--- a/RISCV_CPU/RISCV_CPU.runs/synth_1/.vivado.error.rst
+++ b/RISCV_CPU/RISCV_CPU.runs/synth_1/.vivado.error.rst
--- a/RISCV_CPU/RISCV_CPU.runs/synth_1/CPU.tcl
+++ b/RISCV_CPU/RISCV_CPU.runs/synth_1/CPU.tcl
+# 
+# Synthesis run script generated by Vivado
+# 
+proc create_report { reportName command } {
+  set status "."
+  append status $reportName ".fail"
+  if { [file exists $status] } {
+    eval file delete [glob $status]
+  }
+  send_msg_id runtcl-4 info "Executing : $command"
+  set retval [eval catch { $command } msg]
+  if { $retval != 0 } {
+    set fp [open $status w]
+    close $fp
+    send_msg_id runtcl-5 warning "$msg"
+  }
+}
+create_project -in_memory -part xc7vx485tffg1157-1
+set_param project.singleFileAddWarning.threshold 0
+set_param project.compositeFile.enableAutoGeneration 0
+set_param synth.vivado.isSynthRun true
+set_property webtalk.parent_dir E:/verilogtest/RISCV_CPU/RISCV_CPU/RISCV_CPU.cache/wt [current_project]
+set_property parent.project_path E:/verilogtest/RISCV_CPU/RISCV_CPU/RISCV_CPU.xpr [current_project]
+set_property default_lib xil_defaultlib [current_project]
+set_property target_language Verilog [current_project]
+set_property ip_output_repo e:/verilogtest/RISCV_CPU/RISCV_CPU/RISCV_CPU.cache/ip [current_project]
+set_property ip_cache_permissions {read write} [current_project]
+read_verilog -library xil_defaultlib {
+  E:/verilogtest/RISCV_CPU/ROM.v
+  E:/verilogtest/RISCV_CPU/Registers.v
+  E:/verilogtest/RISCV_CPU/RAM.v
+  E:/verilogtest/RISCV_CPU/myreg.v
+  E:/verilogtest/RISCV_CPU/mux4.v
+  E:/verilogtest/RISCV_CPU/forward.v
+  E:/verilogtest/RISCV_CPU/dependence_detect.v
+  E:/verilogtest/RISCV_CPU/decoder.v
+  E:/verilogtest/RISCV_CPU/ALU.v
+  E:/verilogtest/RISCV_CPU/CPU.v
+}
+# Mark all dcp files as not used in implementation to prevent them from being
+# stitched into the results of this synthesis run. Any black boxes in the
+# design are intentionally left as such for best results. Dcp files will be
+# stitched into the design at a later time, either when this synthesis run is
+# opened, or when it is stitched into a dependent implementation run.
+foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] {
+  set_property used_in_implementation false $dcp
+}
+set_param ips.enableIPCacheLiteLoad 0
+close [open __synthesis_is_running__ w]
+synth_design -top CPU -part xc7vx485tffg1157-1
+# disable binary constraint mode for synth run checkpoints
+set_param constraints.enableBinaryConstraints false
+write_checkpoint -force -noxdef CPU.dcp
+create_report "synth_1_synth_report_utilization_0" "report_utilization -file CPU_utilization_synth.rpt -pb CPU_utilization_synth.pb"
+file delete __synthesis_is_running__
+close [open __synthesis_is_complete__ w]
--- a/RISCV_CPU/RISCV_CPU.runs/synth_1/CPU.vds
+++ b/RISCV_CPU/RISCV_CPU.runs/synth_1/CPU.vds
+#-----------------------------------------------------------
+# Vivado v2018.1 (64-bit)
+# SW Build 2188600 on Wed Apr  4 18:40:38 MDT 2018
+# IP Build 2185939 on Wed Apr  4 20:55:05 MDT 2018
+# Start of session at: Wed Dec 22 22:45:27 2021
+# Process ID: 11108
+# Current directory: E:/verilogtest/RISCV_CPU/RISCV_CPU/RISCV_CPU.runs/synth_1
+# Command line: vivado.exe -log CPU.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source CPU.tcl
+# Log file: E:/verilogtest/RISCV_CPU/RISCV_CPU/RISCV_CPU.runs/synth_1/CPU.vds
+# Journal file: E:/verilogtest/RISCV_CPU/RISCV_CPU/RISCV_CPU.runs/synth_1\vivado.jou
+#-----------------------------------------------------------
+source CPU.tcl -notrace
+Command: synth_design -top CPU -part xc7vx485tffg1157-1
+Starting synth_design
+Attempting to get a license for feature 'Synthesis' and/or device 'xc7vx485t'
+INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7vx485t'
+INFO: Launching helper process for spawning children vivado processes
+INFO: Helper process launched with PID 3976 
+ERROR: [Synth 8-2515] part-select of memory ram_buffer is not allowed [E:/verilogtest/RISCV_CPU/RAM.v:25]
+ERROR: [Synth 8-2114] illegal concatenation of unpacked value [E:/verilogtest/RISCV_CPU/RAM.v:25]
+ERROR: [Synth 8-2515] part-select of memory ram_buffer is not allowed [E:/verilogtest/RISCV_CPU/RAM.v:26]
+ERROR: [Synth 8-2114] illegal concatenation of unpacked value [E:/verilogtest/RISCV_CPU/RAM.v:26]
+INFO: [Synth 8-2350] module RAM ignored due to previous errors [E:/verilogtest/RISCV_CPU/RAM.v:3]
+Failed to read verilog 'E:/verilogtest/RISCV_CPU/RAM.v'
+INFO: [Common 17-83] Releasing license: Synthesis
+3 Infos, 0 Warnings, 0 Critical Warnings and 5 Errors encountered.
+synth_design failed
+ERROR: [Common 17-69] Command failed: Vivado Synthesis failed
+INFO: [Common 17-206] Exiting Vivado at Wed Dec 22 22:45:42 2021...
--- a/RISCV_CPU/RISCV_CPU.runs/synth_1/ISEWrap.js
+++ b/RISCV_CPU/RISCV_CPU.runs/synth_1/ISEWrap.js
+//
+//  Vivado(TM)
+//  ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6
+//  Copyright 1986-1999, 2001-2013,2015 Xilinx, Inc. All Rights Reserved. 
+//
+// GLOBAL VARIABLES
+var ISEShell = new ActiveXObject( "WScript.Shell" );
+var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" );
+var ISERunDir = "";
+var ISELogFile = "runme.log";
+var ISELogFileStr = null;
+var ISELogEcho = true;
+var ISEOldVersionWSH = false;
+// BOOTSTRAP
+ISEInit();
+//
+// ISE FUNCTIONS
+//
+function ISEInit() {
+  // 1. RUN DIR setup
+  var ISEScrFP = WScript.ScriptFullName;
+  var ISEScrN = WScript.ScriptName;
+  ISERunDir = 
+    ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 );
+  // 2. LOG file setup
+  ISELogFileStr = ISEOpenFile( ISELogFile );
+  // 3. LOG echo?
+  var ISEScriptArgs = WScript.Arguments;
+  for ( var loopi=0; loopi<ISEScriptArgs.length; loopi++ ) {
+    if ( ISEScriptArgs(loopi) == "-quiet" ) {
+      ISELogEcho = false;
+      break;
+    }
+  }
+  // 4. WSH version check
+  var ISEOptimalVersionWSH = 5.6;
+  var ISECurrentVersionWSH = WScript.Version;
+  if ( ISECurrentVersionWSH < ISEOptimalVersionWSH ) {
+    ISEStdErr( "" );
+    ISEStdErr( "Warning: ExploreAhead works best with Microsoft WSH " +
+	       ISEOptimalVersionWSH + " or higher. Downloads" );
+    ISEStdErr( "         for upgrading your Windows Scripting Host can be found here: " );
+    ISEStdErr( "             http://msdn.microsoft.com/downloads/list/webdev.asp" );
+    ISEStdErr( "" );
+    ISEOldVersionWSH = true;
+  }
+}
+function ISEStep( ISEProg, ISEArgs ) {
+  // CHECK for a STOP FILE
+  if ( ISEFileSys.FileExists(ISERunDir + "/.stop.rst") ) {
+    ISEStdErr( "" );
+    ISEStdErr( "*** Halting run - EA reset detected ***" );
+    ISEStdErr( "" );
+    WScript.Quit( 1 );
+  }
+  // WRITE STEP HEADER to LOG
+  ISEStdOut( "" );
+  ISEStdOut( "*** Running " + ISEProg );
+  ISEStdOut( "    with args " + ISEArgs );
+  ISEStdOut( "" );
+  // LAUNCH!
+  var ISEExitCode = ISEExec( ISEProg, ISEArgs );  
+  if ( ISEExitCode != 0 ) {
+    WScript.Quit( ISEExitCode );
+  }
+}
+function ISEExec( ISEProg, ISEArgs ) {
+  var ISEStep = ISEProg;
+  if (ISEProg == "realTimeFpga" || ISEProg == "planAhead" || ISEProg == "vivado") {
+    ISEProg += ".bat";
+  }
+  var ISECmdLine = ISEProg + " " + ISEArgs;
+  var ISEExitCode = 1;
+  if ( ISEOldVersionWSH ) { // WSH 5.1
+    // BEGIN file creation
+    ISETouchFile( ISEStep, "begin" );
+    // LAUNCH!
+    ISELogFileStr.Close();
+    ISECmdLine = 
+      "%comspec% /c " + ISECmdLine + " >> " + ISELogFile + " 2>&1";
+    ISEExitCode = ISEShell.Run( ISECmdLine, 0, true );
+    ISELogFileStr = ISEOpenFile( ISELogFile );
+  } else {  // WSH 5.6
+    // LAUNCH!
+    ISEShell.CurrentDirectory = ISERunDir;
+    // Redirect STDERR to STDOUT
+    ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1";
+    var ISEProcess = ISEShell.Exec( ISECmdLine );
+    // BEGIN file creation
+    var ISENetwork = WScript.CreateObject( "WScript.Network" );
+    var ISEHost = ISENetwork.ComputerName;
+    var ISEUser = ISENetwork.UserName;
+    var ISEPid = ISEProcess.ProcessID;
+    var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" );
+    ISEBeginFile.WriteLine( "<?xml version=\"1.0\"?>" );
+    ISEBeginFile.WriteLine( "<ProcessHandle Version=\"1\" Minor=\"0\">" );
+    ISEBeginFile.WriteLine( "    <Process Command=\"" + ISEProg + 
+			    "\" Owner=\"" + ISEUser + 
+			    "\" Host=\"" + ISEHost + 
+			    "\" Pid=\"" + ISEPid +
+			    "\">" );
+    ISEBeginFile.WriteLine( "    </Process>" );
+    ISEBeginFile.WriteLine( "</ProcessHandle>" );
+    ISEBeginFile.Close();
+    var ISEOutStr = ISEProcess.StdOut;
+    var ISEErrStr = ISEProcess.StdErr;
+    // WAIT for ISEStep to finish
+    while ( ISEProcess.Status == 0 ) {
+      // dump stdout then stderr - feels a little arbitrary
+      while ( !ISEOutStr.AtEndOfStream ) {
+        ISEStdOut( ISEOutStr.ReadLine() );
+      }  
+      WScript.Sleep( 100 );
+    }
+    ISEExitCode = ISEProcess.ExitCode;
+  }
+  ISELogFileStr.Close();
+  // END/ERROR file creation
+  if ( ISEExitCode != 0 ) {    
+    ISETouchFile( ISEStep, "error" );
+  } else {
+    ISETouchFile( ISEStep, "end" );
+  }
+  return ISEExitCode;
+}
+//
+// UTILITIES
+//
+function ISEStdOut( ISELine ) {
+  ISELogFileStr.WriteLine( ISELine );
+  if ( ISELogEcho ) {
+    WScript.StdOut.WriteLine( ISELine );
+  }
+}
+function ISEStdErr( ISELine ) {
+  ISELogFileStr.WriteLine( ISELine );
+  if ( ISELogEcho ) {
+    WScript.StdErr.WriteLine( ISELine );
+  }
+}
+function ISETouchFile( ISERoot, ISEStatus ) {
+  var ISETFile = 
+    ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" );
+  ISETFile.Close();
+}
+function ISEOpenFile( ISEFilename ) {
+  // This function has been updated to deal with a problem seen in CR #870871.
+  // In that case the user runs a script that runs impl_1, and then turns around
+  // and runs impl_1 -to_step write_bitstream. That second run takes place in
+  // the same directory, which means we may hit some of the same files, and in
+  // particular, we will open the runme.log file. Even though this script closes
+  // the file (now), we see cases where a subsequent attempt to open the file
+  // fails. Perhaps the OS is slow to release the lock, or the disk comes into
+  // play? In any case, we try to work around this by first waiting if the file
+  // is already there for an arbitrary 5 seconds. Then we use a try-catch block
+  // and try to open the file 10 times with a one second delay after each attempt.
+  // Again, 10 is arbitrary. But these seem to stop the hang in CR #870871.
+  // If there is an unrecognized exception when trying to open the file, we output
+  // an error message and write details to an exception.log file.
+  var ISEFullPath = ISERunDir + "/" + ISEFilename;
+  if (ISEFileSys.FileExists(ISEFullPath)) {
+    // File is already there. This could be a problem. Wait in case it is still in use.
+    WScript.Sleep(5000);
+  }
+  var i;
+  for (i = 0; i < 10; ++i) {
+    try {
+      return ISEFileSys.OpenTextFile(ISEFullPath, 8, true);
+    } catch (exception) {
+      var error_code = exception.number & 0xFFFF; // The other bits are a facility code.
+      if (error_code == 52) { // 52 is bad file name or number.
+        // Wait a second and try again.
+        WScript.Sleep(1000);
+        continue;
+      } else {
+        WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath);
+        var exceptionFilePath = ISERunDir + "/exception.log";
+        if (!ISEFileSys.FileExists(exceptionFilePath)) {
+          WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details.");
+          var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true);
+          exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath);
+          exceptionFile.WriteLine("\tException name: " + exception.name);
+          exceptionFile.WriteLine("\tException error code: " + error_code);
+          exceptionFile.WriteLine("\tException message: " + exception.message);
+          exceptionFile.Close();
+        }
+        throw exception;
+      }
+    }
+  }
+  // If we reached this point, we failed to open the file after 10 attempts.
+  // We need to error out.
+  WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath);
+  WScript.Quit(1);
+}
--- a/RISCV_CPU/RISCV_CPU.runs/synth_1/ISEWrap.sh
+++ b/RISCV_CPU/RISCV_CPU.runs/synth_1/ISEWrap.sh
+#!/bin/sh
+#
+#  Vivado(TM)
+#  ISEWrap.sh: Vivado Runs Script for UNIX
+#  Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved. 
+#
+HD_LOG=$1
+shift
+# CHECK for a STOP FILE
+if [ -f .stop.rst ]
+then
+echo ""                                        >> $HD_LOG
+echo "*** Halting run - EA reset detected ***" >> $HD_LOG
+echo ""                                        >> $HD_LOG
+exit 1
+fi
+ISE_STEP=$1
+shift
+# WRITE STEP HEADER to LOG
+echo ""                      >> $HD_LOG
+echo "*** Running $ISE_STEP" >> $HD_LOG
+echo "    with args $@"      >> $HD_LOG
+echo ""                      >> $HD_LOG
+# LAUNCH!
+$ISE_STEP "$@" >> $HD_LOG 2>&1 &
+# BEGIN file creation
+ISE_PID=$!
+if [ X != X$HOSTNAME ]
+then
+ISE_HOST=$HOSTNAME #bash
+else
+ISE_HOST=$HOST     #csh
+fi
+ISE_USER=$USER
+ISE_BEGINFILE=.$ISE_STEP.begin.rst
+/bin/touch $ISE_BEGINFILE
+echo "<?xml version=\"1.0\"?>"                                                                     >> $ISE_BEGINFILE
+echo "<ProcessHandle Version=\"1\" Minor=\"0\">"                                                   >> $ISE_BEGINFILE
+echo "    <Process Command=\"$ISE_STEP\" Owner=\"$ISE_USER\" Host=\"$ISE_HOST\" Pid=\"$ISE_PID\">" >> $ISE_BEGINFILE
+echo "    </Process>"                                                                              >> $ISE_BEGINFILE
+echo "</ProcessHandle>"                                                                            >> $ISE_BEGINFILE
+# WAIT for ISEStep to finish
+wait $ISE_PID
+# END/ERROR file creation
+RETVAL=$?
+if [ $RETVAL -eq 0 ]
+then
+    /bin/touch .$ISE_STEP.end.rst
+else
+    /bin/touch .$ISE_STEP.error.rst
+fi
+exit $RETVAL
--- a/RISCV_CPU/RISCV_CPU.runs/synth_1/__synthesis_is_running__
+++ b/RISCV_CPU/RISCV_CPU.runs/synth_1/__synthesis_is_running__
--- a/RISCV_CPU/RISCV_CPU.runs/synth_1/gen_run.xml
+++ b/RISCV_CPU/RISCV_CPU.runs/synth_1/gen_run.xml
+<?xml version="1.0" encoding="UTF-8"?>
+<GenRun Id="synth_1" LaunchPart="xc7vx485tffg1157-1" LaunchTime="1640184325">
+  <File Type="PA-TCL" Name="CPU.tcl"/>
+  <File Type="RDS-PROPCONSTRS" Name="CPU_drc_synth.rpt"/>
+  <File Type="REPORTS-TCL" Name="CPU_reports.tcl"/>
+  <File Type="RDS-RDS" Name="CPU.vds"/>
+  <File Type="RDS-UTIL" Name="CPU_utilization_synth.rpt"/>
+  <File Type="RDS-UTIL-PB" Name="CPU_utilization_synth.pb"/>
+  <File Type="RDS-DCP" Name="CPU.dcp"/>
+  <File Type="VDS-TIMINGSUMMARY" Name="CPU_timing_summary_synth.rpt"/>
+  <File Type="VDS-TIMING-PB" Name="CPU_timing_summary_synth.pb"/>
+  <FileSet Name="sources" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
+    <Filter Type="Srcs"/>
+    <File Path="$PPRDIR/../ROM.v">
+      <FileInfo>
+        <Attr Name="Library" Val="xil_defaultlib"/>
+        <Attr Name="UsedIn" Val="synthesis"/>
+        <Attr Name="UsedIn" Val="implementation"/>
+        <Attr Name="UsedIn" Val="simulation"/>
+      </FileInfo>
+    </File>
+    <File Path="$PPRDIR/../Registers.v">
+      <FileInfo>
+        <Attr Name="Library" Val="xil_defaultlib"/>
+        <Attr Name="UsedIn" Val="synthesis"/>
+        <Attr Name="UsedIn" Val="implementation"/>
+        <Attr Name="UsedIn" Val="simulation"/>
+      </FileInfo>
+    </File>
+    <File Path="$PPRDIR/../RAM.v">
+      <FileInfo>
+        <Attr Name="Library" Val="xil_defaultlib"/>
+        <Attr Name="UsedIn" Val="synthesis"/>
+        <Attr Name="UsedIn" Val="implementation"/>
+        <Attr Name="UsedIn" Val="simulation"/>
+      </FileInfo>
+    </File>
+    <File Path="$PPRDIR/../myreg.v">
+      <FileInfo>
+        <Attr Name="Library" Val="xil_defaultlib"/>
+        <Attr Name="UsedIn" Val="synthesis"/>
+        <Attr Name="UsedIn" Val="implementation"/>
+        <Attr Name="UsedIn" Val="simulation"/>
+      </FileInfo>
+    </File>
+    <File Path="$PPRDIR/../mux4.v">
+      <FileInfo>
+        <Attr Name="Library" Val="xil_defaultlib"/>
+        <Attr Name="UsedIn" Val="synthesis"/>
+        <Attr Name="UsedIn" Val="implementation"/>
+        <Attr Name="UsedIn" Val="simulation"/>
+      </FileInfo>
+    </File>
+    <File Path="$PPRDIR/../forward.v">
+      <FileInfo>
+        <Attr Name="Library" Val="xil_defaultlib"/>
+        <Attr Name="UsedIn" Val="synthesis"/>
+        <Attr Name="UsedIn" Val="implementation"/>
+        <Attr Name="UsedIn" Val="simulation"/>
+      </FileInfo>
+    </File>
+    <File Path="$PPRDIR/../dependence_detect.v">
+      <FileInfo>
+        <Attr Name="Library" Val="xil_defaultlib"/>
+        <Attr Name="UsedIn" Val="synthesis"/>
+        <Attr Name="UsedIn" Val="implementation"/>
+        <Attr Name="UsedIn" Val="simulation"/>
+      </FileInfo>
+    </File>
+    <File Path="$PPRDIR/../decoder.v">
+      <FileInfo>
+        <Attr Name="Library" Val="xil_defaultlib"/>
+        <Attr Name="UsedIn" Val="synthesis"/>
+        <Attr Name="UsedIn" Val="implementation"/>
+        <Attr Name="UsedIn" Val="simulation"/>
+      </FileInfo>
+    </File>
+    <File Path="$PPRDIR/../ALU.v">
+      <FileInfo>
+        <Attr Name="Library" Val="xil_defaultlib"/>
+        <Attr Name="UsedIn" Val="synthesis"/>
+        <Attr Name="UsedIn" Val="implementation"/>
+        <Attr Name="UsedIn" Val="simulation"/>
+      </FileInfo>
+    </File>
+    <File Path="$PPRDIR/../CPU.v">
+      <FileInfo>
+        <Attr Name="Library" Val="xil_defaultlib"/>
+        <Attr Name="UsedIn" Val="synthesis"/>
+        <Attr Name="UsedIn" Val="implementation"/>
+        <Attr Name="UsedIn" Val="simulation"/>
+      </FileInfo>
+    </File>
+    <File Path="$PPRDIR/import_ise_summary.txt"/>
+    <Config>
+      <Option Name="DesignMode" Val="RTL"/>
+      <Option Name="TopModule" Val="CPU"/>
+    </Config>
+  </FileSet>
+  <FileSet Name="constrs_in" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
+    <Filter Type="Constrs"/>
+    <Config>
+      <Option Name="ConstrsType" Val="XDC"/>
+    </Config>
+  </FileSet>
+  <Strategy Version="1" Minor="2">
+    <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2018">
+      <Desc>Vivado Synthesis Defaults</Desc>
+    </StratHandle>
+    <Step Id="synth_design"/>
+  </Strategy>
+</GenRun>
--- a/RISCV_CPU/RISCV_CPU.runs/synth_1/htr.txt
+++ b/RISCV_CPU/RISCV_CPU.runs/synth_1/htr.txt
+REM
+REM Vivado(TM)
+REM htr.txt: a Vivado-generated description of how-to-repeat the
+REM          the basic steps of a run.  Note that runme.bat/sh needs
+REM          to be invoked for Vivado to track run status.
+REM Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
+REM
+vivado -log CPU.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source CPU.tcl
--- a/RISCV_CPU/RISCV_CPU.runs/synth_1/project.wdf
+++ b/RISCV_CPU/RISCV_CPU.runs/synth_1/project.wdf
+version:1
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:3131:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:30:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73796e7468657369737374726174656779:56697661646f2053796e7468657369732044656661756c7473:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:696d706c7374726174656779:56697661646f20496d706c656d656e746174696f6e2044656661756c7473:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e7473796e74686573697372756e:73796e74685f31:00:00
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+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c73796e74686573697372756e73:31:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c696d706c72756e73:31:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f72655f636f6e7461696e6572:66616c7365:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73696d756c61746f725f6c616e6775616765:4d69786564:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f6c616e6775616765:566572696c6f67:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64656661756c745f6c696272617279:78696c5f64656661756c746c6962:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f73696d756c61746f72:5853696d:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f7873696d:30:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f6d6f64656c73696d:30:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f717565737461:30:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f696573:30:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f766373:30:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f72697669657261:30:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f61637469766568646c:30:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f7873696d:30:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f6d6f64656c73696d:30:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f717565737461:30:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f696573:30:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f766373:30:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:30:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:30:00:00
+5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:3834363361356639626362333466386138333834666430393435636231653936:506172656e742050412070726f6a656374204944:00
+eof:3616605200
--- a/RISCV_CPU/RISCV_CPU.runs/synth_1/rundef.js
+++ b/RISCV_CPU/RISCV_CPU.runs/synth_1/rundef.js
+//
+// Vivado(TM)
+// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6
+// Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
+//
+var WshShell = new ActiveXObject( "WScript.Shell" );
+var ProcEnv = WshShell.Environment( "Process" );
+var PathVal = ProcEnv("PATH");
+if ( PathVal.length == 0 ) {
+  PathVal = "E:/xilinx/SDK/2018.1/bin;E:/xilinx/Vivado/2018.1/ids_lite/ISE/bin/nt64;E:/xilinx/Vivado/2018.1/ids_lite/ISE/lib/nt64;E:/xilinx/Vivado/2018.1/bin;";
+} else {
+  PathVal = "E:/xilinx/SDK/2018.1/bin;E:/xilinx/Vivado/2018.1/ids_lite/ISE/bin/nt64;E:/xilinx/Vivado/2018.1/ids_lite/ISE/lib/nt64;E:/xilinx/Vivado/2018.1/bin;" + PathVal;
+}
+ProcEnv("PATH") = PathVal;
+var RDScrFP = WScript.ScriptFullName;
+var RDScrN = WScript.ScriptName;
+var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 );
+var ISEJScriptLib = RDScrDir + "/ISEWrap.js";
+eval( EAInclude(ISEJScriptLib) );
+ISEStep( "vivado",
+         "-log CPU.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source CPU.tcl" );
+function EAInclude( EAInclFilename ) {
+  var EAFso = new ActiveXObject( "Scripting.FileSystemObject" );
+  var EAInclFile = EAFso.OpenTextFile( EAInclFilename );
+  var EAIFContents = EAInclFile.ReadAll();
+  EAInclFile.Close();
+  return EAIFContents;
+}
--- a/RISCV_CPU/RISCV_CPU.runs/synth_1/runme.bat
+++ b/RISCV_CPU/RISCV_CPU.runs/synth_1/runme.bat
+@echo off
+rem  Vivado (TM)
+rem  runme.bat: a Vivado-generated Script
+rem  Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
+set HD_SDIR=%~dp0
+cd /d "%HD_SDIR%"
+cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %*
--- a/RISCV_CPU/RISCV_CPU.runs/synth_1/runme.log
+++ b/RISCV_CPU/RISCV_CPU.runs/synth_1/runme.log
+*** Running vivado
+    with args -log CPU.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source CPU.tcl
+****** Vivado v2018.1 (64-bit)
+  **** SW Build 2188600 on Wed Apr  4 18:40:38 MDT 2018
+  **** IP Build 2185939 on Wed Apr  4 20:55:05 MDT 2018
+    ** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
+source CPU.tcl -notrace
+Command: synth_design -top CPU -part xc7vx485tffg1157-1
+Starting synth_design
+Attempting to get a license for feature 'Synthesis' and/or device 'xc7vx485t'
+INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7vx485t'
+INFO: Launching helper process for spawning children vivado processes
+INFO: Helper process launched with PID 3976 
+ERROR: [Synth 8-2515] part-select of memory ram_buffer is not allowed [E:/verilogtest/RISCV_CPU/RAM.v:25]
+ERROR: [Synth 8-2114] illegal concatenation of unpacked value [E:/verilogtest/RISCV_CPU/RAM.v:25]
+ERROR: [Synth 8-2515] part-select of memory ram_buffer is not allowed [E:/verilogtest/RISCV_CPU/RAM.v:26]
+ERROR: [Synth 8-2114] illegal concatenation of unpacked value [E:/verilogtest/RISCV_CPU/RAM.v:26]
+INFO: [Synth 8-2350] module RAM ignored due to previous errors [E:/verilogtest/RISCV_CPU/RAM.v:3]
+Failed to read verilog 'E:/verilogtest/RISCV_CPU/RAM.v'
+INFO: [Common 17-83] Releasing license: Synthesis
+3 Infos, 0 Warnings, 0 Critical Warnings and 5 Errors encountered.
+synth_design failed
+ERROR: [Common 17-69] Command failed: Vivado Synthesis failed
+INFO: [Common 17-206] Exiting Vivado at Wed Dec 22 22:45:42 2021...
--- a/RISCV_CPU/RISCV_CPU.runs/synth_1/runme.sh
+++ b/RISCV_CPU/RISCV_CPU.runs/synth_1/runme.sh
+#!/bin/sh
+# 
+# Vivado(TM)
+# runme.sh: a Vivado-generated Runs Script for UNIX
+# Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
+# 
+echo "This script was generated under a different operating system."
+echo "Please update the PATH and LD_LIBRARY_PATH variables below, before executing this script"
+exit
+if [ -z "$PATH" ]; then
+  PATH=E:/xilinx/SDK/2018.1/bin;E:/xilinx/Vivado/2018.1/ids_lite/ISE/bin/nt64;E:/xilinx/Vivado/2018.1/ids_lite/ISE/lib/nt64:E:/xilinx/Vivado/2018.1/bin
+else
+  PATH=E:/xilinx/SDK/2018.1/bin;E:/xilinx/Vivado/2018.1/ids_lite/ISE/bin/nt64;E:/xilinx/Vivado/2018.1/ids_lite/ISE/lib/nt64:E:/xilinx/Vivado/2018.1/bin:$PATH
+fi
+export PATH
+if [ -z "$LD_LIBRARY_PATH" ]; then
+  LD_LIBRARY_PATH=
+else
+  LD_LIBRARY_PATH=:$LD_LIBRARY_PATH
+fi
+export LD_LIBRARY_PATH
+HD_PWD='E:/verilogtest/RISCV_CPU/RISCV_CPU/RISCV_CPU.runs/synth_1'
+cd "$HD_PWD"
+HD_LOG=runme.log
+/bin/touch $HD_LOG
+ISEStep="./ISEWrap.sh"
+EAStep()
+{
+     $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1
+     if [ $? -ne 0 ]
+     then
+         exit
+     fi
+}
+EAStep vivado -log CPU.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source CPU.tcl
--- a/RISCV_CPU/RISCV_CPU.runs/synth_1/vivado.jou
+++ b/RISCV_CPU/RISCV_CPU.runs/synth_1/vivado.jou
+#-----------------------------------------------------------
+# Vivado v2018.1 (64-bit)
+# SW Build 2188600 on Wed Apr  4 18:40:38 MDT 2018
+# IP Build 2185939 on Wed Apr  4 20:55:05 MDT 2018
+# Start of session at: Wed Dec 22 22:45:27 2021
+# Process ID: 11108
+# Current directory: E:/verilogtest/RISCV_CPU/RISCV_CPU/RISCV_CPU.runs/synth_1
+# Command line: vivado.exe -log CPU.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source CPU.tcl
+# Log file: E:/verilogtest/RISCV_CPU/RISCV_CPU/RISCV_CPU.runs/synth_1/CPU.vds
+# Journal file: E:/verilogtest/RISCV_CPU/RISCV_CPU/RISCV_CPU.runs/synth_1\vivado.jou
+#-----------------------------------------------------------
+source CPU.tcl -notrace
--- a/RISCV_CPU/RISCV_CPU.runs/synth_1/vivado.pb
+++ b/RISCV_CPU/RISCV_CPU.runs/synth_1/vivado.pb
--- a/RISCV_CPU/RISCV_CPU.xpr
+++ b/RISCV_CPU/RISCV_CPU.xpr
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- Product Version: Vivado v2018.1 (64-bit)              -->
+<!--                                                         -->
+<!-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.   -->
+<Project Version="7" Minor="36" Path="E:/verilogtest/RISCV_CPU/RISCV_CPU/RISCV_CPU.xpr">
+  <DefaultLaunch Dir="$PRUNDIR"/>
+  <Configuration>
+    <Option Name="Id" Val="8463a5f9bcb34f8a8384fd0945cb1e96"/>
+    <Option Name="Part" Val="xc7vx485tffg1157-1"/>
+    <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
+    <Option Name="CompiledLibDirXSim" Val=""/>
+    <Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
+    <Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
+    <Option Name="CompiledLibDirIES" Val="$PCACHEDIR/compile_simlib/ies"/>
+    <Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
+    <Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
+    <Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
+    <Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
+    <Option Name="BoardPart" Val=""/>
+    <Option Name="SourceMgmtMode" Val="DisplayOnly"/>
+    <Option Name="ActiveSimSet" Val="sim_1"/>
+    <Option Name="DefaultLib" Val="xil_defaultlib"/>
+    <Option Name="ProjectType" Val="Default"/>
+    <Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
+    <Option Name="IPCachePermission" Val="read"/>
+    <Option Name="IPCachePermission" Val="write"/>
+    <Option Name="EnableCoreContainer" Val="FALSE"/>
+    <Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
+    <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
+    <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
+    <Option Name="EnableBDX" Val="FALSE"/>
+    <Option Name="DSAVendor" Val="xilinx"/>
+    <Option Name="DSANumComputeUnits" Val="60"/>
+    <Option Name="WTXSimLaunchSim" Val="0"/>
+    <Option Name="WTModelSimLaunchSim" Val="0"/>
+    <Option Name="WTQuestaLaunchSim" Val="0"/>
+    <Option Name="WTIesLaunchSim" Val="0"/>
+    <Option Name="WTVcsLaunchSim" Val="0"/>
+    <Option Name="WTRivieraLaunchSim" Val="0"/>
+    <Option Name="WTActivehdlLaunchSim" Val="0"/>
+    <Option Name="WTXSimExportSim" Val="0"/>
+    <Option Name="WTModelSimExportSim" Val="0"/>
+    <Option Name="WTQuestaExportSim" Val="0"/>
+    <Option Name="WTIesExportSim" Val="0"/>
+    <Option Name="WTVcsExportSim" Val="0"/>
+    <Option Name="WTRivieraExportSim" Val="0"/>
+    <Option Name="WTActivehdlExportSim" Val="0"/>
+    <Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
+    <Option Name="XSimRadix" Val="hex"/>
+    <Option Name="XSimTimeUnit" Val="ns"/>
+    <Option Name="XSimArrayDisplayLimit" Val="1024"/>
+    <Option Name="XSimTraceLimit" Val="65536"/>
+    <Option Name="SimTypes" Val="rtl"/>
+  </Configuration>
+  <FileSets Version="1" Minor="31">
+    <FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
+      <Filter Type="Srcs"/>
+      <File Path="$PPRDIR/../ROM.v">
+        <FileInfo>
+          <Attr Name="Library" Val="xil_defaultlib"/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../Registers.v">
+        <FileInfo>
+          <Attr Name="Library" Val="xil_defaultlib"/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../RAM.v">
+        <FileInfo>
+          <Attr Name="Library" Val="xil_defaultlib"/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../myreg.v">
+        <FileInfo>
+          <Attr Name="Library" Val="xil_defaultlib"/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../mux4.v">
+        <FileInfo>
+          <Attr Name="Library" Val="xil_defaultlib"/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../forward.v">
+        <FileInfo>
+          <Attr Name="Library" Val="xil_defaultlib"/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../dependence_detect.v">
+        <FileInfo>
+          <Attr Name="Library" Val="xil_defaultlib"/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../decoder.v">
+        <FileInfo>
+          <Attr Name="Library" Val="xil_defaultlib"/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../ALU.v">
+        <FileInfo>
+          <Attr Name="Library" Val="xil_defaultlib"/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../CPU.v">
+        <FileInfo>
+          <Attr Name="Library" Val="xil_defaultlib"/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/import_ise_summary.txt"/>
+      <Config>
+        <Option Name="DesignMode" Val="RTL"/>
+        <Option Name="TopModule" Val="CPU"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
+      <Filter Type="Constrs"/>
+      <Config>
+        <Option Name="ConstrsType" Val="XDC"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
+      <Config>
+        <Option Name="DesignMode" Val="RTL"/>
+        <Option Name="TopModule" Val="unknown"/>
+        <Option Name="TransportPathDelay" Val="0"/>
+        <Option Name="TransportIntDelay" Val="0"/>
+        <Option Name="SrcSet" Val="sources_1"/>
+      </Config>
+    </FileSet>
+  </FileSets>
+  <Simulators>
+    <Simulator Name="XSim">
+      <Option Name="Description" Val="Vivado Simulator"/>
+      <Option Name="CompiledLib" Val="0"/>
+    </Simulator>
+    <Simulator Name="ModelSim">
+      <Option Name="Description" Val="ModelSim Simulator"/>
+    </Simulator>
+    <Simulator Name="Questa">
+      <Option Name="Description" Val="Questa Advanced Simulator"/>
+    </Simulator>
+    <Simulator Name="Riviera">
+      <Option Name="Description" Val="Riviera-PRO Simulator"/>
+    </Simulator>
+    <Simulator Name="ActiveHDL">
+      <Option Name="Description" Val="Active-HDL Simulator"/>
+    </Simulator>
+  </Simulators>
+  <Runs Version="1" Minor="10">
+    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2018">
+          <Desc>Vivado Synthesis Defaults</Desc>
+        </StratHandle>
+        <Step Id="synth_design"/>
+      </Strategy>
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2018"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+    </Run>
+    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2018">
+          <Desc>Default settings for Implementation.</Desc>
+        </StratHandle>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2018"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+    </Run>
+  </Runs>
+  <Board/>
+</Project>
--- a/RISCV_CPU/import_ise_summary.txt
+++ b/RISCV_CPU/import_ise_summary.txt
--- a/ROM.v
+++ b/ROM.v
+`timescale 1ns / 1ps
+module ROM
+ #(
+   parameter INS_WIDTH = 32
+  )
+  (
+   input [31 : 0] addr,
+   output [INS_WIDTH-1 : 0] instruction
+  );
+  wire [31:0] rladdr;
+  assign rladdr=addr>>2;
+  reg [INS_WIDTH-1 : 0] rom_buffer [128 : 0];
+  //--------------------------------
+  //test
+  initial begin
+   /*rom_buffer[0]=32'b0000000_00001_00010_000_11110_0110011;//rs30=rs1+rs2·ÏÖ¸Áî
+	rom_buffer[1]=32'b0000000_00001_00010_000_00011_0110011;//rs3=rs1+rs2
+	rom_buffer[2]=32'b000000000010_00000_010_00101_0000011;//rs5=M[4]
+	rom_buffer[3]=32'b0000000_00101_00011_100_00111_0110011;//rs7=rs3+rs5
+	rom_buffer[4]=32'b0000000_00111_01000_110_01001_0110011;//rs9=rs7+rs8
+	rom_buffer[5]=32'b0000000_01001_01010_111_01011_0110011;//rs11=rs9+rs10
+	rom_buffer[6]=32'b0000000_01011_01100_000_01101_0110011;//rs13=rs11+rs12*/
+	/*rom_buffer[0]=32'b0000000_00001_00010_000_11110_0110011;//rs30=rs1+rs2·ÏÖ¸Áî
+	rom_buffer[1]=32'b0000000_00001_00010_000_00011_0110011;//rs3=rs1+rs2
+	rom_buffer[2]=32'b0000000_00100_00011_100_00101_0110011;//rs5=rs3^rs4
+	rom_buffer[3]=32'b0000000_00101_00011_100_00111_0110011;//rs7=rs3+rs5
+	rom_buffer[4]=32'b0000000_00111_01000_110_01001_0110011;//rs9=rs7+rs8
+	rom_buffer[5]=32'b0000000_01001_01010_111_01011_0110011;//rs11=rs9+rs10
+	rom_buffer[6]=32'b0000000_01011_01100_000_01101_0110011;//rs13=rs11+rs12*/
+	rom_buffer[0]=32'b0000000_00001_00010_000_11110_0110011;//rs30=rs1+rs2·ÏÖ¸Áî
+	rom_buffer[1]=32'b0000001_00001_00010_000_00000_1100011;//if(rs1==rs2) PC=PC+12;
+	//rom_buffer[2]=32'b0000000_00011_00000_010_00000_0100011;//CSB[2] = rs[3] = 4;
+	rom_buffer[2]=32'b000000000000_01001_010_01000_0000011;//rs[8] = RAM[6];
+	rom_buffer[3]=32'b0000000_00100_00001_010_00000_0100011;//CSB[3] = rs[4] = 2;
+	rom_buffer[4]=32'b0000000_00101_00010_010_00000_0100011;//CSB[0] = rs[5] = 1;
+	rom_buffer[5]=32'b0000000_01001_01010_111_01011_0110011;//rs11=rs9&rs10
+	rom_buffer[6]=32'b0000000_01011_01100_000_01101_0110011;//rs13=rs11+rs12
+	rom_buffer[7]=32'b0000000_00101_00011_100_00111_0110011;//rs7=rs3+rs5
+	rom_buffer[8]=32'b0000000_00111_01000_110_01001_0110011;//rs9=rs7+rs8
+	rom_buffer[9]=32'b0000000_01001_01010_111_01011_0110011;//rs11=rs9+rs10
+	rom_buffer[10]=32'b0000000_01011_01100_000_01101_0110011;//rs13=rs11+rs12*/
+	rom_buffer[11]=32'b0000000_00101_00011_100_00111_0110011;//rs7=rs3+rs5
+	rom_buffer[12]=32'b0000000_00111_01000_110_01001_0110011;//rs9=rs7+rs8
+	rom_buffer[13]=32'b0000000_01001_01010_111_01011_0110011;//rs11=rs9+rs10
+	rom_buffer[14]=32'b0000000_01011_01100_000_01101_0110011;//rs13=rs11+rs12*/
+	rom_buffer[15]=32'b0000000_00101_00011_100_00111_0110011;//rs7=rs3+rs5
+	rom_buffer[16]=32'b0000000_00111_01000_110_01001_0110011;//rs9=rs7+rs8
+	rom_buffer[17]=32'b0000000_01001_01010_111_01011_0110011;//rs11=rs9+rs10
+	rom_buffer[18]=32'b0000000_01011_01100_000_01101_0110011;//rs13=rs11+rs12*/
+	rom_buffer[19]=32'b0000000_00101_00011_100_00111_0110011;//rs7=rs3+rs5
+	rom_buffer[20]=32'b0000000_00111_01000_110_01001_0110011;//rs9=rs7+rs8
+	rom_buffer[21]=32'b0000000_01001_01010_111_01011_0110011;//rs11=rs9+rs10
+	rom_buffer[22]=32'b0000000_01011_01100_000_01101_0110011;//rs13=rs11+rs12*/
+	rom_buffer[23]=32'b0000000_00101_00011_100_00111_0110011;//rs7=rs3+rs5
+	rom_buffer[24]=32'b0000000_00111_01000_110_01001_0110011;//rs9=rs7+rs8
+	rom_buffer[25]=32'b0000000_01001_01010_111_01011_0110011;//rs11=rs9+rs10
+	rom_buffer[26]=32'b0000000_01011_01100_000_01101_0110011;//rs13=rs11+rs12*/
+	rom_buffer[27]=32'b0000000_00101_00011_100_00111_0110011;//rs7=rs3+rs5
+	rom_buffer[28]=32'b0000000_00111_01000_110_01001_0110011;//rs9=rs7+rs8
+	rom_buffer[29]=32'b0000000_01001_01010_111_01011_0110011;//rs11=rs9+rs10rom_buffer[3]=32'b0000000_00101_00011_100_00111_0110011;//rs7=rs3+rs5
+	rom_buffer[30]=32'b0000000_00111_01000_110_01001_0110011;//rs9=rs7+rs8
+	rom_buffer[31]=32'b0000000_01001_01010_111_01011_0110011;//rs11=rs9+rs10
+	rom_buffer[32]=32'b0000000_01011_01100_000_01101_0110011;//rs13=rs11+rs12*/
+	rom_buffer[33]=32'b0000000_00101_00011_100_00111_0110011;//rs7=rs3+rs5
+	rom_buffer[34]=32'b0000000_00111_01000_110_01001_0110011;//rs9=rs7+rs8
+	rom_buffer[35]=32'b0000000_01001_01010_111_01011_0110011;//rs11=rs9+rs10
+	rom_buffer[36]=32'b0000000_01011_01100_000_01101_0110011;//rs13=rs11+rs12*/
+	rom_buffer[37]=32'b0000000_00101_00011_100_00111_0110011;//rs7=rs3+rs5
+	rom_buffer[38]=32'b0000000_00111_01000_110_01001_0110011;//rs9=rs7+rs8
+	rom_buffer[39]=32'b0000000_01001_01010_111_01011_0110011;//rs11=rs9+rs10
+	rom_buffer[40]=32'b0000000_01011_01100_000_01101_0110011;//rs13=rs11+rs12*/
+	rom_buffer[41]=32'b0000000_00101_00011_100_00111_0110011;//rs7=rs3+rs5
+	rom_buffer[42]=32'b0000000_00111_01000_110_01001_0110011;//rs9=rs7+rs8
+	rom_buffer[43]=32'b0000000_01001_01010_111_01011_0110011;//rs11=rs9+rs10
+	rom_buffer[44]=32'b0000000_01011_01100_000_01101_0110011;//rs13=rs11+rs12*/
+	rom_buffer[45]=32'b0000000_00101_00011_100_00111_0110011;//rs7=rs3+rs5
+	rom_buffer[46]=32'b0000000_00111_01000_110_01001_0110011;//rs9=rs7+rs8
+	rom_buffer[47]=32'b0000000_01001_01010_111_01011_0110011;//rs11=rs9+rs10
+	rom_buffer[48]=32'b0000000_01011_01100_000_01101_0110011;//rs13=rs11+rs12*/
+	rom_buffer[49]=32'b0000000_00101_00011_100_00111_0110011;//rs7=rs3+rs5
+	rom_buffer[50]=32'b0000000_00111_01000_110_01001_0110011;//rs9=rs7+rs8
+	rom_buffer[51]=32'b0000000_01001_01010_111_01011_0110011;//rs11=rs9+rs10
+	rom_buffer[52]=32'b0000000_01011_01100_000_01101_0110011;//rs13=rs11+rs12*/
+	rom_buffer[53]=32'b0000000_00101_00011_100_00111_0110011;//rs7=rs3+rs5
+	rom_buffer[54]=32'b0000000_00111_01000_110_01001_0110011;//rs9=rs7+rs8
+	rom_buffer[55]=32'b0000000_01001_01010_111_01011_0110011;//rs11=rs9+rs10
+	rom_buffer[56]=32'b0000000_01011_01100_000_01101_0110011;//rs13=rs11+rs12*/
+	rom_buffer[57]=32'b0000000_00101_00011_100_00111_0110011;//rs7=rs3+rs5
+	rom_buffer[58]=32'b0000000_00111_01000_110_01001_0110011;//rs9=rs7+rs8
+	rom_buffer[59]=32'b0000000_01001_01010_111_01011_0110011;//rs11=rs9+rs10
+	rom_buffer[60]=32'b0000000_01011_01100_000_01101_0110011;//rs13=rs11+rs12*/
+	rom_buffer[61]=32'b0000000_00101_00011_100_00111_0110011;//rs7=rs3+rs5
+	rom_buffer[62]=32'b0000000_00111_01000_110_01001_0110011;//rs9=rs7+rs8
+	rom_buffer[63]=32'b0000000_01001_01010_111_01011_0110011;//rs11=rs9+rs10
+	rom_buffer[64]=32'b0000000_01011_01100_000_01101_0110011;//rs13=rs11+rs12*/
+	rom_buffer[65]=32'b0000000_00101_00011_100_00111_0110011;//rs7=rs3+rs5
+	rom_buffer[66]=32'b0000000_00111_01000_110_01001_0110011;//rs9=rs7+rs8
+	rom_buffer[67]=32'b0000000_01001_01010_111_01011_0110011;//rs11=rs9+rs10
+	rom_buffer[68]=32'b0000000_01011_01100_000_01101_0110011;//rs13=rs11+rs12*/
+	rom_buffer[69]=32'b0000000_00101_00011_100_00111_0110011;//rs7=rs3+rs5
+	rom_buffer[70]=32'b0000000_00111_01000_110_01001_0110011;//rs9=rs7+rs8
+	rom_buffer[71]=32'b0000000_01001_01010_111_01011_0110011;//rs11=rs9+rs10
+	rom_buffer[72]=32'b0000000_01011_01100_000_01101_0110011;//rs13=rs11+rs12*/
+	rom_buffer[73]=32'b0000000_00101_00011_100_00111_0110011;//rs7=rs3+rs5
+	rom_buffer[74]=32'b0000000_00111_01000_110_01001_0110011;//rs9=rs7+rs8
+	rom_buffer[75]=32'b0000000_01001_01010_111_01011_0110011;//rs11=rs9+rs10
+	rom_buffer[76]=32'b0000000_01011_01100_000_01101_0110011;//rs13=rs11+rs12*/
+	rom_buffer[77]=32'b0000000_00101_00011_100_00111_0110011;//rs7=rs3+rs5
+	rom_buffer[78]=32'b0000000_00111_01000_110_01001_0110011;//rs9=rs7+rs8
+	rom_buffer[79]=32'b0000000_01001_01010_111_01011_0110011;//rs11=rs9+rs10
+	rom_buffer[80]=32'b0000000_01011_01100_000_01101_0110011;//rs13=rs11+rs12*/
+	rom_buffer[81]=32'b0000000_00101_00011_100_00111_0110011;//rs7=rs3+rs5
+	rom_buffer[82]=32'b0000000_00111_01000_110_01001_0110011;//rs9=rs7+rs8
+	rom_buffer[83]=32'b0000000_01001_01010_111_01011_0110011;//rs11=rs9+rs10
+	rom_buffer[84]=32'b0000000_01011_01100_000_01101_0110011;//rs13=rs11+rs12*/
+	rom_buffer[85]=32'b0000000_00101_00011_100_00111_0110011;//rs7=rs3+rs5
+	rom_buffer[86]=32'b0000000_00111_01000_110_01001_0110011;//rs9=rs7+rs8
+	rom_buffer[87]=32'b0000000_01001_01010_111_01011_0110011;//rs11=rs9+rs10
+	rom_buffer[88]=32'b0000000_01011_01100_000_01101_0110011;//rs13=rs11+rs12*/
+	rom_buffer[89]=32'b0000000_00101_00011_100_00111_0110011;//rs7=rs3+rs5
+	rom_buffer[90]=32'b0000000_00111_01000_110_01001_0110011;//rs9=rs7+rs8
+	rom_buffer[91]=32'b0000000_01001_01010_111_01011_0110011;//rs11=rs9+rs10
+	rom_buffer[92]=32'b0000000_01011_01100_000_01101_0110011;//rs13=rs11+rs12*/
+	rom_buffer[93]=32'b0000000_00101_00011_100_00111_0110011;//rs7=rs3+rs5
+	rom_buffer[94]=32'b0000000_00111_01000_110_01001_0110011;//rs9=rs7+rs8
+	rom_buffer[95]=32'b0000000_01001_01010_111_01011_0110011;//rs11=rs9+rs10
+	rom_buffer[96]=32'b0000000_01011_01100_000_01101_0110011;//rs13=rs11+rs12*/
+	rom_buffer[97]=32'b0000000_00101_00011_100_00111_0110011;//rs7=rs3+rs5
+	rom_buffer[98]=32'b0000000_00111_01000_110_01001_0110011;//rs9=rs7+rs8
+	rom_buffer[99]=32'b0000000_01001_01010_111_01011_0110011;//rs11=rs9+rs10
+	rom_buffer[100]=32'b0000000_01011_01100_000_01101_0110011;//rs13=rs11+rs12*/
+  end
+  //--------------------------------
+  assign instruction = rom_buffer[rladdr];
+endmodule 
\ No newline at end of file
--- a/ROM_isim_beh.exe
+++ b/ROM_isim_beh.exe
--- a/ROM_stx_beh.prj
+++ b/ROM_stx_beh.prj
+verilog isim_temp "ROM.v"
+verilog isim_temp "E:/ISE/14.7/ISE_DS/ISE//verilog/src/glbl.v"
--- a/Registers.v
+++ b/Registers.v
+`timescale 1ns / 1ps
+module Registers
+ #(
+   parameter REG_WIDTH = 32,
+	parameter ADDR_WIDTH = 5
+  )
+  (
+	 input                            clk,
+    input                            write_en,
+    input      [ADDR_WIDTH-1 : 0]    addr1,
+    input      [ADDR_WIDTH-1 : 0]    addr2,
+    input      [ADDR_WIDTH-1 : 0]    write_addr,
+    input      [REG_WIDTH-1 : 0]     write_data,
+    output     [REG_WIDTH-1 : 0]     data1,
+    output     [REG_WIDTH-1 : 0]     data2
+  );
+//这里用了时序逻辑避免write_addr信号先改变导致regs[write_addr] = write_data写入发生错误
+//==========================================================
+//==    初始化寄存器组
+//==========================================================
+  reg [REG_WIDTH-1 : 0] regs [31 : 0];
+  //always@(*)
+  //begin
+    //regs[0] = 32'h0;
+  //end
+//==========================================================
+//==    向寄存器组写数据
+//==========================================================
+  always@(posedge clk)
+  begin
+    if(write_en)
+      regs[write_addr] = write_data;
+  end
+//==========================================================
+//==    从寄存器组读数据
+//==========================================================
+  assign data1 = regs[addr1];
+  assign data2 = regs[addr2];
+//------------------------------------------------
+//test
+	initial begin
+	   regs[0]=32'b00000000_00000000_00010000_00001000;
+		regs[1]=32'b00000000_00000000_00010000_00001100;
+		regs[2]=32'b00000000_00000000_00010000_00000000;
+		regs[3]=32'b00000000_00000000_00000000_00000100;
+		regs[4]=32'b00000000_00000000_00000000_00000010;
+		regs[5]=32'b00000000_00000000_00000000_00000001;
+		regs[6]=32'b00000001_10000000_00000000_00001000;
+		regs[7]=32'b00000001_10000000_00000000_00001100;
+		regs[8]=32'b00000001_00000001_00000000_00001000;
+		regs[9]=32'b00000000_00000000_00000000_00011000;
+		regs[10]=32'b00000001_10000000_00000000_00001000;
+		regs[11]=32'b00000001_10000000_00000000_00001011;
+		regs[12]=32'b00000001_10000000_00000000_00001000;
+		regs[13]=32'b00000001_10000000_00000000_00000100;
+		regs[14]=32'b00000001_10000000_00000000_00000100;
+		regs[15]=32'b00000001_10000000_00000000_00000100;
+		regs[16]=32'b00000001_10000000_00000000_00000100;
+		regs[17]=32'b00000001_10000000_00000000_00000100;
+		regs[18]=32'b00000001_10000000_00000000_00000100;
+		regs[19]=32'b00000001_10000000_00000000_00000100;
+		regs[20]=32'b00000001_10000000_00000000_00000100;
+		regs[22]=32'b00000001_10000000_00000000_00000100;
+	end
+endmodule 
\ No newline at end of file
--- a/_xmsgs/pn_parser.xmsgs
+++ b/_xmsgs/pn_parser.xmsgs
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- IMPORTANT: This is an internal file that has been generated   -->
+<!--     by the Xilinx ISE software.  Any direct editing or        -->
+<!--     changes made to this file may result in unpredictable     -->
+<!--     behavior or data corruption.  It is strongly advised that -->
+<!--     users do not edit the contents of this file.              -->
+<!--                                                               -->
+<!-- Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.    -->
+<messages>
+<msg type="info" file="ProjectMgmt" num="1845" ><arg fmt="%s" index="1">Analyzing Verilog file &quot;E:/verilogtest/RISCV_CPU/AXI_BUS_tb1.v&quot; into library work</arg>
+</msg>
+<msg type="info" file="ProjectMgmt" num="1845" ><arg fmt="%s" index="1">Analyzing Verilog file &quot;E:/verilogtest/RISCV_CPU/CPU_tb1.v&quot; into library work</arg>
+</msg>
+</messages>
--- a/_xmsgs/xst.xmsgs
+++ b/_xmsgs/xst.xmsgs
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- IMPORTANT: This is an internal file that has been generated
+     by the Xilinx ISE software.  Any direct editing or
+     changes made to this file may result in unpredictable
+     behavior or data corruption.  It is strongly advised that
+     users do not edit the contents of this file. -->
+<messages>
+<msg type="error" file="HDLCompilers" num="27" delta="old" ><arg fmt="%s" index="1">&quot;CPU.v&quot; line 293 </arg>Illegal redeclaration of &apos;<arg fmt="%s" index="2">ram_out_mem</arg>&apos;
+</msg>
+</messages>
--- a/decoder.v
+++ b/decoder.v
+`timescale 1ns / 1ps
+module decoder
+ #(
+    parameter INS_WIDTH    =    32,
+    parameter JUMP_OP      =    7'b1101111,
+	 parameter JR_OP        =    7'b1100111,
+    parameter BRANCH_OP    =    7'b1100011,
+    parameter LOAD_OP      =    7'b0000011,
+    parameter STORE_OP     =    7'b0100011,
+    parameter I_TYPE_OP    =    7'b0010011,
+    parameter R_TYPE_OP    =    7'b0110011,
+	 parameter LUI_OP       =    7'b0110111,
+	 parameter AUIPC_OP     =    7'b0010111, 
+    parameter BEQ_FUNCT    =    3'b000,
+    parameter BNE_FUNCT    =    3'b001,
+    parameter BLT_FUNCT    =    3'b100,
+    parameter BGE_FUNCT    =    3'b101,
+    parameter BLTU_FUNCT   =    3'b110,
+    parameter BGEU_FUNCT   =    3'b111,
+    parameter LW_FUNCT     =    3'b010,
+    parameter LH_FUNCT     =    3'b001,
+    parameter LB_FUNCT     =    3'b000,
+	 parameter LBU_FUNCT    =    3'b100,
+	 parameter LHU_FUNCT    =    3'b101,
+	 parameter SB_FUNCT     =    3'b000,
+	 parameter SH_FUNCT     =    3'b001,
+    parameter SW_FUNCT     =    3'b010,
+    parameter ADDI_FUNCT   =    3'b000,
+    parameter SLTI_FUNCT   =    3'b010,
+    parameter SLTIU_FUNCT  =    3'b011,
+    parameter XORI_FUNCT   =    3'b100,
+    parameter ORI_FUNCT    =    3'b110,
+    parameter ANDI_FUNCT   =    3'b111,
+    parameter SLLI_FUNCT   =    3'b001,
+    parameter SRLI_FUNCT   =    3'b101,
+    parameter SRAI_FUNCT   =    3'b101,
+    parameter ADD_FUNCT    =    3'b000,
+    parameter SUB_FUNCT    =    3'b000,
+    parameter SLL_FUNCT    =    3'b001,
+    parameter SLT_FUNCT    =    3'b010,
+    parameter SLTU_FUNCT   =    3'b011,
+    parameter XOR_FUNCT    =    3'b100,
+    parameter SRL_FUNCT    =    3'b101,
+    parameter SRA_FUNCT    =    3'b101,
+    parameter OR_FUNCT     =    3'b110,
+    parameter AND_FUNCT    =    3'b111,
+    parameter SUB_SRA_FUNCT =   7'b0100000
+  )
+  (
+    input      [31 : 0]    ins,
+    input      [31 : 0]    rs1_data,
+    input      [31 : 0]    rs2_data,
+    output                 J,
+    output                 JR,
+	 output                 LUI,
+	 output                 AUIPC,
+    output reg             Branch,
+    output                 ram_read,
+    output                 ram_write,
+    output                 regs_write,                 
+    output reg [1 : 0]     op_b_sel,
+    output reg [2 : 0]     load_type,
+	 output reg [1 : 0]     store_type,
+    output reg [5 : 0]     alu_op,
+	 output                 flush
+  );
+  assign flush=J||JR||Branch;
+  //截取op、funct3、funct7
+  wire [6 : 0] op,
+               funct7;
+  wire [2 : 0] funct3;
+  assign op = ins[6 : 0];
+  assign funct3 = ins[14 : 12];
+  assign funct7 = ins[31 : 25];
+  //Jump
+  assign J = op == JUMP_OP;
+  assign JR = op == JR_OP;
+  //LUI
+  assign LUI = op == LUI_OP;
+  //AUIPC
+  assign AUIPC = op ==AUIPC_OP;
+  //Branch是否跳转的判断
+  always@(*)
+  begin
+    if (op == BRANCH_OP) begin
+      case(funct3)
+        BEQ_FUNCT: begin
+                    if (rs1_data == rs2_data)
+                      Branch = 1;
+                    else
+                      Branch = 0;
+                   end
+        BNE_FUNCT: begin
+                    if (rs1_data != rs2_data)
+                      Branch = 1;
+                    else
+                      Branch = 0;
+                   end  
+        BLT_FUNCT: begin
+                    if ($signed(rs1_data) < $signed(rs2_data))
+                      Branch = 1;
+                    else
+                      Branch = 0;
+                   end
+        BGE_FUNCT: begin
+                    if ($signed(rs1_data) >= $signed(rs2_data))
+                      Branch = 1;
+                    else
+                      Branch = 0;
+                   end
+        BLTU_FUNCT: begin
+                      if (rs1_data < rs2_data)
+                        Branch = 1;
+                      else
+                        Branch = 0;
+                    end 
+        BGEU_FUNCT: begin
+                      if (rs1_data >= rs2_data)
+                        Branch = 1;
+                      else
+                        Branch = 0;
+                    end
+		  default   : Branch = 0;
+      endcase
+    end
+	 else Branch = 0;
+  end
+  //Load & Store
+  always@(*)
+  begin
+    if (op == LOAD_OP)begin
+      op_b_sel = 2'b01;
+      case(funct3)
+        LW_FUNCT:  load_type = 3'b000;
+        LH_FUNCT:  load_type = 3'b001;
+        LB_FUNCT:  load_type = 3'b010;
+        LBU_FUNCT: load_type = 3'b011;
+		  LHU_FUNCT: load_type = 3'b100;
+		  default  : load_type = 3'b101;
+      endcase
+    end
+    else if (op == STORE_OP)begin
+      op_b_sel = 2'b10;
+		case(funct3)
+			SB_FUNCT:  store_type = 2'b00;
+			SH_FUNCT:  store_type = 2'b01;
+			SW_FUNCT:  store_type = 2'b10;
+			default :  store_type = 2'b11;
+		endcase
+	 end
+	 else if(op == I_TYPE_OP)
+		op_b_sel = 2'b01;
+	 else if(op == R_TYPE_OP)
+		op_b_sel = 2'b00;
+	 else 
+		op_b_sel=2'b11;
+  end
+  //把指令分为几大类R、I、S、L
+  wire   r_type_ins, i_type_ins, load_ins, store_ins;
+  assign load_ins   = op == LOAD_OP;
+  assign store_ins  = op == STORE_OP;
+  assign i_type_ins = op == I_TYPE_OP;
+  assign r_type_ins = op == R_TYPE_OP;
+  //控制信号的定义
+  assign ram_read   = load_ins;
+  assign ram_write  = store_ins;
+  assign regs_write = r_type_ins || i_type_ins || load_ins || J || JR || LUI || AUIPC;
+  //定义不同指令的ALU_Code,并将其送入ALU
+  localparam alu_ram   =  6'b000000;
+  localparam alu_add   =  6'b000001;
+  localparam alu_sub   =  6'b001010;
+  localparam alu_slt   =  6'b000010;
+  localparam alu_sltu  =  6'b000011;
+  localparam alu_sll   =  6'b000100;
+  localparam alu_srl   =  6'b000101;
+  localparam alu_sra   =  6'b000110;
+  localparam alu_xor   =  6'b000111;
+  localparam alu_or    =  6'b001000;
+  localparam alu_and   =  6'b001001;
+  localparam alu_nop   =  6'b111111;
+  always@(*)
+  begin
+    case(op)
+      LOAD_OP:    alu_op = alu_ram;
+      STORE_OP:   alu_op = alu_ram;
+      I_TYPE_OP:  begin
+                    case(funct3)
+                      ADDI_FUNCT:   alu_op = alu_add;
+                      SLTI_FUNCT:   alu_op = alu_slt;
+                      SLTIU_FUNCT:  alu_op = alu_sltu;
+                      SLLI_FUNCT:   alu_op = alu_sll;
+                      SRLI_FUNCT:   if(funct7 == SUB_SRA_FUNCT)
+                                      alu_op = alu_sra;
+                                    else
+                                      alu_op = alu_srl;
+                      XORI_FUNCT:   alu_op = alu_xor;
+                      ORI_FUNCT:    alu_op = alu_or;
+                      ANDI_FUNCT:   alu_op = alu_and;
+                      default:      alu_op = alu_nop;
+                    endcase
+                  end           
+      R_TYPE_OP:  begin
+                    case(funct3)
+                      ADD_FUNCT:    if(funct7 == SUB_SRA_FUNCT)
+                                      alu_op = alu_sub;
+                                    else
+                                      alu_op = alu_add;
+                      SLT_FUNCT:    alu_op = alu_slt;
+                      SLTU_FUNCT:   alu_op = alu_sltu;
+                      SLL_FUNCT:    alu_op = alu_sll;
+                      SRL_FUNCT:    if(funct7 == SUB_SRA_FUNCT)
+                                      alu_op = alu_sra;
+                                    else
+                                      alu_op = alu_srl;
+                      XOR_FUNCT:    alu_op = alu_xor;
+                      OR_FUNCT:     alu_op = alu_or;
+                      AND_FUNCT:    alu_op = alu_and;
+                      default:      alu_op = alu_nop;
+                    endcase
+                  end
+      default:    alu_op = alu_nop;
+    endcase
+  end
+endmodule
--- a/decoder_isim_beh.exe
+++ b/decoder_isim_beh.exe
--- a/decoder_stx_beh.prj
+++ b/decoder_stx_beh.prj
+verilog isim_temp "decoder.v"
+verilog isim_temp "E:/ISE/14.7/ISE_DS/ISE//verilog/src/glbl.v"
--- a/dependence_detect.v
+++ b/dependence_detect.v
+`timescale 1ns / 1ns
+//采用气泡处理LOAD指令的目标地址是下一个指令所用寄存器地址的数据依赖
+module dependence_detect
+  (
+   input            ram_read_ex,
+   input  [4 : 0]   rd_addr_ex,
+   input  [4 : 0]   rs1_addr_id,
+   input  [4 : 0]   rs2_addr_id,
+   output           stall,
+   output           pc_en
+  );
+   assign stall = ram_read_ex && ((rd_addr_ex == rs1_addr_id) || (rd_addr_ex == rs2_addr_id));
+   assign pc_en = ~stall;
+endmodule 
\ No newline at end of file
--- a/forward.v
+++ b/forward.v
+`timescale 1ns / 1ns
+// Description:
+// 处理器中负责转发的模块，forward_a和forward_b分别是用来表明rs1_data和rs2_data是否应该进行转发的握手信号。
+// forward = 2'b00时，不需要进行转发。
+// forward = 2'b01时，需要转发处在wb阶段的运算结果。
+// forward = 2'b10时，需要转发处在mem阶段的运算结果。
+module forward
+  (
+   input                regs_write_ex,
+   input                regs_write_mem,
+   input                regs_write_wb,
+	input                ram_read_mem,
+   input      [4 : 0]   rs1_addr_ex,
+   input      [4 : 0]   rs2_addr_ex,
+   input      [4 : 0]   rd_addr_mem,
+   input      [4 : 0]   rd_addr_wb,
+   output     [1 : 0]   forward_a,
+   output     [1 : 0]   forward_b
+  );
+//-- 判断rs1是否是上两条指令的目标寄存器, mem的优先级大于wb.
+  assign forward_a[1] = (regs_write_ex===1'b1) && ((regs_write_mem===1'b1)||(ram_read_mem===1'b1)) && (rs1_addr_ex === rd_addr_mem);
+  assign forward_a[0] = (regs_write_ex===1'b1) && ((regs_write_wb===1'b1) &&( !((rs1_addr_ex === rd_addr_mem) && (regs_write_mem===1'b1)) && (rs1_addr_ex === rd_addr_wb))||((ram_read_mem===1'b1)&&(rs1_addr_ex === rd_addr_mem)));
+//-- 判断rs2是否是上两条指令的目标寄存器.
+  assign forward_b[1] = (regs_write_ex===1'b1) && ((regs_write_mem===1'b1)||(ram_read_mem===1'b1)) && (rs2_addr_ex === rd_addr_mem);
+  assign forward_b[0] = (regs_write_ex===1'b1) && ((regs_write_wb===1'b1) &&( !((rs2_addr_ex === rd_addr_mem) && (regs_write_mem===1'b1)) && (rs2_addr_ex === rd_addr_wb))||((ram_read_mem===1'b1)&&(rs2_addr_ex === rd_addr_mem)));
+endmodule 
\ No newline at end of file
--- a/forward_isim_beh.exe
+++ b/forward_isim_beh.exe
--- a/forward_stx_beh.prj
+++ b/forward_stx_beh.prj
+verilog isim_temp "forward.v"
+verilog isim_temp "E:/ISE/14.7/ISE_DS/ISE//verilog/src/glbl.v"
--- a/fuse.log
+++ b/fuse.log
+Running: E:\ISE\14.7\ISE_DS\ISE\bin\nt64\unwrapped\fuse.exe -intstyle ise -incremental -lib unisims_ver -lib unimacro_ver -lib xilinxcorelib_ver -o E:/verilogtest/RISCV_CPU/AXI_BUS_tb1_isim_beh.exe -prj E:/verilogtest/RISCV_CPU/AXI_BUS_tb1_beh.prj work.AXI_BUS_tb1 work.glbl 
+ISim P.20131013 (signature 0x7708f090)
+Number of CPUs detected in this system: 8
+Turning on mult-threading, number of parallel sub-compilation jobs: 16 
+Determining compilation order of HDL files
+Analyzing Verilog file "E:/verilogtest/RISCV_CPU/ROM.v" into library work
+Analyzing Verilog file "E:/verilogtest/RISCV_CPU/Registers.v" into library work
+Analyzing Verilog file "E:/verilogtest/RISCV_CPU/myreg.v" into library work
+Analyzing Verilog file "E:/verilogtest/RISCV_CPU/mux4.v" into library work
+Analyzing Verilog file "E:/verilogtest/RISCV_CPU/forward.v" into library work
+Analyzing Verilog file "E:/verilogtest/RISCV_CPU/decoder.v" into library work
+Analyzing Verilog file "E:/verilogtest/RISCV_CPU/ALU.v" into library work
+Analyzing Verilog file "E:/verilogtest/RISCV_CPU/RAM.v" into library work
+Analyzing Verilog file "E:/verilogtest/RISCV_CPU/NVDLA.v" into library work
+WARNING:HDLCompiler:693 - "E:/verilogtest/RISCV_CPU/NVDLA.v" Line 153: Parameter declaration becomes local in NVDLA with formal parameter declaration list
+WARNING:HDLCompiler:693 - "E:/verilogtest/RISCV_CPU/NVDLA.v" Line 154: Parameter declaration becomes local in NVDLA with formal parameter declaration list
+WARNING:HDLCompiler:693 - "E:/verilogtest/RISCV_CPU/NVDLA.v" Line 155: Parameter declaration becomes local in NVDLA with formal parameter declaration list
+WARNING:HDLCompiler:693 - "E:/verilogtest/RISCV_CPU/NVDLA.v" Line 156: Parameter declaration becomes local in NVDLA with formal parameter declaration list
+WARNING:HDLCompiler:693 - "E:/verilogtest/RISCV_CPU/NVDLA.v" Line 157: Parameter declaration becomes local in NVDLA with formal parameter declaration list
+WARNING:HDLCompiler:693 - "E:/verilogtest/RISCV_CPU/NVDLA.v" Line 158: Parameter declaration becomes local in NVDLA with formal parameter declaration list
+Analyzing Verilog file "E:/verilogtest/RISCV_CPU/CPU.v" into library work
+WARNING:HDLCompiler:35 - "E:/verilogtest/RISCV_CPU/CPU.v" Line 308: <ram_out_mem> is already implicitly declared earlier.
+Analyzing Verilog file "E:/verilogtest/RISCV_CPU/RAM_CONTROL.v" into library work
+Analyzing Verilog file "E:/verilogtest/RISCV_CPU/NVDLA_CONTROL.v" into library work
+Analyzing Verilog file "E:/verilogtest/RISCV_CPU/CPU_CONTROL.v" into library work
+Analyzing Verilog file "E:/verilogtest/RISCV_CPU/AXI_BUS.v" into library work
+Analyzing Verilog file "E:/verilogtest/RISCV_CPU/AXI_BUS_tb1.v" into library work
+Analyzing Verilog file "E:/ISE/14.7/ISE_DS/ISE//verilog/src/glbl.v" into library work
+Starting static elaboration
+WARNING:HDLCompiler:189 - "E:/verilogtest/RISCV_CPU/AXI_BUS.v" Line 727: Size mismatch in connection of port <RAM_S_AXI_AWUSER>. Formal port size is 2-bit while actual signal size is 1-bit.
+WARNING:HDLCompiler:189 - "E:/verilogtest/RISCV_CPU/AXI_BUS.v" Line 733: Size mismatch in connection of port <RAM_S_AXI_WUSER>. Formal port size is 2-bit while actual signal size is 1-bit.
+WARNING:HDLCompiler:189 - "E:/verilogtest/RISCV_CPU/AXI_BUS.v" Line 738: Size mismatch in connection of port <RAM_S_AXI_BUSER>. Formal port size is 2-bit while actual signal size is 1-bit.
+WARNING:HDLCompiler:189 - "E:/verilogtest/RISCV_CPU/AXI_BUS.v" Line 751: Size mismatch in connection of port <RAM_S_AXI_ARUSER>. Formal port size is 2-bit while actual signal size is 1-bit.
+WARNING:HDLCompiler:189 - "E:/verilogtest/RISCV_CPU/AXI_BUS.v" Line 758: Size mismatch in connection of port <RAM_S_AXI_RUSER>. Formal port size is 2-bit while actual signal size is 1-bit.
+WARNING:HDLCompiler:189 - "E:/verilogtest/RISCV_CPU/AXI_BUS.v" Line 774: Size mismatch in connection of port <CPU_AWUSER>. Formal port size is 2-bit while actual signal size is 1-bit.
+WARNING:HDLCompiler:189 - "E:/verilogtest/RISCV_CPU/AXI_BUS.v" Line 780: Size mismatch in connection of port <CPU_WUSER>. Formal port size is 2-bit while actual signal size is 1-bit.
+WARNING:HDLCompiler:189 - "E:/verilogtest/RISCV_CPU/AXI_BUS.v" Line 785: Size mismatch in connection of port <CPU_BUSER>. Formal port size is 2-bit while actual signal size is 1-bit.
+WARNING:HDLCompiler:189 - "E:/verilogtest/RISCV_CPU/AXI_BUS.v" Line 797: Size mismatch in connection of port <CPU_ARUSER>. Formal port size is 2-bit while actual signal size is 1-bit.
+WARNING:HDLCompiler:189 - "E:/verilogtest/RISCV_CPU/AXI_BUS.v" Line 804: Size mismatch in connection of port <CPU_RUSER>. Formal port size is 2-bit while actual signal size is 1-bit.
+WARNING:HDLCompiler:189 - "E:/verilogtest/RISCV_CPU/CPU.v" Line 164: Size mismatch in connection of port <LUI>. Formal port size is 1-bit while actual signal size is 32-bit.
+WARNING:HDLCompiler:189 - "E:/verilogtest/RISCV_CPU/CPU.v" Line 165: Size mismatch in connection of port <AUIPC>. Formal port size is 1-bit while actual signal size is 32-bit.
+WARNING:HDLCompiler:189 - "E:/verilogtest/RISCV_CPU/CPU.v" Line 204: Size mismatch in connection of port <in>. Formal port size is 1-bit while actual signal size is 32-bit.
+WARNING:HDLCompiler:189 - "E:/verilogtest/RISCV_CPU/CPU.v" Line 205: Size mismatch in connection of port <in>. Formal port size is 1-bit while actual signal size is 32-bit.
+WARNING:HDLCompiler:189 - "E:/verilogtest/RISCV_CPU/CPU.v" Line 283: Size mismatch in connection of port <in>. Formal port size is 1-bit while actual signal size is 32-bit.
+WARNING:HDLCompiler:189 - "E:/verilogtest/RISCV_CPU/CPU.v" Line 284: Size mismatch in connection of port <in>. Formal port size is 1-bit while actual signal size is 32-bit.
+WARNING:HDLCompiler:189 - "E:/verilogtest/RISCV_CPU/CPU.v" Line 338: Size mismatch in connection of port <in>. Formal port size is 1-bit while actual signal size is 32-bit.
+WARNING:HDLCompiler:189 - "E:/verilogtest/RISCV_CPU/CPU.v" Line 339: Size mismatch in connection of port <in>. Formal port size is 1-bit while actual signal size is 32-bit.
+Completed static elaboration
+Compiling module NVDLA
+Compiling module NVDLA_CONTROL_default
+Compiling module RAM_default
+Compiling module RAM_CONTROL_default
+Compiling module myreg
+Compiling module ROM
+Compiling module decoder
+Compiling module Registers
+Compiling module myreg(REG_WIDTH=1)
+Compiling module myreg(REG_WIDTH=5)
+Compiling module myreg(REG_WIDTH=3)
+Compiling module myreg(REG_WIDTH=2)
+Compiling module myreg(REG_WIDTH=6)
+Compiling module forward
+Compiling module mux4
+Compiling module ALU
+Compiling module CPU
+Compiling module CPU_CONTROL
+Compiling module AXI_BUS
+Compiling module AXI_BUS_tb1
+Compiling module glbl
+Time Resolution for simulation is 1ps.
+Waiting for 6 sub-compilation(s) to finish...
+Compiled 21 Verilog Units
+Built simulation executable E:/verilogtest/RISCV_CPU/AXI_BUS_tb1_isim_beh.exe
+Fuse Memory Usage: 33416 KB
+Fuse CPU Usage: 718 ms
--- a/fuse.xmsgs
+++ b/fuse.xmsgs
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- IMPORTANT: This is an internal file that has been generated
+     by the Xilinx ISE software.  Any direct editing or
+     changes made to this file may result in unpredictable
+     behavior or data corruption.  It is strongly advised that
+     users do not edit the contents of this file. -->
+<messages>
+<msg type="warning" file="HDLCompiler" num="693" delta="unknown" >"E:/verilogtest/RISCV_CPU/NVDLA.v" Line 153: Parameter declaration becomes local in <arg fmt="%s" index="1">NVDLA</arg> with formal parameter declaration list
+</msg>
+<msg type="warning" file="HDLCompiler" num="693" delta="unknown" >"E:/verilogtest/RISCV_CPU/NVDLA.v" Line 154: Parameter declaration becomes local in <arg fmt="%s" index="1">NVDLA</arg> with formal parameter declaration list
+</msg>
+<msg type="warning" file="HDLCompiler" num="693" delta="unknown" >"E:/verilogtest/RISCV_CPU/NVDLA.v" Line 155: Parameter declaration becomes local in <arg fmt="%s" index="1">NVDLA</arg> with formal parameter declaration list
+</msg>
+<msg type="warning" file="HDLCompiler" num="693" delta="unknown" >"E:/verilogtest/RISCV_CPU/NVDLA.v" Line 156: Parameter declaration becomes local in <arg fmt="%s" index="1">NVDLA</arg> with formal parameter declaration list
+</msg>
+<msg type="warning" file="HDLCompiler" num="693" delta="unknown" >"E:/verilogtest/RISCV_CPU/NVDLA.v" Line 157: Parameter declaration becomes local in <arg fmt="%s" index="1">NVDLA</arg> with formal parameter declaration list
+</msg>
+<msg type="warning" file="HDLCompiler" num="693" delta="unknown" >"E:/verilogtest/RISCV_CPU/NVDLA.v" Line 158: Parameter declaration becomes local in <arg fmt="%s" index="1">NVDLA</arg> with formal parameter declaration list
+</msg>
+<msg type="warning" file="HDLCompiler" num="35" delta="unknown" >"E:/verilogtest/RISCV_CPU/CPU.v" Line 308: &lt;<arg fmt="%s" index="1">ram_out_mem</arg>&gt; is already implicitly declared earlier.
+</msg>
+<msg type="warning" file="HDLCompiler" num="189" delta="unknown" >"E:/verilogtest/RISCV_CPU/AXI_BUS.v" Line 727: Size mismatch in connection of port &lt;<arg fmt="%s" index="3">RAM_S_AXI_AWUSER</arg>&gt;. Formal port size is <arg fmt="%d" index="2">2</arg>-bit while actual signal size is <arg fmt="%d" index="1">1</arg>-bit.
+</msg>
+<msg type="warning" file="HDLCompiler" num="189" delta="unknown" >"E:/verilogtest/RISCV_CPU/AXI_BUS.v" Line 733: Size mismatch in connection of port &lt;<arg fmt="%s" index="3">RAM_S_AXI_WUSER</arg>&gt;. Formal port size is <arg fmt="%d" index="2">2</arg>-bit while actual signal size is <arg fmt="%d" index="1">1</arg>-bit.
+</msg>
+<msg type="warning" file="HDLCompiler" num="189" delta="unknown" >"E:/verilogtest/RISCV_CPU/AXI_BUS.v" Line 738: Size mismatch in connection of port &lt;<arg fmt="%s" index="3">RAM_S_AXI_BUSER</arg>&gt;. Formal port size is <arg fmt="%d" index="2">2</arg>-bit while actual signal size is <arg fmt="%d" index="1">1</arg>-bit.
+</msg>
+<msg type="warning" file="HDLCompiler" num="189" delta="unknown" >"E:/verilogtest/RISCV_CPU/AXI_BUS.v" Line 751: Size mismatch in connection of port &lt;<arg fmt="%s" index="3">RAM_S_AXI_ARUSER</arg>&gt;. Formal port size is <arg fmt="%d" index="2">2</arg>-bit while actual signal size is <arg fmt="%d" index="1">1</arg>-bit.
+</msg>
+<msg type="warning" file="HDLCompiler" num="189" delta="unknown" >"E:/verilogtest/RISCV_CPU/AXI_BUS.v" Line 758: Size mismatch in connection of port &lt;<arg fmt="%s" index="3">RAM_S_AXI_RUSER</arg>&gt;. Formal port size is <arg fmt="%d" index="2">2</arg>-bit while actual signal size is <arg fmt="%d" index="1">1</arg>-bit.
+</msg>
+<msg type="warning" file="HDLCompiler" num="189" delta="unknown" >"E:/verilogtest/RISCV_CPU/AXI_BUS.v" Line 774: Size mismatch in connection of port &lt;<arg fmt="%s" index="3">CPU_AWUSER</arg>&gt;. Formal port size is <arg fmt="%d" index="2">2</arg>-bit while actual signal size is <arg fmt="%d" index="1">1</arg>-bit.
+</msg>
+<msg type="warning" file="HDLCompiler" num="189" delta="unknown" >"E:/verilogtest/RISCV_CPU/AXI_BUS.v" Line 780: Size mismatch in connection of port &lt;<arg fmt="%s" index="3">CPU_WUSER</arg>&gt;. Formal port size is <arg fmt="%d" index="2">2</arg>-bit while actual signal size is <arg fmt="%d" index="1">1</arg>-bit.
+</msg>
+<msg type="warning" file="HDLCompiler" num="189" delta="unknown" >"E:/verilogtest/RISCV_CPU/AXI_BUS.v" Line 785: Size mismatch in connection of port &lt;<arg fmt="%s" index="3">CPU_BUSER</arg>&gt;. Formal port size is <arg fmt="%d" index="2">2</arg>-bit while actual signal size is <arg fmt="%d" index="1">1</arg>-bit.
+</msg>
+<msg type="warning" file="HDLCompiler" num="189" delta="unknown" >"E:/verilogtest/RISCV_CPU/AXI_BUS.v" Line 797: Size mismatch in connection of port &lt;<arg fmt="%s" index="3">CPU_ARUSER</arg>&gt;. Formal port size is <arg fmt="%d" index="2">2</arg>-bit while actual signal size is <arg fmt="%d" index="1">1</arg>-bit.
+</msg>
+<msg type="warning" file="HDLCompiler" num="189" delta="unknown" >"E:/verilogtest/RISCV_CPU/AXI_BUS.v" Line 804: Size mismatch in connection of port &lt;<arg fmt="%s" index="3">CPU_RUSER</arg>&gt;. Formal port size is <arg fmt="%d" index="2">2</arg>-bit while actual signal size is <arg fmt="%d" index="1">1</arg>-bit.
+</msg>
+<msg type="warning" file="HDLCompiler" num="189" delta="unknown" >"E:/verilogtest/RISCV_CPU/CPU.v" Line 164: Size mismatch in connection of port &lt;<arg fmt="%s" index="3">LUI</arg>&gt;. Formal port size is <arg fmt="%d" index="2">1</arg>-bit while actual signal size is <arg fmt="%d" index="1">32</arg>-bit.
+</msg>
+<msg type="warning" file="HDLCompiler" num="189" delta="unknown" >"E:/verilogtest/RISCV_CPU/CPU.v" Line 165: Size mismatch in connection of port &lt;<arg fmt="%s" index="3">AUIPC</arg>&gt;. Formal port size is <arg fmt="%d" index="2">1</arg>-bit while actual signal size is <arg fmt="%d" index="1">32</arg>-bit.
+</msg>
+<msg type="warning" file="HDLCompiler" num="189" delta="unknown" >"E:/verilogtest/RISCV_CPU/CPU.v" Line 204: Size mismatch in connection of port &lt;<arg fmt="%s" index="3">in</arg>&gt;. Formal port size is <arg fmt="%d" index="2">1</arg>-bit while actual signal size is <arg fmt="%d" index="1">32</arg>-bit.
+</msg>
+<msg type="warning" file="HDLCompiler" num="189" delta="unknown" >"E:/verilogtest/RISCV_CPU/CPU.v" Line 205: Size mismatch in connection of port &lt;<arg fmt="%s" index="3">in</arg>&gt;. Formal port size is <arg fmt="%d" index="2">1</arg>-bit while actual signal size is <arg fmt="%d" index="1">32</arg>-bit.
+</msg>
+<msg type="warning" file="HDLCompiler" num="189" delta="unknown" >"E:/verilogtest/RISCV_CPU/CPU.v" Line 283: Size mismatch in connection of port &lt;<arg fmt="%s" index="3">in</arg>&gt;. Formal port size is <arg fmt="%d" index="2">1</arg>-bit while actual signal size is <arg fmt="%d" index="1">32</arg>-bit.
+</msg>
+<msg type="warning" file="HDLCompiler" num="189" delta="unknown" >"E:/verilogtest/RISCV_CPU/CPU.v" Line 284: Size mismatch in connection of port &lt;<arg fmt="%s" index="3">in</arg>&gt;. Formal port size is <arg fmt="%d" index="2">1</arg>-bit while actual signal size is <arg fmt="%d" index="1">32</arg>-bit.
+</msg>
+<msg type="warning" file="HDLCompiler" num="189" delta="unknown" >"E:/verilogtest/RISCV_CPU/CPU.v" Line 338: Size mismatch in connection of port &lt;<arg fmt="%s" index="3">in</arg>&gt;. Formal port size is <arg fmt="%d" index="2">1</arg>-bit while actual signal size is <arg fmt="%d" index="1">32</arg>-bit.
+</msg>
+<msg type="warning" file="HDLCompiler" num="189" delta="unknown" >"E:/verilogtest/RISCV_CPU/CPU.v" Line 339: Size mismatch in connection of port &lt;<arg fmt="%s" index="3">in</arg>&gt;. Formal port size is <arg fmt="%d" index="2">1</arg>-bit while actual signal size is <arg fmt="%d" index="1">32</arg>-bit.
+</msg>
+</messages>
--- a/fuseRelaunch.cmd
+++ b/fuseRelaunch.cmd
+-intstyle "ise" -incremental -lib "unisims_ver" -lib "unimacro_ver" -lib "xilinxcorelib_ver" -o "E:/verilogtest/RISCV_CPU/AXI_BUS_tb1_isim_beh.exe" -prj "E:/verilogtest/RISCV_CPU/AXI_BUS_tb1_beh.prj" "work.AXI_BUS_tb1" "work.glbl" 
--- a/iseconfig/AXI_BUS.xreport
+++ b/iseconfig/AXI_BUS.xreport
--- a/iseconfig/CPU.xreport
+++ b/iseconfig/CPU.xreport
--- a/iseconfig/RISCV_CPU.projectmgr
+++ b/iseconfig/RISCV_CPU.projectmgr
--- a/isim.cmd
+++ b/isim.cmd
+onerror {resume}
+wave add /
+run 1000 ns;
--- a/isim.log
+++ b/isim.log
+ISim log file
+Running: E:\verilogtest\RISCV_CPU\AXI_BUS_tb1_isim_beh.exe -intstyle ise -gui -tclbatch isim.cmd -wdb E:/verilogtest/RISCV_CPU/AXI_BUS_tb1_isim_beh.wdb 
+ISim P.20131013 (signature 0x7708f090)
+This is a Full version of ISim.
+WARNING: File "E:/verilogtest/RISCV_CPU/AXI_BUS.v" Line 328.  For instance uut/RAM0/, width 2 of formal port RAM_S_AXI_AWUSER is not equal to width 1 of actual signal RAM_S_AXI_AWUSER.
+WARNING: File "E:/verilogtest/RISCV_CPU/AXI_BUS.v" Line 347.  For instance uut/RAM0/, width 2 of formal port RAM_S_AXI_WUSER is not equal to width 1 of actual signal RAM_S_AXI_WUSER.
+WARNING: File "E:/verilogtest/RISCV_CPU/AXI_BUS.v" Line 361.  For instance uut/RAM0/, width 2 of formal port RAM_S_AXI_BUSER is not equal to width 1 of actual signal RAM_S_AXI_BUSER.
+WARNING: File "E:/verilogtest/RISCV_CPU/AXI_BUS.v" Line 398.  For instance uut/RAM0/, width 2 of formal port RAM_S_AXI_ARUSER is not equal to width 1 of actual signal RAM_S_AXI_ARUSER.
+WARNING: File "E:/verilogtest/RISCV_CPU/AXI_BUS.v" Line 419.  For instance uut/RAM0/, width 2 of formal port RAM_S_AXI_RUSER is not equal to width 1 of actual signal RAM_S_AXI_RUSER.
+WARNING: File "E:/verilogtest/RISCV_CPU/CPU.v" Line 29.  For instance CPU0/cpu_decoder/, width 1 of formal port LUI is not equal to width 32 of actual signal lui_id.
+WARNING: File "E:/verilogtest/RISCV_CPU/CPU.v" Line 33.  For instance CPU0/cpu_decoder/, width 1 of formal port AUIPC is not equal to width 32 of actual signal auipc_id.
+WARNING: File "E:/verilogtest/RISCV_CPU/CPU.v" Line 29.  For instance CPU0/lui_id_ex/, width 1 of formal port in is not equal to width 32 of actual signal lui_id.
+WARNING: File "E:/verilogtest/RISCV_CPU/CPU.v" Line 30.  For instance CPU0/lui_id_ex/, width 1 of formal port out is not equal to width 32 of actual signal lui_ex.
+WARNING: File "E:/verilogtest/RISCV_CPU/CPU.v" Line 33.  For instance CPU0/auipc_id_ex/, width 1 of formal port in is not equal to width 32 of actual signal auipc_id.
+WARNING: File "E:/verilogtest/RISCV_CPU/CPU.v" Line 34.  For instance CPU0/auipc_id_ex/, width 1 of formal port out is not equal to width 32 of actual signal auipc_ex.
+WARNING: File "E:/verilogtest/RISCV_CPU/CPU.v" Line 30.  For instance CPU0/lui_ex_mem/, width 1 of formal port in is not equal to width 32 of actual signal lui_ex.
+WARNING: File "E:/verilogtest/RISCV_CPU/CPU.v" Line 31.  For instance CPU0/lui_ex_mem/, width 1 of formal port out is not equal to width 32 of actual signal lui_mem.
+WARNING: File "E:/verilogtest/RISCV_CPU/CPU.v" Line 34.  For instance CPU0/auipc_ex_mem/, width 1 of formal port in is not equal to width 32 of actual signal auipc_ex.
+WARNING: File "E:/verilogtest/RISCV_CPU/CPU.v" Line 35.  For instance CPU0/auipc_ex_mem/, width 1 of formal port out is not equal to width 32 of actual signal auipc_mem.
+WARNING: File "E:/verilogtest/RISCV_CPU/CPU.v" Line 31.  For instance CPU0/lui_mem_wb/, width 1 of formal port in is not equal to width 32 of actual signal lui_mem.
+WARNING: File "E:/verilogtest/RISCV_CPU/CPU.v" Line 32.  For instance CPU0/lui_mem_wb/, width 1 of formal port out is not equal to width 32 of actual signal lui_wb.
+WARNING: File "E:/verilogtest/RISCV_CPU/CPU.v" Line 35.  For instance CPU0/auipc_mem_wb/, width 1 of formal port in is not equal to width 32 of actual signal auipc_mem.
+WARNING: File "E:/verilogtest/RISCV_CPU/CPU.v" Line 36.  For instance CPU0/auipc_mem_wb/, width 1 of formal port out is not equal to width 32 of actual signal auipc_wb.
+WARNING: File "E:/verilogtest/RISCV_CPU/AXI_BUS.v" Line 450.  For instance uut/CPU0/, width 2 of formal port CPU_AWUSER is not equal to width 1 of actual signal CPU_AWUSER.
+WARNING: File "E:/verilogtest/RISCV_CPU/AXI_BUS.v" Line 466.  For instance uut/CPU0/, width 2 of formal port CPU_WUSER is not equal to width 1 of actual signal CPU_WUSER.
+WARNING: File "E:/verilogtest/RISCV_CPU/AXI_BUS.v" Line 478.  For instance uut/CPU0/, width 2 of formal port CPU_BUSER is not equal to width 1 of actual signal CPU_BUSER.
+WARNING: File "E:/verilogtest/RISCV_CPU/AXI_BUS.v" Line 510.  For instance uut/CPU0/, width 2 of formal port CPU_ARUSER is not equal to width 1 of actual signal CPU_ARUSER.
+WARNING: File "E:/verilogtest/RISCV_CPU/AXI_BUS.v" Line 527.  For instance uut/CPU0/, width 2 of formal port CPU_RUSER is not equal to width 1 of actual signal CPU_RUSER.
+Time resolution is 1 ps
+# onerror resume
+# wave add /
+# run 1000 ns
+Simulator is doing circuit initialization process.
+Finished circuit initialization process.
+# restart
+# run all
+Simulator is doing circuit initialization process.
+Finished circuit initialization process.
+Stopped at time : 1200095 ns : File "E:/verilogtest/RISCV_CPU/myreg.v" Line 20
+# restart
+# run all
+Simulator is doing circuit initialization process.
+Finished circuit initialization process.
+Stopped at time : 1217745 ns : File "E:/verilogtest/RISCV_CPU/myreg.v" Line 16
+# restart
+# restart
+# run all
+Simulator is doing circuit initialization process.
+Finished circuit initialization process.
+Stopped at time : 971505 ns : File "E:/verilogtest/RISCV_CPU/myreg.v" Line 20
+# restart
+# run all
+Simulator is doing circuit initialization process.
+Finished circuit initialization process.
+Stopped at time : 875595 ns : File "E:/verilogtest/RISCV_CPU/NVDLA.v" Line 531
--- a/isim/AXI_BUS_tb1_isim_beh.exe.sim/AXI_BUS_tb1_isim_beh.exe
+++ b/isim/AXI_BUS_tb1_isim_beh.exe.sim/AXI_BUS_tb1_isim_beh.exe
--- a/isim/AXI_BUS_tb1_isim_beh.exe.sim/ISimEngine-DesignHierarchy.dbg
+++ b/isim/AXI_BUS_tb1_isim_beh.exe.sim/ISimEngine-DesignHierarchy.dbg
--- a/isim/AXI_BUS_tb1_isim_beh.exe.sim/isimcrash.log
+++ b/isim/AXI_BUS_tb1_isim_beh.exe.sim/isimcrash.log
--- a/isim/AXI_BUS_tb1_isim_beh.exe.sim/isimkernel.log
+++ b/isim/AXI_BUS_tb1_isim_beh.exe.sim/isimkernel.log
+Command line:
+   AXI_BUS_tb1_isim_beh.exe
+     -simmode  gui
+     -simrunnum  0
+     -socket  59600
+Mon Mar 07 15:43:53 2022
+ Elaboration Time: 0.0625 sec
+ Current Memory Usage: 5166.28 Meg
+ Total Signals          : 816
+ Total Nets             : 3188
+ Total Signal Drivers   : 321
+ Total Blocks           : 63
+ Total Primitive Blocks : 57
+ Total Processes        : 439
+ Total Traceable Variables  : 387
+ Total Scalar Nets and Variables : 18836
+ Total Simulation Time: 5.20313 sec
+ Current Memory Usage: 4694.42 Meg
+Mon Mar 07 15:51:11 2022
--- a/isim/AXI_BUS_tb1_isim_beh.exe.sim/libPortability.dll
+++ b/isim/AXI_BUS_tb1_isim_beh.exe.sim/libPortability.dll
--- a/isim/AXI_BUS_tb1_isim_beh.exe.sim/netId.dat
+++ b/isim/AXI_BUS_tb1_isim_beh.exe.sim/netId.dat
--- a/isim/AXI_BUS_tb1_isim_beh.exe.sim/tmp_save/_1
+++ b/isim/AXI_BUS_tb1_isim_beh.exe.sim/tmp_save/_1
--- a/isim/AXI_BUS_tb1_isim_beh.exe.sim/work/AXI_BUS_tb1_isim_beh.exe_main.c
+++ b/isim/AXI_BUS_tb1_isim_beh.exe.sim/work/AXI_BUS_tb1_isim_beh.exe_main.c
+/**********************************************************************/
+/*   ____  ____                                                       */
+/*  /   /\/   /                                                       */
+/* /___/  \  /                                                        */
+/* \   \   \/                                                       */
+/*  \   \        Copyright (c) 2003-2009 Xilinx, Inc.                */
+/*  /   /          All Right Reserved.                                 */
+/* /---/   /\                                                         */
+/* \   \  /  \                                                      */
+/*  \___\/\___\                                                    */
+/***********************************************************************/
+#include "xsi.h"
+struct XSI_INFO xsi_info;
+int main(int argc, char **argv)
+{
+    xsi_init_design(argc, argv);
+    xsi_register_info(&xsi_info);
+    xsi_register_min_prec_unit(-12);
+    work_m_00000000003576089974_3955322165_init();
+    work_m_00000000000209309465_0536867676_init();
+    work_m_00000000002155642264_2942457252_init();
+    work_m_00000000001152277975_4147288882_init();
+    work_m_00000000001223310956_0593233085_init();
+    work_m_00000000001225860115_0317860448_init();
+    work_m_00000000000765697032_3069169239_init();
+    work_m_00000000004003102621_3385901664_init();
+    work_m_00000000001223310956_2483239782_init();
+    work_m_00000000001223310956_4033871458_init();
+    work_m_00000000001223310956_2788514276_init();
+    work_m_00000000001223310956_3207489701_init();
+    work_m_00000000001223310956_3678580129_init();
+    work_m_00000000002680120478_3210399350_init();
+    work_m_00000000002989708220_3527808377_init();
+    work_m_00000000000457112708_0886308060_init();
+    work_m_00000000000103434339_3508565487_init();
+    work_m_00000000002357191628_0783193758_init();
+    work_m_00000000004207917840_1195057124_init();
+    work_m_00000000002705598459_1458851209_init();
+    work_m_00000000004134447467_2073120511_init();
+    xsi_register_tops("work_m_00000000002705598459_1458851209");
+    xsi_register_tops("work_m_00000000004134447467_2073120511");
+    return xsi_run_simulation(argc, argv);
+}
--- a/isim/AXI_BUS_tb1_isim_beh.exe.sim/work/AXI_BUS_tb1_isim_beh.exe_main.nt64.obj
+++ b/isim/AXI_BUS_tb1_isim_beh.exe.sim/work/AXI_BUS_tb1_isim_beh.exe_main.nt64.obj
--- a/isim/AXI_BUS_tb1_isim_beh.exe.sim/work/m_00000000000103434339_3508565487.c
+++ b/isim/AXI_BUS_tb1_isim_beh.exe.sim/work/m_00000000000103434339_3508565487.c
--- a/isim/AXI_BUS_tb1_isim_beh.exe.sim/work/m_00000000000103434339_3508565487.didat
+++ b/isim/AXI_BUS_tb1_isim_beh.exe.sim/work/m_00000000000103434339_3508565487.didat
--- a/isim/AXI_BUS_tb1_isim_beh.exe.sim/work/m_00000000000103434339_3508565487.nt64.obj
+++ b/isim/AXI_BUS_tb1_isim_beh.exe.sim/work/m_00000000000103434339_3508565487.nt64.obj
--- a/isim/AXI_BUS_tb1_isim_beh.exe.sim/work/m_00000000000209309465_0536867676.c
+++ b/isim/AXI_BUS_tb1_isim_beh.exe.sim/work/m_00000000000209309465_0536867676.c
--- a/isim/AXI_BUS_tb1_isim_beh.exe.sim/work/m_00000000000209309465_0536867676.didat
+++ b/isim/AXI_BUS_tb1_isim_beh.exe.sim/work/m_00000000000209309465_0536867676.didat
--- a/isim/AXI_BUS_tb1_isim_beh.exe.sim/work/m_00000000000209309465_0536867676.nt64.obj
+++ b/isim/AXI_BUS_tb1_isim_beh.exe.sim/work/m_00000000000209309465_0536867676.nt64.obj
--- a/isim/AXI_BUS_tb1_isim_beh.exe.sim/work/m_00000000000457112708_0886308060.c
+++ b/isim/AXI_BUS_tb1_isim_beh.exe.sim/work/m_00000000000457112708_0886308060.c
--- a/isim/AXI_BUS_tb1_isim_beh.exe.sim/work/m_00000000000457112708_0886308060.didat
+++ b/isim/AXI_BUS_tb1_isim_beh.exe.sim/work/m_00000000000457112708_0886308060.didat
--- a/isim/AXI_BUS_tb1_isim_beh.exe.sim/work/m_00000000000457112708_0886308060.nt64.obj
+++ b/isim/AXI_BUS_tb1_isim_beh.exe.sim/work/m_00000000000457112708_0886308060.nt64.obj
--- a/isim/AXI_BUS_tb1_isim_beh.exe.sim/work/m_00000000000765697032_3069169239.c
+++ b/isim/AXI_BUS_tb1_isim_beh.exe.sim/work/m_00000000000765697032_3069169239.c
--- a/isim/AXI_BUS_tb1_isim_beh.exe.sim/work/m_00000000000765697032_3069169239.didat
+++ b/isim/AXI_BUS_tb1_isim_beh.exe.sim/work/m_00000000000765697032_3069169239.didat
--- a/isim/AXI_BUS_tb1_isim_beh.exe.sim/work/m_00000000000765697032_3069169239.nt64.obj
+++ b/isim/AXI_BUS_tb1_isim_beh.exe.sim/work/m_00000000000765697032_3069169239.nt64.obj
--- a/isim/AXI_BUS_tb1_isim_beh.exe.sim/work/m_00000000001152277975_4147288882.c
+++ b/isim/AXI_BUS_tb1_isim_beh.exe.sim/work/m_00000000001152277975_4147288882.c
--- a/isim/AXI_BUS_tb1_isim_beh.exe.sim/work/m_00000000001152277975_4147288882.didat
+++ b/isim/AXI_BUS_tb1_isim_beh.exe.sim/work/m_00000000001152277975_4147288882.didat
--- a/isim/AXI_BUS_tb1_isim_beh.exe.sim/work/m_00000000001152277975_4147288882.nt64.obj
+++ b/isim/AXI_BUS_tb1_isim_beh.exe.sim/work/m_00000000001152277975_4147288882.nt64.obj
--- a/isim/AXI_BUS_tb1_isim_beh.exe.sim/work/m_00000000001223310956_0593233085.c
+++ b/isim/AXI_BUS_tb1_isim_beh.exe.sim/work/m_00000000001223310956_0593233085.c
--- a/isim/AXI_BUS_tb1_isim_beh.exe.sim/work/m_00000000001223310956_0593233085.didat
+++ b/isim/AXI_BUS_tb1_isim_beh.exe.sim/work/m_00000000001223310956_0593233085.didat
--- a/isim/AXI_BUS_tb1_isim_beh.exe.sim/work/m_00000000001223310956_0593233085.nt64.obj
+++ b/isim/AXI_BUS_tb1_isim_beh.exe.sim/work/m_00000000001223310956_0593233085.nt64.obj
--- a/isim/AXI_BUS_tb1_isim_beh.exe.sim/work/m_00000000001223310956_2483239782.c
+++ b/isim/AXI_BUS_tb1_isim_beh.exe.sim/work/m_00000000001223310956_2483239782.c
--- a/isim/AXI_BUS_tb1_isim_beh.exe.sim/work/m_00000000001223310956_2483239782.didat
+++ b/isim/AXI_BUS_tb1_isim_beh.exe.sim/work/m_00000000001223310956_2483239782.didat
--- a/isim/AXI_BUS_tb1_isim_beh.exe.sim/work/m_00000000001223310956_2483239782.nt64.obj
+++ b/isim/AXI_BUS_tb1_isim_beh.exe.sim/work/m_00000000001223310956_2483239782.nt64.obj
--- a/isim/AXI_BUS_tb1_isim_beh.exe.sim/work/m_00000000001223310956_2788514276.c
+++ b/isim/AXI_BUS_tb1_isim_beh.exe.sim/work/m_00000000001223310956_2788514276.c
--- a/isim/AXI_BUS_tb1_isim_beh.exe.sim/work/m_00000000001223310956_2788514276.didat
+++ b/isim/AXI_BUS_tb1_isim_beh.exe.sim/work/m_00000000001223310956_2788514276.didat
--- a/isim/AXI_BUS_tb1_isim_beh.exe.sim/work/m_00000000001223310956_2788514276.nt64.obj
+++ b/isim/AXI_BUS_tb1_isim_beh.exe.sim/work/m_00000000001223310956_2788514276.nt64.obj
--- a/isim/AXI_BUS_tb1_isim_beh.exe.sim/work/m_00000000001223310956_3207489701.c
+++ b/isim/AXI_BUS_tb1_isim_beh.exe.sim/work/m_00000000001223310956_3207489701.c
--- a/isim/AXI_BUS_tb1_isim_beh.exe.sim/work/m_00000000001223310956_3207489701.didat
+++ b/isim/AXI_BUS_tb1_isim_beh.exe.sim/work/m_00000000001223310956_3207489701.didat
--- a/isim/AXI_BUS_tb1_isim_beh.exe.sim/work/m_00000000001223310956_3207489701.nt64.obj
+++ b/isim/AXI_BUS_tb1_isim_beh.exe.sim/work/m_00000000001223310956_3207489701.nt64.obj
--- a/isim/AXI_BUS_tb1_isim_beh.exe.sim/work/m_00000000001223310956_3678580129.c
+++ b/isim/AXI_BUS_tb1_isim_beh.exe.sim/work/m_00000000001223310956_3678580129.c
--- a/isim/AXI_BUS_tb1_isim_beh.exe.sim/work/m_00000000001223310956_3678580129.didat
+++ b/isim/AXI_BUS_tb1_isim_beh.exe.sim/work/m_00000000001223310956_3678580129.didat
--- a/isim/AXI_BUS_tb1_isim_beh.exe.sim/work/m_00000000001223310956_3678580129.nt64.obj
+++ b/isim/AXI_BUS_tb1_isim_beh.exe.sim/work/m_00000000001223310956_3678580129.nt64.obj
--- a/isim/AXI_BUS_tb1_isim_beh.exe.sim/work/m_00000000001223310956_4033871458.c
+++ b/isim/AXI_BUS_tb1_isim_beh.exe.sim/work/m_00000000001223310956_4033871458.c
--- a/isim/AXI_BUS_tb1_isim_beh.exe.sim/work/m_00000000001223310956_4033871458.didat
+++ b/isim/AXI_BUS_tb1_isim_beh.exe.sim/work/m_00000000001223310956_4033871458.didat
--- a/isim/AXI_BUS_tb1_isim_beh.exe.sim/work/m_00000000001223310956_4033871458.nt64.obj
+++ b/isim/AXI_BUS_tb1_isim_beh.exe.sim/work/m_00000000001223310956_4033871458.nt64.obj
--- a/isim/AXI_BUS_tb1_isim_beh.exe.sim/work/m_00000000001225860115_0317860448.c
+++ b/isim/AXI_BUS_tb1_isim_beh.exe.sim/work/m_00000000001225860115_0317860448.c
--- a/isim/AXI_BUS_tb1_isim_beh.exe.sim/work/m_00000000001225860115_0317860448.didat
+++ b/isim/AXI_BUS_tb1_isim_beh.exe.sim/work/m_00000000001225860115_0317860448.didat
--- a/isim/AXI_BUS_tb1_isim_beh.exe.sim/work/m_00000000001225860115_0317860448.nt64.obj
+++ b/isim/AXI_BUS_tb1_isim_beh.exe.sim/work/m_00000000001225860115_0317860448.nt64.obj
--- a/isim/AXI_BUS_tb1_isim_beh.exe.sim/work/m_00000000002155642264_2942457252.c
+++ b/isim/AXI_BUS_tb1_isim_beh.exe.sim/work/m_00000000002155642264_2942457252.c
--- a/isim/AXI_BUS_tb1_isim_beh.exe.sim/work/m_00000000002155642264_2942457252.didat
+++ b/isim/AXI_BUS_tb1_isim_beh.exe.sim/work/m_00000000002155642264_2942457252.didat
--- a/isim/AXI_BUS_tb1_isim_beh.exe.sim/work/m_00000000002155642264_2942457252.nt64.obj
+++ b/isim/AXI_BUS_tb1_isim_beh.exe.sim/work/m_00000000002155642264_2942457252.nt64.obj
--- a/isim/AXI_BUS_tb1_isim_beh.exe.sim/work/m_00000000002357191628_0783193758.c
+++ b/isim/AXI_BUS_tb1_isim_beh.exe.sim/work/m_00000000002357191628_0783193758.c
--- a/isim/AXI_BUS_tb1_isim_beh.exe.sim/work/m_00000000002357191628_0783193758.didat
+++ b/isim/AXI_BUS_tb1_isim_beh.exe.sim/work/m_00000000002357191628_0783193758.didat
--- a/isim/AXI_BUS_tb1_isim_beh.exe.sim/work/m_00000000002357191628_0783193758.nt64.obj
+++ b/isim/AXI_BUS_tb1_isim_beh.exe.sim/work/m_00000000002357191628_0783193758.nt64.obj
--- a/isim/AXI_BUS_tb1_isim_beh.exe.sim/work/m_00000000002680120478_3210399350.c
+++ b/isim/AXI_BUS_tb1_isim_beh.exe.sim/work/m_00000000002680120478_3210399350.c
--- a/isim/AXI_BUS_tb1_isim_beh.exe.sim/work/m_00000000002680120478_3210399350.didat
+++ b/isim/AXI_BUS_tb1_isim_beh.exe.sim/work/m_00000000002680120478_3210399350.didat
--- a/isim/AXI_BUS_tb1_isim_beh.exe.sim/work/m_00000000002680120478_3210399350.nt64.obj
+++ b/isim/AXI_BUS_tb1_isim_beh.exe.sim/work/m_00000000002680120478_3210399350.nt64.obj
--- a/isim/AXI_BUS_tb1_isim_beh.exe.sim/work/m_00000000002705598459_1458851209.c
+++ b/isim/AXI_BUS_tb1_isim_beh.exe.sim/work/m_00000000002705598459_1458851209.c
--- a/isim/AXI_BUS_tb1_isim_beh.exe.sim/work/m_00000000002705598459_1458851209.didat
+++ b/isim/AXI_BUS_tb1_isim_beh.exe.sim/work/m_00000000002705598459_1458851209.didat
--- a/isim/AXI_BUS_tb1_isim_beh.exe.sim/work/m_00000000002705598459_1458851209.nt64.obj
+++ b/isim/AXI_BUS_tb1_isim_beh.exe.sim/work/m_00000000002705598459_1458851209.nt64.obj
--- a/isim/AXI_BUS_tb1_isim_beh.exe.sim/work/m_00000000002989708220_3527808377.c
+++ b/isim/AXI_BUS_tb1_isim_beh.exe.sim/work/m_00000000002989708220_3527808377.c
--- a/isim/AXI_BUS_tb1_isim_beh.exe.sim/work/m_00000000002989708220_3527808377.didat
+++ b/isim/AXI_BUS_tb1_isim_beh.exe.sim/work/m_00000000002989708220_3527808377.didat
--- a/isim/AXI_BUS_tb1_isim_beh.exe.sim/work/m_00000000002989708220_3527808377.nt64.obj
+++ b/isim/AXI_BUS_tb1_isim_beh.exe.sim/work/m_00000000002989708220_3527808377.nt64.obj
--- a/isim/AXI_BUS_tb1_isim_beh.exe.sim/work/m_00000000003576089974_3955322165.c
+++ b/isim/AXI_BUS_tb1_isim_beh.exe.sim/work/m_00000000003576089974_3955322165.c
--- a/isim/AXI_BUS_tb1_isim_beh.exe.sim/work/m_00000000003576089974_3955322165.didat
+++ b/isim/AXI_BUS_tb1_isim_beh.exe.sim/work/m_00000000003576089974_3955322165.didat
--- a/isim/AXI_BUS_tb1_isim_beh.exe.sim/work/m_00000000003576089974_3955322165.nt64.obj
+++ b/isim/AXI_BUS_tb1_isim_beh.exe.sim/work/m_00000000003576089974_3955322165.nt64.obj
--- a/isim/AXI_BUS_tb1_isim_beh.exe.sim/work/m_00000000004003102621_3385901664.c
+++ b/isim/AXI_BUS_tb1_isim_beh.exe.sim/work/m_00000000004003102621_3385901664.c
--- a/isim/AXI_BUS_tb1_isim_beh.exe.sim/work/m_00000000004003102621_3385901664.didat
+++ b/isim/AXI_BUS_tb1_isim_beh.exe.sim/work/m_00000000004003102621_3385901664.didat
--- a/isim/AXI_BUS_tb1_isim_beh.exe.sim/work/m_00000000004003102621_3385901664.nt64.obj
+++ b/isim/AXI_BUS_tb1_isim_beh.exe.sim/work/m_00000000004003102621_3385901664.nt64.obj
--- a/isim/AXI_BUS_tb1_isim_beh.exe.sim/work/m_00000000004134447467_2073120511.c
+++ b/isim/AXI_BUS_tb1_isim_beh.exe.sim/work/m_00000000004134447467_2073120511.c
--- a/isim/AXI_BUS_tb1_isim_beh.exe.sim/work/m_00000000004134447467_2073120511.didat
+++ b/isim/AXI_BUS_tb1_isim_beh.exe.sim/work/m_00000000004134447467_2073120511.didat
--- a/isim/AXI_BUS_tb1_isim_beh.exe.sim/work/m_00000000004134447467_2073120511.nt64.obj
+++ b/isim/AXI_BUS_tb1_isim_beh.exe.sim/work/m_00000000004134447467_2073120511.nt64.obj
--- a/isim/AXI_BUS_tb1_isim_beh.exe.sim/work/m_00000000004207917840_1195057124.c
+++ b/isim/AXI_BUS_tb1_isim_beh.exe.sim/work/m_00000000004207917840_1195057124.c
--- a/isim/AXI_BUS_tb1_isim_beh.exe.sim/work/m_00000000004207917840_1195057124.didat
+++ b/isim/AXI_BUS_tb1_isim_beh.exe.sim/work/m_00000000004207917840_1195057124.didat
--- a/isim/AXI_BUS_tb1_isim_beh.exe.sim/work/m_00000000004207917840_1195057124.nt64.obj
+++ b/isim/AXI_BUS_tb1_isim_beh.exe.sim/work/m_00000000004207917840_1195057124.nt64.obj
--- a/isim/CPU_CONTROL_isim_beh.exe.sim/CPU_CONTROL_isim_beh.exe
+++ b/isim/CPU_CONTROL_isim_beh.exe.sim/CPU_CONTROL_isim_beh.exe
--- a/isim/CPU_CONTROL_isim_beh.exe.sim/ISimEngine-DesignHierarchy.dbg
+++ b/isim/CPU_CONTROL_isim_beh.exe.sim/ISimEngine-DesignHierarchy.dbg
--- a/isim/CPU_CONTROL_isim_beh.exe.sim/isimcrash.log
+++ b/isim/CPU_CONTROL_isim_beh.exe.sim/isimcrash.log
--- a/isim/CPU_CONTROL_isim_beh.exe.sim/isimkernel.log
+++ b/isim/CPU_CONTROL_isim_beh.exe.sim/isimkernel.log
--- a/isim/CPU_CONTROL_isim_beh.exe.sim/libPortability.dll
+++ b/isim/CPU_CONTROL_isim_beh.exe.sim/libPortability.dll
--- a/isim/CPU_CONTROL_isim_beh.exe.sim/netId.dat
+++ b/isim/CPU_CONTROL_isim_beh.exe.sim/netId.dat
--- a/isim/CPU_CONTROL_isim_beh.exe.sim/tmp_save/_1
+++ b/isim/CPU_CONTROL_isim_beh.exe.sim/tmp_save/_1
--- a/isim/CPU_CONTROL_isim_beh.exe.sim/work/CPU_CONTROL_isim_beh.exe_main.c
+++ b/isim/CPU_CONTROL_isim_beh.exe.sim/work/CPU_CONTROL_isim_beh.exe_main.c
--- a/isim/CPU_CONTROL_isim_beh.exe.sim/work/CPU_CONTROL_isim_beh.exe_main.nt64.obj
+++ b/isim/CPU_CONTROL_isim_beh.exe.sim/work/CPU_CONTROL_isim_beh.exe_main.nt64.obj
--- a/isim/CPU_CONTROL_isim_beh.exe.sim/work/m_00000000000103434339_3508565487.c
+++ b/isim/CPU_CONTROL_isim_beh.exe.sim/work/m_00000000000103434339_3508565487.c
--- a/isim/CPU_CONTROL_isim_beh.exe.sim/work/m_00000000000103434339_3508565487.didat
+++ b/isim/CPU_CONTROL_isim_beh.exe.sim/work/m_00000000000103434339_3508565487.didat
--- a/isim/CPU_CONTROL_isim_beh.exe.sim/work/m_00000000000103434339_3508565487.nt64.obj
+++ b/isim/CPU_CONTROL_isim_beh.exe.sim/work/m_00000000000103434339_3508565487.nt64.obj
--- a/isim/CPU_CONTROL_isim_beh.exe.sim/work/m_00000000000457112708_0886308060.c
+++ b/isim/CPU_CONTROL_isim_beh.exe.sim/work/m_00000000000457112708_0886308060.c
--- a/isim/CPU_CONTROL_isim_beh.exe.sim/work/m_00000000000457112708_0886308060.didat
+++ b/isim/CPU_CONTROL_isim_beh.exe.sim/work/m_00000000000457112708_0886308060.didat
--- a/isim/CPU_CONTROL_isim_beh.exe.sim/work/m_00000000000457112708_0886308060.nt64.obj
+++ b/isim/CPU_CONTROL_isim_beh.exe.sim/work/m_00000000000457112708_0886308060.nt64.obj
--- a/isim/CPU_CONTROL_isim_beh.exe.sim/work/m_00000000000765697032_3069169239.c
+++ b/isim/CPU_CONTROL_isim_beh.exe.sim/work/m_00000000000765697032_3069169239.c
--- a/isim/CPU_CONTROL_isim_beh.exe.sim/work/m_00000000000765697032_3069169239.didat
+++ b/isim/CPU_CONTROL_isim_beh.exe.sim/work/m_00000000000765697032_3069169239.didat
--- a/isim/CPU_CONTROL_isim_beh.exe.sim/work/m_00000000000765697032_3069169239.nt64.obj
+++ b/isim/CPU_CONTROL_isim_beh.exe.sim/work/m_00000000000765697032_3069169239.nt64.obj
--- a/isim/CPU_CONTROL_isim_beh.exe.sim/work/m_00000000001223310956_0593233085.c
+++ b/isim/CPU_CONTROL_isim_beh.exe.sim/work/m_00000000001223310956_0593233085.c
--- a/isim/CPU_CONTROL_isim_beh.exe.sim/work/m_00000000001223310956_0593233085.didat
+++ b/isim/CPU_CONTROL_isim_beh.exe.sim/work/m_00000000001223310956_0593233085.didat
--- a/isim/CPU_CONTROL_isim_beh.exe.sim/work/m_00000000001223310956_0593233085.nt64.obj
+++ b/isim/CPU_CONTROL_isim_beh.exe.sim/work/m_00000000001223310956_0593233085.nt64.obj
--- a/isim/CPU_CONTROL_isim_beh.exe.sim/work/m_00000000001223310956_2483239782.c
+++ b/isim/CPU_CONTROL_isim_beh.exe.sim/work/m_00000000001223310956_2483239782.c
--- a/isim/CPU_CONTROL_isim_beh.exe.sim/work/m_00000000001223310956_2483239782.didat
+++ b/isim/CPU_CONTROL_isim_beh.exe.sim/work/m_00000000001223310956_2483239782.didat
--- a/isim/CPU_CONTROL_isim_beh.exe.sim/work/m_00000000001223310956_2483239782.nt64.obj
+++ b/isim/CPU_CONTROL_isim_beh.exe.sim/work/m_00000000001223310956_2483239782.nt64.obj
--- a/isim/CPU_CONTROL_isim_beh.exe.sim/work/m_00000000001223310956_2788514276.c
+++ b/isim/CPU_CONTROL_isim_beh.exe.sim/work/m_00000000001223310956_2788514276.c
--- a/isim/CPU_CONTROL_isim_beh.exe.sim/work/m_00000000001223310956_2788514276.didat
+++ b/isim/CPU_CONTROL_isim_beh.exe.sim/work/m_00000000001223310956_2788514276.didat
--- a/isim/CPU_CONTROL_isim_beh.exe.sim/work/m_00000000001223310956_2788514276.nt64.obj
+++ b/isim/CPU_CONTROL_isim_beh.exe.sim/work/m_00000000001223310956_2788514276.nt64.obj
--- a/isim/CPU_CONTROL_isim_beh.exe.sim/work/m_00000000001223310956_3207489701.c
+++ b/isim/CPU_CONTROL_isim_beh.exe.sim/work/m_00000000001223310956_3207489701.c
--- a/isim/CPU_CONTROL_isim_beh.exe.sim/work/m_00000000001223310956_3207489701.didat
+++ b/isim/CPU_CONTROL_isim_beh.exe.sim/work/m_00000000001223310956_3207489701.didat
--- a/isim/CPU_CONTROL_isim_beh.exe.sim/work/m_00000000001223310956_3207489701.nt64.obj
+++ b/isim/CPU_CONTROL_isim_beh.exe.sim/work/m_00000000001223310956_3207489701.nt64.obj
--- a/isim/CPU_CONTROL_isim_beh.exe.sim/work/m_00000000001223310956_3678580129.c
+++ b/isim/CPU_CONTROL_isim_beh.exe.sim/work/m_00000000001223310956_3678580129.c
--- a/isim/CPU_CONTROL_isim_beh.exe.sim/work/m_00000000001223310956_3678580129.didat
+++ b/isim/CPU_CONTROL_isim_beh.exe.sim/work/m_00000000001223310956_3678580129.didat
--- a/isim/CPU_CONTROL_isim_beh.exe.sim/work/m_00000000001223310956_3678580129.nt64.obj
+++ b/isim/CPU_CONTROL_isim_beh.exe.sim/work/m_00000000001223310956_3678580129.nt64.obj
--- a/isim/CPU_CONTROL_isim_beh.exe.sim/work/m_00000000001223310956_4033871458.c
+++ b/isim/CPU_CONTROL_isim_beh.exe.sim/work/m_00000000001223310956_4033871458.c
--- a/isim/CPU_CONTROL_isim_beh.exe.sim/work/m_00000000001223310956_4033871458.didat
+++ b/isim/CPU_CONTROL_isim_beh.exe.sim/work/m_00000000001223310956_4033871458.didat
--- a/isim/CPU_CONTROL_isim_beh.exe.sim/work/m_00000000001223310956_4033871458.nt64.obj
+++ b/isim/CPU_CONTROL_isim_beh.exe.sim/work/m_00000000001223310956_4033871458.nt64.obj
--- a/isim/CPU_CONTROL_isim_beh.exe.sim/work/m_00000000001225860115_0317860448.c
+++ b/isim/CPU_CONTROL_isim_beh.exe.sim/work/m_00000000001225860115_0317860448.c
--- a/isim/CPU_CONTROL_isim_beh.exe.sim/work/m_00000000001225860115_0317860448.didat
+++ b/isim/CPU_CONTROL_isim_beh.exe.sim/work/m_00000000001225860115_0317860448.didat
--- a/isim/CPU_CONTROL_isim_beh.exe.sim/work/m_00000000001225860115_0317860448.nt64.obj
+++ b/isim/CPU_CONTROL_isim_beh.exe.sim/work/m_00000000001225860115_0317860448.nt64.obj
--- a/isim/CPU_CONTROL_isim_beh.exe.sim/work/m_00000000002357191628_0783193758.c
+++ b/isim/CPU_CONTROL_isim_beh.exe.sim/work/m_00000000002357191628_0783193758.c
--- a/isim/CPU_CONTROL_isim_beh.exe.sim/work/m_00000000002357191628_0783193758.didat
+++ b/isim/CPU_CONTROL_isim_beh.exe.sim/work/m_00000000002357191628_0783193758.didat
--- a/isim/CPU_CONTROL_isim_beh.exe.sim/work/m_00000000002357191628_0783193758.nt64.obj
+++ b/isim/CPU_CONTROL_isim_beh.exe.sim/work/m_00000000002357191628_0783193758.nt64.obj
--- a/isim/CPU_CONTROL_isim_beh.exe.sim/work/m_00000000002680120478_3210399350.c
+++ b/isim/CPU_CONTROL_isim_beh.exe.sim/work/m_00000000002680120478_3210399350.c
--- a/isim/CPU_CONTROL_isim_beh.exe.sim/work/m_00000000002680120478_3210399350.didat
+++ b/isim/CPU_CONTROL_isim_beh.exe.sim/work/m_00000000002680120478_3210399350.didat
--- a/isim/CPU_CONTROL_isim_beh.exe.sim/work/m_00000000002680120478_3210399350.nt64.obj
+++ b/isim/CPU_CONTROL_isim_beh.exe.sim/work/m_00000000002680120478_3210399350.nt64.obj
--- a/isim/CPU_CONTROL_isim_beh.exe.sim/work/m_00000000002989708220_3527808377.c
+++ b/isim/CPU_CONTROL_isim_beh.exe.sim/work/m_00000000002989708220_3527808377.c
--- a/isim/CPU_CONTROL_isim_beh.exe.sim/work/m_00000000002989708220_3527808377.didat
+++ b/isim/CPU_CONTROL_isim_beh.exe.sim/work/m_00000000002989708220_3527808377.didat
--- a/isim/CPU_CONTROL_isim_beh.exe.sim/work/m_00000000002989708220_3527808377.nt64.obj
+++ b/isim/CPU_CONTROL_isim_beh.exe.sim/work/m_00000000002989708220_3527808377.nt64.obj
--- a/isim/CPU_CONTROL_isim_beh.exe.sim/work/m_00000000004003102621_3385901664.c
+++ b/isim/CPU_CONTROL_isim_beh.exe.sim/work/m_00000000004003102621_3385901664.c
--- a/isim/CPU_CONTROL_isim_beh.exe.sim/work/m_00000000004003102621_3385901664.didat
+++ b/isim/CPU_CONTROL_isim_beh.exe.sim/work/m_00000000004003102621_3385901664.didat
--- a/isim/CPU_CONTROL_isim_beh.exe.sim/work/m_00000000004003102621_3385901664.nt64.obj
+++ b/isim/CPU_CONTROL_isim_beh.exe.sim/work/m_00000000004003102621_3385901664.nt64.obj
--- a/isim/CPU_CONTROL_isim_beh.exe.sim/work/m_00000000004134447467_2073120511.c
+++ b/isim/CPU_CONTROL_isim_beh.exe.sim/work/m_00000000004134447467_2073120511.c
--- a/isim/CPU_CONTROL_isim_beh.exe.sim/work/m_00000000004134447467_2073120511.didat
+++ b/isim/CPU_CONTROL_isim_beh.exe.sim/work/m_00000000004134447467_2073120511.didat
--- a/isim/CPU_CONTROL_isim_beh.exe.sim/work/m_00000000004134447467_2073120511.nt64.obj
+++ b/isim/CPU_CONTROL_isim_beh.exe.sim/work/m_00000000004134447467_2073120511.nt64.obj
--- a/isim/isim_usage_statistics.html
+++ b/isim/isim_usage_statistics.html
--- a/isim/pn_info
+++ b/isim/pn_info
--- a/isim/temp/@a@l@u.sdb
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--- a/isim/temp/@a@x@i_@b@u@s_tb1.sdb
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--- a/isim/temp/@c@p@u_@c@o@n@t@r@o@l.sdb
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--- a/isim/temp/@n@v@d@l@a.sdb
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--- a/isim/temp/@n@v@d@l@a_@c@o@n@t@r@o@l.sdb
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--- a/isim/temp/@r@a@m.sdb
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--- a/isim/temp/@r@a@m_@c@o@n@t@r@o@l.sdb
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--- a/isim/temp/@r@o@m.sdb
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--- a/isim/temp/@registers.sdb
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--- a/isim/temp/decoder.sdb
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--- a/isim/temp/forward.sdb
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--- a/isim/temp/glbl.sdb
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--- a/isim/temp/mux4.sdb
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--- a/isim/temp/myreg.sdb
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--- a/isim/work/@a@l@u.sdb
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--- a/isim/work/@a@x@i_@b@u@s.sdb
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--- a/isim/work/@a@x@i_@b@u@s_tb1.sdb
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--- a/isim/work/@c@p@u.sdb
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--- a/isim/work/@c@p@u_@c@o@n@t@r@o@l.sdb
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--- a/isim/work/@n@v@d@l@a.sdb
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--- a/isim/work/@n@v@d@l@a_@c@o@n@t@r@o@l.sdb
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--- a/isim/work/@r@a@m.sdb
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--- a/isim/work/@r@a@m_@c@o@n@t@r@o@l.sdb
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--- a/isim/work/@r@o@m.sdb
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--- a/isim/work/@registers.sdb
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--- a/isim/work/decoder.sdb
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--- a/isim/work/forward.sdb
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--- a/isim/work/glbl.sdb
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--- a/isim/work/mux4.sdb
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--- a/isim/work/myreg.sdb
+++ b/isim/work/myreg.sdb
--- a/mux4.v
+++ b/mux4.v
--- a/myreg.v
+++ b/myreg.v
--- a/myreg_isim_beh.exe
+++ b/myreg_isim_beh.exe
--- a/myreg_stx_beh.prj
+++ b/myreg_stx_beh.prj
--- a/webtalk_pn.xml
+++ b/webtalk_pn.xml
--- a/xilinxsim.ini
+++ b/xilinxsim.ini
--- a/xst/work/hdllib.ref
+++ b/xst/work/hdllib.ref
--- a/xst/work/vlg02/decoder.bin
+++ b/xst/work/vlg02/decoder.bin
--- a/xst/work/vlg14/_r_a_m.bin
+++ b/xst/work/vlg14/_r_a_m.bin
--- a/xst/work/vlg15/forward.bin
+++ b/xst/work/vlg15/forward.bin
--- a/xst/work/vlg20/_registers.bin
+++ b/xst/work/vlg20/_registers.bin
--- a/xst/work/vlg2A/_a_l_u.bin
+++ b/xst/work/vlg2A/_a_l_u.bin
--- a/xst/work/vlg32/mux4.bin
+++ b/xst/work/vlg32/mux4.bin
--- a/xst/work/vlg34/myreg.bin
+++ b/xst/work/vlg34/myreg.bin
--- a/xst/work/vlg4B/dependence__detect.bin
+++ b/xst/work/vlg4B/dependence__detect.bin
--- a/xst/work/vlg5A/_r_o_m.bin
+++ b/xst/work/vlg5A/_r_o_m.bin
--- a/xst/work/vlg70/_c_p_u.bin
+++ b/xst/work/vlg70/_c_p_u.bin