execute.py

src/aag_to_cpp/execute.py

+from generate_top import *
+verilog_top("c432")

src/aag_to_cpp/generate_top.py

@@ -4,7 +4,7 @@ def verilog_top(filename,  num_lines=10):
     integers = []
     
     try:
-        with open(filename+".v", 'r') as file:
+        with open("input_verilog/"+filename+".v", 'r') as file:
             for i in range(num_lines):
                 line = file.readline()
                 if not line:  # 如果文件行数不足，提前结束
@@ -63,7 +63,7 @@ def verilog_top(filename,  num_lines=10):
     try:
         with open("yosys_bits/yosys.ys", 'w') as file:
             for bit_index in range (output_bit_width):
-                file.write("read_verilog %s.v;\n"%filename)
+                file.write("read_verilog input_verilog/%s.v;\n"%filename)
                 file.write("read_verilog verilog_bits/%s_o%d.v;\n"%(filename,bit_index))
                 file.write("hierarchy -top %s_o%d;\n"%(filename,bit_index))
                 file.write("flatten;\n")
@@ -121,7 +121,7 @@ def verilog_top(filename,  num_lines=10):
 
 
 
-    output_file = filename+".h"
+    output_file = "output_cpp/"+filename+".h"
     try:
         with open(output_file, 'w') as out_file:
             out_file.write("#ifndef IO_GENERATOR_OUTER_H\n")
@@ -173,7 +173,7 @@ def verilog_top(filename,  num_lines=10):
     except Exception as e:
         print(f"写入文件 {output_file} 时出错: {e}")
 
-    output_file = filename+"_vec.h"
+    output_file = "output_cpp/"+filename+"_vec.h"
     try:
         with open(output_file, 'w') as out_file:
             for i in range(output_bit_width):  
@@ -224,4 +224,3 @@ def verilog_top(filename,  num_lines=10):
 
     return integers	
 
-verilog_top("c432")

src/aag_to_cpp/yosys_bits/yosys.ys

-read_verilog c432.v;
+read_verilog input_verilog/c432.v;
 read_verilog verilog_bits/c432_o0.v;
 hierarchy -top c432_o0;
 flatten;
@@ -6,7 +6,7 @@ synth;
 aigmap;
 write_aiger -symbols -ascii aag_bits/c432_o0.aag
 
-read_verilog c432.v;
+read_verilog input_verilog/c432.v;
 read_verilog verilog_bits/c432_o1.v;
 hierarchy -top c432_o1;
 flatten;
@@ -14,7 +14,7 @@ synth;
 aigmap;
 write_aiger -symbols -ascii aag_bits/c432_o1.aag
 
-read_verilog c432.v;
+read_verilog input_verilog/c432.v;
 read_verilog verilog_bits/c432_o2.v;
 hierarchy -top c432_o2;
 flatten;
@@ -22,7 +22,7 @@ synth;
 aigmap;
 write_aiger -symbols -ascii aag_bits/c432_o2.aag
 
-read_verilog c432.v;
+read_verilog input_verilog/c432.v;
 read_verilog verilog_bits/c432_o3.v;
 hierarchy -top c432_o3;
 flatten;
@@ -30,7 +30,7 @@ synth;
 aigmap;
 write_aiger -symbols -ascii aag_bits/c432_o3.aag
 
-read_verilog c432.v;
+read_verilog input_verilog/c432.v;
 read_verilog verilog_bits/c432_o4.v;
 hierarchy -top c432_o4;
 flatten;
@@ -38,7 +38,7 @@ synth;
 aigmap;
 write_aiger -symbols -ascii aag_bits/c432_o4.aag
 
-read_verilog c432.v;
+read_verilog input_verilog/c432.v;
 read_verilog verilog_bits/c432_o5.v;
 hierarchy -top c432_o5;
 flatten;
@@ -46,7 +46,7 @@ synth;
 aigmap;
 write_aiger -symbols -ascii aag_bits/c432_o5.aag
 
-read_verilog c432.v;
+read_verilog input_verilog/c432.v;
 read_verilog verilog_bits/c432_o6.v;
 hierarchy -top c432_o6;
 flatten;

src/aag_to_cpp/zstart.sh

-python generate_top.py
+python execute.py
 yosys yosys_bits/yosys.ys
 python  aag_to_cpp_bits.py
 sh vec_bits/write_vec.sh
-python generate_top.py
+python execute.py