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ZhangXiaoyun
verl
Commits
b06b4eb7
Commit
b06b4eb7
authored
Sep 10, 2025
by
root
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fix yosys script issues in PPA estimation
parent
399e9bb9
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6 changed files
with
17 additions
and
17 deletions
+17
-17
eda_tools/eda_tools/utils.py
+4
-2
eda_tools/scripts/simple_yosys.ys
+1
-3
eda_tools/scripts/sta.ys
+1
-1
eda_tools/scripts/test.ys
+2
-0
eda_tools/scripts/yosys.ys
+7
-9
examples/data_preprocess/codev.py
+2
-2
No files found.
eda_tools/eda_tools/utils.py
View file @
b06b4eb7
...
...
@@ -816,13 +816,15 @@ Example of expected response format:
os
.
makedirs
(
report_dir
,
exist_ok
=
True
)
power_path
=
os
.
path
.
join
(
report_dir
,
"power.rpt"
)
unconstrained_path
=
os
.
path
.
join
(
report_dir
,
"unconstrained.rpt"
)
# yosys_script = yosys_script.replace("/yosys.ys", "/simple_yosys.ys")
with
open
(
yosys_script
,
"r"
)
as
f
:
ys_template
=
f
.
read
()
ys_script
=
ys_template
.
format
(
file_path
=
file_path
,
top_module
=
top_module
,
t_ech
=
t_ech
t_ech
=
t_ech
,
base_dir
=
base_dir
)
try
:
result
=
subprocess
.
run
(
...
...
@@ -891,7 +893,7 @@ Example of expected response format:
clock_constraint
=
""
if
clk
is
not
None
:
clock_constraint
=
f
'create_clock -name {clk} -period 10 [get_ports {clk}]
\n
'
sta_script
=
sta_template
.
replace
(
"{t_ech}"
,
t_ech
)
.
replace
(
"{top_module}"
,
top_module
)
.
replace
(
"{file_path}"
,
file_path
)
.
replace
(
"{file_id}"
,
file_id
)
sta_script
=
sta_template
.
replace
(
"{t_ech}"
,
t_ech
)
.
replace
(
"{top_module}"
,
top_module
)
.
replace
(
"{file_path}"
,
file_path
)
.
replace
(
"{file_id}"
,
file_id
)
.
replace
(
"{base_dir}"
,
base_dir
)
if
clock_constraint
:
sta_script
=
sta_script
.
replace
(
f
'link_design $sc_design'
,
...
...
eda_tools/scripts/simple_yosys.ys
View file @
b06b4eb7
set base_dir [file dirname [file dirname [info script]]]
# =============================================================================
# Read Design and Libraries
# =============================================================================
...
...
@@ -18,7 +16,7 @@ synth -top {top_module} -run fine:check # Refine and check design
# ABC Optimization and Mapping
# =============================================================================
abc -fast -liberty {t_ech} # Fast logic optimization
abc -constr
[file join $base_dir files_needed/sc_abc.constraints]
\ # Constrained ABC mapping
abc -constr
{base_dir}/files_needed/sc_abc.constraints
\ # Constrained ABC mapping
-liberty {t_ech} \
-dont_use OAI211_X1 \
-dont_use CLKBUF_X1 \
...
...
eda_tools/scripts/sta.ys
View file @
b06b4eb7
...
...
@@ -5,7 +5,7 @@ set sc_design {top_module}
set sc_scenarios "worst"
set sc_delaymodel "nldm"
set sc_sdc
"files_needed/sc_constraints.sdc"
set sc_sdc
{base_dir}/files_needed/sc_constraints.sdc
#**************************************************************
# Load Technology Libraries
...
...
eda_tools/scripts/test.ys
0 → 100644
View file @
b06b4eb7
set base_dir [info script]
\ No newline at end of file
eda_tools/scripts/yosys.ys
View file @
b06b4eb7
set base_dir [file dirname [file dirname [info script]]]
# =============================================================================
# Read source RTL and libraries
# =============================================================================
...
...
@@ -14,7 +12,7 @@ read_liberty -setattr liberty_cell -lib {t_ech}
hierarchy -top {top_module}
tribuf
scratchpad -set flatten.separator /
synth -flatten -extra-map
[file join $base_dir files_needed/lcu_kogge_stone.v]
-top {top_module} -run begin:fine
synth -flatten -extra-map
{base_dir}/files_needed/lcu_kogge_stone.v
-top {top_module} -run begin:fine
hierarchy -check -top {top_module}
# =============================================================================
...
...
@@ -114,7 +112,7 @@ opt_clean
# =============================================================================
# Additional synthesis and full optimization
# =============================================================================
synth -flatten -extra-map
[file join $base_dir files_needed/lcu_kogge_stone.v]
-top {top_module} -run fine:check
synth -flatten -extra-map
{base_dir}/files_needed/lcu_kogge_stone.v
-top {top_module} -run fine:check
opt -fast -full
opt_expr -full
opt_merge
...
...
@@ -135,7 +133,7 @@ opt_expr -full
# =============================================================================
# Techmapping to target cells
# =============================================================================
techmap -map +/techmap.v -map
[file join $base_dir files_needed/lcu_kogge_stone.v]
techmap -map +/techmap.v -map
{base_dir}/files_needed/lcu_kogge_stone.v
opt -fast
opt_expr
opt_merge
...
...
@@ -171,7 +169,7 @@ opt_expr
# =============================================================================
# Specialized techmapping and logic extraction
# =============================================================================
techmap -map
[file join $base_dir files_needed/cells_tristatebuf.v]
techmap -map
{base_dir}/files_needed/cells_tristatebuf.v
techmap
opt -fast -purge
opt_expr
...
...
@@ -180,7 +178,7 @@ opt_dff
opt_clean -purge
extract_fa
techmap -map
[file join $base_dir files_needed/cells_adders.v]
techmap -map
{base_dir}/files_needed/cells_adders.v
techmap
opt -fast -purge
opt_expr
...
...
@@ -188,7 +186,7 @@ opt_merge
opt_dff
opt_clean -purge
techmap -map
[file join $base_dir files_needed/cells_latch.v]
techmap -map
{base_dir}/files_needed/cells_latch.v
techmap
opt -fast -purge
opt_expr
...
...
@@ -222,7 +220,7 @@ opt_expr
# =============================================================================
# Final ABC with constraints
# =============================================================================
abc -constr
[file join $base_dir files_needed/sc_abc.constraints]
-liberty {t_ech} -dont_use OAI211_X1 -dont_use CLKBUF_X1 -dont_use CLKBUF_X2 -dont_use CLKBUF_X3
abc -constr
{base_dir}/files_needed/sc_abc.constraints
-liberty {t_ech} -dont_use OAI211_X1 -dont_use CLKBUF_X1 -dont_use CLKBUF_X2 -dont_use CLKBUF_X3
# =============================================================================
# Post-mapping cleanup and output
...
...
examples/data_preprocess/codev.py
View file @
b06b4eb7
...
...
@@ -157,7 +157,7 @@ if __name__ == '__main__':
from
omegaconf
import
OmegaConf
tools_config_file
=
'examples/tir/sandbox_fusion_verilog_config.yaml'
tools
=
OmegaConf
.
load
(
tools_config_file
)
tools
=
[
OmegaConf
.
to_container
(
t
ools
.
tools
[
0
]
.
tool_schema
,
resolve
=
True
)
]
tools
=
[
OmegaConf
.
to_container
(
t
.
tool_schema
,
resolve
=
True
)
for
t
in
tools
.
tools
]
def
filter_by_token_len
(
example
):
question
=
make_question
(
example
[
"prompt"
])
...
...
@@ -170,7 +170,7 @@ if __name__ == '__main__':
)
token_len
=
len
(
token_ids
)
example
[
"question_token_len"
]
=
token_len
return
token_len
<=
MAX_TOKEN_LEN
-
2
0
return
token_len
<=
MAX_TOKEN_LEN
-
3
0
raw_dataset
=
raw_dataset
.
filter
(
function
=
filter_by_token_len
,
...
...
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