Code for Qimeng-3

src/readme.md

@@ -2,29 +2,13 @@ src/
 
 The latest version of the BSD Learner. 
 
-1. For AIGs, modify and run write_vec.h
+You only need to modify top.h:
 
-	Modify:
+	Line 2: change the include file to your io generator file name. For example: 		#include	"io_generator/c1908.h"	
 
-		Line 1 your own module name.
-
-	Execute in the terminal:
-
-		bash write_vec.sh
-
-2. Use BSD_Learner to design your own circuit.
-
-	Modify top.h: 
-
-		Line 1: modify input bitwidth;
-		Line 2: modify output bitwidth;
-		Line 3: include your own io_generator file. 
-		Line 4: If it is an AIG file, add its vec.h file generated from write_vec.sh.
-		Line 5: If it is a AIG, #define INPUT_AIG, otherwise do not define it.
-
-			Line 1:		extern const int	parameter_input_bit_width 	= 256+5; 	
-			Line 2:		extern const int	parameter_output_bit_width	= 129;	 	
-			Line 3:		#include"io_generator/adder.h"
-			Line 4:		#include             "adder_vec.h"
-			Line 5:		#define INPUT_AIG
+Your io generator function in the file need to start with the following head:
 
+	extern const int PI_WIDTH = 33;
+	extern const int PO_WIDTH = 25;
+	void io_generator_outer(bool* pi, bool* po) {
+	}

src/top.h

-#include "head.h"
+#include 	"head.h"
+#include	"io_generator/c1908.h"					//io_generator中需要包含对PI_WIDTH,PO_WIDTH的全局定义,如: extern const int PI_WIDTH = 36;
 
-#include       "io_generator/c1908.h"					//io_generator中需要包含对PI_WIDTH,PO_WIDTH的全局定义,如: extern const int PI_WIDTH = 36;
-#include   "io_generator_vec/c1908_vec.h"				//如果有对应Verilog, 可以在aag_to_rtl里面直接生成2个文件	
 
-//#include           "io_generator/ip-cores/combinational_circuits/c_prefix_arbiter_base.h"
-//#include       "io_generator/ip-cores/combinational_circuits_vec/c_prefix_arbiter_base_vec.h"
+
+
+//#include   "io_generator_vec/c1908_vec.h"				//如果有对应Verilog, 可以在aag_to_rtl里面直接生成2个文件	
 //#define INPUT_AIG							//io_generator是否可以用uint按位操作进行加速,也即是否包含_vec后缀的另一个io_generator
 //#define SINGLE_BITS							//io_generator是否包含每一个bit单独的io_generator_o{x}