add README

src/aag_to_cpp/README

+This program translate Verilog code to cpp for BSD
+
+	Modify:	execute.py  
+	
+		use the name of your module (for example, c432)
+	
+	./input_verilog		
+	
+		put your .v file here (for example, c432.v)
+	
+	./output_cpp
+	
+		get both .h files here (for example, c432.h c432_vec.h)
+
+
+run zstart.sh
+