Commit 4727bb3e by Zhengyue Zhao

Add new file

parent 5ceb7c32
module RISCV_pt(
PTE_address, PTE_valid,
PTE_ply,
PTE_out, PTE_out_valid,
);
input [31:0] PTE_address;
input PTE_valid;
input [1:0] PTE_ply;
output [31:0] PTE_out;
output PTE_valid;
parameter PTE_1_num = 1024;
parameter PTE_2_num = 1024*1024;
integer i;
wire [31:0] PTE_1[PTE_1_num-1:0];
wire [31:0] PTE_2[PTE_2_num-1:0];
for(i=0;i<PTE_1;i=i+1)
assign PTE_1[i]=i[20:0]+12{{$random}%2};
for(i=0;i<PTE_2_num;i=i+1)
assign PTE_2[i]=i[20:0]+12{{$random}%2};
if (PTE_valid && PTE_ply==2'b01)
begin
assign PTE_out=PTE_1[PTE_address[31:22]];
assign PTE_out_valid=1'b1;
end
else if(PTE_valid && PTE_ply==2'b10)
begin
assign PTE_out=PTE_2[PTE_address[31:12]];
assign PTE_out_valid=1'b1;
end
else
begin
assign PTE_out=32'h00000000;
assign PTE_out_valid=1'b0;
end
endmodule
\ No newline at end of file
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