Add new file

RISCV)mmu_driver.v

+module	RISCV_mmu_driver(
+		driver_on,
+		axi_read_data, axi_read_data_valid, axi_write_data_bvalid,
+		satp, mstatus, sstatus,
+		instruction_type, this_priviledge,
+		logic_axi_read_data_address, logic_axi_write_data_address,
+		logic_axi_write_data,
+		logic_axi_read_data_address_valid, logic_axi_write_data_valid,
+		store_data_size_in;
+		);
+		
+input			driver_on;
+
+output	[31:0]	axi_read_data;
+output			axi_read_data_valid;
+output 			axi_write_data_bvalid;
+
+output	[31:0]	satp;
+output 	[31:0]	mstatus;
+output 	[31:0]	sstatus;
+
+output 	[1:0]	instruction_type;
+output	[1:0]	this_priviledge;
+
+output 	[31:0]	logic_axi_read_data_address;
+output 	[31:0]	logic_axi_write_data_address;
+
+output 	[31:0]	logic_axi_write_data;
+
+output 			logic_axi_read_data_address_valid;
+output 			logic_axi_write_data_valid;
+output 	[1:0] 	store_data_size_in;
+
+assign axi_read_data = 32'd0;
+assign axi_read_data_valid = 1'b0;
+assign axi_write_data_bvalid = 1'b0;
+
+if(driver_on)
+begin
+	assign satp[31]=1;
+	assign satp[30:0]=31'd0;
+	assign mstatus = 32{{$random}%2};
+	assign sstatus = 32{{$random}%2};
+
+	assign instruction_type=2'b10;
+	assign this_priviledge=2'b01;
+
+	assign logic_axi_read_data_address=32{{$random}%2};
+	assign logic_axi_write_data_address=32{{$random}%2};
+	assign logic_axi_write_data=32{{$random}%2};
+	
+	assign logic_axi_read_data_address_valid=this_priviledge[0];
+	assign logic_axi_write_data_valid=this_priviledge[1];
+	
+	assign store_data_size_in = 2'b01;
+
+end
+else
+begin
+	assign satp[32]=32'd0;
+	assign mstatus = 32'd0;
+	assign sstatus = 32'd0;
+
+	assign instruction_type=2'b00;
+	assign this_priviledge=2'b00;
+
+	assign logic_axi_read_data_address=32'd0;
+	assign logic_axi_write_data_address=32'd0;
+	assign logic_axi_write_data=32'd0;
+	
+	assign logic_axi_read_data_address_valid=1'b0;
+	assign logic_axi_write_data_valid=1'b0;
+	
+	assign store_data_size_in = 2'b00;
+end
+
+
+endmodule
\ No newline at end of file