Add new file

RISCV_mm.v

+
+module RISCV_mm(reset, clk,
+				read_address, read_valid
+				write_address, write_data, write_valid,
+				store_data_size,
+				read_data, read_data_valid,
+				write_data_bvalid);
+	input reset, clk;
+	input [31:0] read_address, write_address, write_data;
+	input read_valid, write_valid;
+	input [1:0] store_data_size;
+	output [31:0] read_data;
+	output read_data_valid, write_data_bvalid;
+
+	wire [31:0]	Address;
+	assign Address = read_valid?read_address:write_valid?write_address:32'b0;
+	
+	
+	parameter RAM_SIZE = 1024*1024;
+	parameter RAM_SIZE_BIT = 20;
+	
+	reg [31:0] RAM_data[RAM_SIZE - 1: 0];
+	assign read_data = read_valid? RAM_data[Address[31:12]]: 32'h00000000;
+	assign read_data_valid = read_valid? 1'b1:1'b0;
+
+	integer i;
+	always @(posedge reset or posedge clk)
+		if (reset)
+			for (i = 0; i < RAM_SIZE; i = i + 1)
+				RAM_data[i] <= 32'h00000000;
+		else if (write_valid)
+		begin
+			RAM_data[Address[31:12]] <= write_data[store_data_size*8-1:0];
+			write_data_bvalid=1'b0;
+		end
+			
+endmodule