Skip to content
Projects
Groups
Snippets
Help
This project
Loading...
Sign in / Register
Toggle navigation
T
tic
Overview
Overview
Details
Activity
Cycle Analytics
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Charts
Issues
0
Issues
0
List
Board
Labels
Milestones
Merge Requests
0
Merge Requests
0
CI / CD
CI / CD
Pipelines
Jobs
Schedules
Charts
Wiki
Wiki
Snippets
Snippets
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Charts
Create a new issue
Jobs
Commits
Issue Boards
Open sidebar
wenyuanbo
tic
Commits
f397fead
Commit
f397fead
authored
Jan 24, 2019
by
Wuwei Lin
Committed by
Yizhi Liu
Jan 23, 2019
Browse files
Options
Browse Files
Download
Email Patches
Plain Diff
[RELAY] Fix ops in packed layout (#2472)
* [RELAY] Fix ops in packed layout * Fix style
parent
32549dec
Show whitespace changes
Inline
Side-by-side
Showing
3 changed files
with
11 additions
and
2 deletions
+11
-2
src/relay/op/nn/pooling.cc
+5
-1
src/relay/op/tensor/transform.cc
+2
-1
tests/python/relay/test_pass_alter_op_layout.py
+4
-0
No files found.
src/relay/op/nn/pooling.cc
View file @
f397fead
...
@@ -83,7 +83,11 @@ bool Pool2DRel(const Array<Type>& types,
...
@@ -83,7 +83,11 @@ bool Pool2DRel(const Array<Type>& types,
return
false
;
return
false
;
}
}
std
::
vector
<
IndexExpr
>
oshape
({
dshape
[
0
],
dshape
[
1
],
dshape
[
2
],
dshape
[
3
]});
std
::
vector
<
IndexExpr
>
oshape
;
for
(
const
auto
&
e
:
dshape
)
{
oshape
.
push_back
(
e
);
}
if
(
param
->
ceil_mode
)
{
if
(
param
->
ceil_mode
)
{
oshape
[
hidx
]
=
((
dshape
[
hidx
]
+
pad_h
-
param
->
pool_size
[
0
]
+
oshape
[
hidx
]
=
((
dshape
[
hidx
]
+
pad_h
-
param
->
pool_size
[
0
]
+
param
->
strides
[
0
]
-
1
)
/
param
->
strides
[
0
])
+
1
;
param
->
strides
[
0
]
-
1
)
/
param
->
strides
[
0
])
+
1
;
...
...
src/relay/op/tensor/transform.cc
View file @
f397fead
...
@@ -76,7 +76,8 @@ RELAY_REGISTER_OP("cast")
...
@@ -76,7 +76,8 @@ RELAY_REGISTER_OP("cast")
.
set_support_level
(
3
)
.
set_support_level
(
3
)
.
add_type_rel
(
"Cast"
,
CastRel
)
.
add_type_rel
(
"Cast"
,
CastRel
)
.
set_attr
<
FTVMCompute
>
(
"FTVMCompute"
,
CastCompute
)
.
set_attr
<
FTVMCompute
>
(
"FTVMCompute"
,
CastCompute
)
.
set_attr
<
TOpPattern
>
(
"TOpPattern"
,
kElemWise
);
.
set_attr
<
TOpPattern
>
(
"TOpPattern"
,
kElemWise
)
.
set_attr
<
FInferCorrectLayout
>
(
"FInferCorrectLayout"
,
ElemwiseArbitraryLayout
);
// relay.expand_dims
// relay.expand_dims
TVM_REGISTER_NODE_TYPE
(
ExpandDimsAttrs
);
TVM_REGISTER_NODE_TYPE
(
ExpandDimsAttrs
);
...
...
tests/python/relay/test_pass_alter_op_layout.py
View file @
f397fead
...
@@ -82,6 +82,8 @@ def test_alter_layout():
...
@@ -82,6 +82,8 @@ def test_alter_layout():
# a useless tuple, which will be eliminated
# a useless tuple, which will be eliminated
y
=
relay
.
Tuple
([
y
])[
0
]
y
=
relay
.
Tuple
([
y
])[
0
]
y
=
relay
.
nn
.
relu
(
y
)
y
=
relay
.
nn
.
relu
(
y
)
y
=
relay
.
nn
.
max_pool2d
(
y
,
pool_size
=
(
2
,
2
))
y
=
relay
.
cast
(
y
,
'int32'
)
y
=
relay
.
nn
.
batch_flatten
(
y
)
y
=
relay
.
nn
.
batch_flatten
(
y
)
y
=
relay
.
Function
(
free_vars
(
y
),
y
)
y
=
relay
.
Function
(
free_vars
(
y
),
y
)
return
y
return
y
...
@@ -112,6 +114,8 @@ def test_alter_layout():
...
@@ -112,6 +114,8 @@ def test_alter_layout():
y
=
relay
.
add
(
y
,
b
)
y
=
relay
.
add
(
y
,
b
)
y
=
relay
.
nn
.
relu
(
y
)
y
=
relay
.
nn
.
relu
(
y
)
y
=
relay
.
nn
.
max_pool2d
(
y
,
pool_size
=
(
2
,
2
),
layout
=
"NCHW16c"
)
y
=
relay
.
cast
(
y
,
'int32'
)
y
=
relay
.
layout_transform
(
y
,
"NCHW16c"
,
"NCHW"
)
y
=
relay
.
layout_transform
(
y
,
"NCHW16c"
,
"NCHW"
)
y
=
relay
.
nn
.
batch_flatten
(
y
)
y
=
relay
.
nn
.
batch_flatten
(
y
)
y
=
relay
.
Function
(
free_vars
(
y
),
y
)
y
=
relay
.
Function
(
free_vars
(
y
),
y
)
...
...
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment