[VTA] [Chisel] fix tensor issue/commit in gemm (#3637)

* fix tensor issue/commit in gemm

* remove trailing spaces

vta/hardware/chisel/src/main/scala/core/TensorGemm.scala

@@ -226,9 +226,9 @@ class TensorGemm(debug: Boolean = false)(implicit p: Parameters) extends Module
   when (state === sIdle) {
     inflight := 0.U
   } .elsewhen (!dec.reset) {
-    when (state === sExe && inflight =/= ((1 << pBits) - 1).asUInt) { // overflow check
+    when (state === sReadTensor) { // issue a tensor
       inflight := inflight + 1.U
-    } .elsewhen (mvc.io.acc_o.data.valid && inflight =/= 0.U) { // underflow check
+    } .elsewhen (mvc.io.acc_o.data.valid) { // commit a tensor
       inflight := inflight - 1.U
     }
   }

vta/hardware/chisel/src/main/scala/core/TensorStore.scala

@@ -28,7 +28,7 @@ import vta.shell._
   *
   * Store 1D and 2D tensors from out-scratchpad (SRAM) to main memory (DRAM).
   */
-class TensorStore(tensorType: String = "true", debug: Boolean = false)
+class TensorStore(tensorType: String = "none", debug: Boolean = false)
   (implicit p: Parameters) extends Module {
   val tp = new TensorParams(tensorType)
   val mp = p(ShellKey).memParams