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wenyuanbo
tic
Commits
7cc92ace
Commit
7cc92ace
authored
7 years ago
by
ziheng
Committed by
Tianqi Chen
7 years ago
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[LANG] Expose tvm.cast (#195)
* [LANG] Expose tvm.cast * Update * Add unittest
parent
7c6a71ba
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4 changed files
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34 additions
and
0 deletions
+34
-0
python/tvm/api.py
+17
-0
python/tvm/expr.py
+14
-0
src/api/api_ir.cc
+1
-0
tests/python/unittest/test_lang_tensor.py
+2
-0
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python/tvm/api.py
View file @
7cc92ace
...
...
@@ -467,6 +467,23 @@ def reduce_axis(dom, name="rv"):
"""
return
_IterVar
(
dom
,
name
,
2
)
def
cast
(
dtype
,
expr
):
"""Cast an expression to other type
Parameters
----------
dtype : str, optional
The type of new expression
expr : Expr
The expression
Returns
-------
expr : Expr
Expression with new type
"""
return
_make
.
Cast
(
dtype
,
expr
)
def
select
(
cond
,
t
,
f
):
"""Construct a select branch
Parameters
...
...
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Click to expand it.
python/tvm/expr.py
View file @
7cc92ace
...
...
@@ -89,6 +89,20 @@ class ExprOp(object):
"""
return
_make
.
EQ
(
self
,
other
)
def
astype
(
self
,
dtype
):
"""Cast the expression to other type
Parameters
----------
dtype : str, optional
The type of new expression
Returns
-------
expr : Expr
Expression with new type
"""
return
_make
.
Cast
(
dtype
,
self
)
class
Expr
(
NodeBase
,
ExprOp
):
"""Base class of all tvm Expressions"""
...
...
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Click to expand it.
src/api/api_ir.cc
View file @
7cc92ace
...
...
@@ -139,6 +139,7 @@ REGISTER_MAKE_BINARY_OP(Or);
REGISTER_MAKE1
(
Not
);
REGISTER_MAKE3
(
Select
);
REGISTER_MAKE3
(
Ramp
);
REGISTER_MAKE2
(
Cast
);
REGISTER_MAKE2
(
Broadcast
);
REGISTER_MAKE3
(
Let
);
REGISTER_MAKE3
(
LetStmt
);
...
...
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tests/python/unittest/test_lang_tensor.py
View file @
7cc92ace
...
...
@@ -16,6 +16,8 @@ def test_tensor():
assert
(
T
.
op
.
output
(
0
)
.
__hash__
()
==
T
.
__hash__
())
d
=
{
T
.
op
.
output
(
0
)
:
1
}
assert
(
d
[
T
]
==
1
)
assert
(
tvm
.
cast
(
'float16'
,
T
[
0
][
0
][
0
])
.
dtype
==
'float16'
)
assert
(
T
[
0
][
0
][
0
]
.
astype
(
'float16'
)
.
dtype
==
'float16'
)
def
test_conv1d
():
...
...
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