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Unverified Commit 6a36fb40 by Liangfu Chen Committed by GitHub
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[VTA][Chisel] Change Scala Linter scalafmt => scalastyle (#4998) 

* scalafmt => scalastyle

Change-Id: Ifc590e7cb63585f35dfdc9efcf3c6287b1afb1dd

* scalafmt => scalastyle

Change-Id: I8aff2632dadda05d2896e28bdaf6f780a160a15a

* add indentation constraint

Change-Id: Ibeb00c11a5718ea47322ea2b82e757828af8af91

* trigger ci again
parent 62424611
Showing with 194 additions and 166 deletions
vta/apps/tsim_example/hardware/chisel/.scalafmt.conf deleted 100644 → 0
/*
* Licensed to the Apache Software Foundation (ASF) under one
* or more contributor license agreements. See the NOTICE file
* distributed with this work for additional information
* regarding copyright ownership. The ASF licenses this file
* to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance
* with the License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing,
* software distributed under the License is distributed on an
* "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
* KIND, either express or implied. See the License for the
* specific language governing permissions and limitations
* under the License.
*/
maxColumn = 100
rewrite.rules = [SortModifiers, SortImports]
vta/apps/tsim_example/hardware/chisel/Makefile
......@@ -94,7 +94,8 @@ endif
default: lint lib
lint:
sbt scalafmt
cp $(vta_dir)/hardware/chisel/scalastyle-config.xml .
sbt scalastyle
lib: $(lib_path)
$(lib_path): $(verilator_build_dir)/V$(TOP).cpp
......
vta/apps/tsim_example/hardware/chisel/project/plugins.sbt
......@@ -18,4 +18,4 @@
*/
logLevel := Level.Warn
addSbtPlugin("com.geirsson" % "sbt-scalafmt" % "1.5.1")
addSbtPlugin("org.scalastyle" %% "scalastyle-sbt-plugin" % "1.0.0")
vta/apps/tsim_example/hardware/chisel/src/main/scala/accel/RegFile.scala
......@@ -39,7 +39,7 @@ import vta.dpi._
* Output pointer lsb | 0x18
* Output pointer msb | 0x1c
* -------------------------------
*
* ------------------------------
* Control status register | bit
* ------------------------------
......@@ -98,8 +98,7 @@ class RegFile(implicit config: AccelConfig) extends Module {
}
for (i <- 0 until (config.nVals + (2 * config.nPtrs))) {
when(
state === sIdle && io.host.req.valid &&
when(state === sIdle && io.host.req.valid &&
io.host.req.opcode && addr(vo + i).U === io.host.req.addr) {
reg(vo + i) := io.host.req.value
}
......
vta/hardware/chisel/.scalafmt.conf deleted 100644 → 0
/*
* Licensed to the Apache Software Foundation (ASF) under one
* or more contributor license agreements. See the NOTICE file
* distributed with this work for additional information
* regarding copyright ownership. The ASF licenses this file
* to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance
* with the License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing,
* software distributed under the License is distributed on an
* "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
* KIND, either express or implied. See the License for the
* specific language governing permissions and limitations
* under the License.
*/
maxColumn = 100
rewrite.rules = [SortModifiers, SortImports]
vta/hardware/chisel/Makefile
......@@ -112,7 +112,7 @@ endif
default: lint lib
lint:
sbt scalafmt --test
sbt scalastyle
lib: $(lib_path)
......
vta/hardware/chisel/project/plugins.sbt
......@@ -18,4 +18,4 @@
*/
logLevel := Level.Warn
addSbtPlugin("com.geirsson" % "sbt-scalafmt" % "1.5.1")
addSbtPlugin("org.scalastyle" %% "scalastyle-sbt-plugin" % "1.0.0")
vta/hardware/chisel/scalastyle-config.xml 0 → 100644
<scalastyle>
<name>Scalastyle standard configuration</name>
<check level="error" class="org.scalastyle.file.FileTabChecker" enabled="true"></check>
<check level="error" class="org.scalastyle.file.FileLengthChecker" enabled="true">
<parameters>
<parameter name="maxFileLength"><![CDATA[800]]></parameter>
</parameters>
</check>
<check level="error" class="org.scalastyle.file.HeaderMatchesChecker" enabled="true">
<parameters>
<parameter name="header"><![CDATA[/*
* Licensed to the Apache Software Foundation (ASF) under one
* or more contributor license agreements. See the NOTICE file
* distributed with this work for additional information
* regarding copyright ownership. The ASF licenses this file
* to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance
* with the License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing,
* software distributed under the License is distributed on an
* "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
* KIND, either express or implied. See the License for the
* specific language governing permissions and limitations
* under the License.
*/
]]></parameter>
</parameters>
</check>
<check level="error" class="org.scalastyle.scalariform.SpacesAfterPlusChecker" enabled="true"></check>
<check level="error" class="org.scalastyle.file.WhitespaceEndOfLineChecker" enabled="true"></check>
<check level="error" class="org.scalastyle.scalariform.SpacesBeforePlusChecker" enabled="true"></check>
<check level="error" class="org.scalastyle.file.FileLineLengthChecker" enabled="true">
<parameters>
<parameter name="maxLineLength"><![CDATA[120]]></parameter>
<parameter name="tabSize"><![CDATA[2]]></parameter>
</parameters>
</check>
<check level="error" class="org.scalastyle.scalariform.ClassNamesChecker" enabled="true">
<parameters>
<parameter name="regex"><![CDATA[[A-Z][A-Za-z]*]]></parameter>
</parameters>
</check>
<check level="error" class="org.scalastyle.scalariform.ObjectNamesChecker" enabled="true">
<parameters>
<parameter name="regex"><![CDATA[[A-Z][A-Za-z]*]]></parameter>
</parameters>
</check>
<check level="error" class="org.scalastyle.scalariform.PackageObjectNamesChecker" enabled="true">
<parameters>
<parameter name="regex"><![CDATA[^[a-z][A-Za-z]*$]]></parameter>
</parameters>
</check>
<check level="error" class="org.scalastyle.scalariform.EqualsHashCodeChecker" enabled="true"></check>
<check level="error" class="org.scalastyle.scalariform.IllegalImportsChecker" enabled="true">
<parameters>
<parameter name="illegalImports"><![CDATA[sun._,java.awt._]]></parameter>
</parameters>
</check>
<check level="error" class="org.scalastyle.scalariform.ParameterNumberChecker" enabled="true">
<parameters>
<parameter name="maxParameters"><![CDATA[8]]></parameter>
</parameters>
</check>
<check level="error" class="org.scalastyle.scalariform.MagicNumberChecker" enabled="false">
<parameters>
<parameter name="ignore"><![CDATA[-1,0,1,2,3,4,8,16,32,64,128]]></parameter>
</parameters>
</check>
<check level="error" class="org.scalastyle.scalariform.NoWhitespaceBeforeLeftBracketChecker" enabled="true"></check>
<check level="error" class="org.scalastyle.scalariform.NoWhitespaceAfterLeftBracketChecker" enabled="true"></check>
<check level="error" class="org.scalastyle.scalariform.ReturnChecker" enabled="true"></check>
<check level="error" class="org.scalastyle.scalariform.NullChecker" enabled="true"></check>
<check level="error" class="org.scalastyle.scalariform.NoCloneChecker" enabled="true"></check>
<check level="error" class="org.scalastyle.scalariform.NoFinalizeChecker" enabled="true"></check>
<check level="error" class="org.scalastyle.scalariform.CovariantEqualsChecker" enabled="true"></check>
<check level="error" class="org.scalastyle.scalariform.StructuralTypeChecker" enabled="true"></check>
<check level="error" class="org.scalastyle.file.RegexChecker" enabled="true">
<parameters>
<parameter name="regex"><![CDATA[println]]></parameter>
</parameters>
</check>
<check level="error" class="org.scalastyle.scalariform.NumberOfTypesChecker" enabled="true">
<parameters>
<parameter name="maxTypes"><![CDATA[30]]></parameter>
</parameters>
</check>
<check level="error" class="org.scalastyle.scalariform.CyclomaticComplexityChecker" enabled="true">
<parameters>
<parameter name="maximum"><![CDATA[10]]></parameter>
</parameters>
</check>
<check level="error" class="org.scalastyle.scalariform.UppercaseLChecker" enabled="true"></check>
<check level="error" class="org.scalastyle.scalariform.SimplifyBooleanExpressionChecker" enabled="true"></check>
<check level="error" class="org.scalastyle.scalariform.IfBraceChecker" enabled="false">
<parameters>
<parameter name="singleLineAllowed"><![CDATA[true]]></parameter>
<parameter name="doubleLineAllowed"><![CDATA[false]]></parameter>
</parameters>
</check>
<check level="error" class="org.scalastyle.scalariform.MethodLengthChecker" enabled="true">
<parameters>
<parameter name="maxLength"><![CDATA[50]]></parameter>
</parameters>
</check>
<check level="error" class="org.scalastyle.scalariform.MethodNamesChecker" enabled="false">
<parameters>
<parameter name="regex"><![CDATA[^[a-z][A-Za-z0-9]*$]]></parameter>
</parameters>
</check>
<check level="error" class="org.scalastyle.scalariform.NumberOfMethodsInTypeChecker" enabled="true">
<parameters>
<parameter name="maxMethods"><![CDATA[30]]></parameter>
</parameters>
</check>
<check level="error" class="org.scalastyle.scalariform.PublicMethodsHaveTypeChecker" enabled="false"></check>
<check level="error" class="org.scalastyle.file.NewLineAtEofChecker" enabled="true"></check>
<check level="error" class="org.scalastyle.file.NoNewLineAtEofChecker" enabled="false"></check>
<check level="error" class="org.scalastyle.file.IndentationChecker" enabled="true">
<parameters>
<parameter name="tabSize">2</parameter>
<parameter name="methodParamIndentSize">2</parameter>
<parameter name="classParamIndentSize">4</parameter>
</parameters>
</check>
</scalastyle>
vta/hardware/chisel/src/main/scala/core/Compute.scala
......@@ -116,20 +116,14 @@ class Compute(debug: Boolean = false)(implicit p: Parameters) extends Module {
loadUop.io.inst := inst_q.io.deq.bits
loadUop.io.baddr := io.uop_baddr
io.vme_rd(0) <> loadUop.io.vme_rd
loadUop.io.uop.idx <> Mux(dec.io.isGemm,
tensorGemm.io.uop.idx,
tensorAlu.io.uop.idx)
loadUop.io.uop.idx <> Mux(dec.io.isGemm, tensorGemm.io.uop.idx, tensorAlu.io.uop.idx)
// acc
tensorAcc.io.start := state === sIdle & start & dec.io.isLoadAcc
tensorAcc.io.inst := inst_q.io.deq.bits
tensorAcc.io.baddr := io.acc_baddr
tensorAcc.io.tensor.rd.idx <> Mux(dec.io.isGemm,
tensorGemm.io.acc.rd.idx,
tensorAlu.io.acc.rd.idx)
tensorAcc.io.tensor.wr <> Mux(dec.io.isGemm,
tensorGemm.io.acc.wr,
tensorAlu.io.acc.wr)
tensorAcc.io.tensor.rd.idx <> Mux(dec.io.isGemm, tensorGemm.io.acc.rd.idx, tensorAlu.io.acc.rd.idx)
tensorAcc.io.tensor.wr <> Mux(dec.io.isGemm, tensorGemm.io.acc.wr, tensorAlu.io.acc.wr)
io.vme_rd(1) <> tensorAcc.io.vme_rd
// gemm
......@@ -179,17 +173,13 @@ class Compute(debug: Boolean = false)(implicit p: Parameters) extends Module {
printf("[Compute] start sync\n")
}.elsewhen(dec.io.isLoadUop) {
printf("[Compute] start load uop\n")
}
.elsewhen(dec.io.isLoadAcc) {
}.elsewhen(dec.io.isLoadAcc) {
printf("[Compute] start load acc\n")
}
.elsewhen(dec.io.isGemm) {
}.elsewhen(dec.io.isGemm) {
printf("[Compute] start gemm\n")
}
.elsewhen(dec.io.isAlu) {
}.elsewhen(dec.io.isAlu) {
printf("[Compute] start alu\n")
}
.elsewhen(dec.io.isFinish) {
}.elsewhen(dec.io.isFinish) {
printf("[Compute] start finish\n")
}
}
......@@ -203,14 +193,11 @@ class Compute(debug: Boolean = false)(implicit p: Parameters) extends Module {
printf("[Compute] done load uop\n")
}.elsewhen(dec.io.isLoadAcc) {
printf("[Compute] done load acc\n")
}
.elsewhen(dec.io.isGemm) {
}.elsewhen(dec.io.isGemm) {
printf("[Compute] done gemm\n")
}
.elsewhen(dec.io.isAlu) {
}.elsewhen(dec.io.isAlu) {
printf("[Compute] done alu\n")
}
.elsewhen(dec.io.isFinish) {
}.elsewhen(dec.io.isFinish) {
printf("[Compute] done finish\n")
}
}
......
vta/hardware/chisel/src/main/scala/core/Configs.scala
......@@ -27,8 +27,7 @@ import vta.util.config._
* be eventually filled out with class configurations that can be
* mixed/matched with Shell configurations for different backends.
*/
class CoreConfig
extends Config((site, here, up) => {
class CoreConfig extends Config((site, here, up) => {
case CoreKey =>
CoreParams(
batch = 1,
......@@ -46,4 +45,4 @@ class CoreConfig
outMemDepth = 2048,
instQueueEntries = 512
)
})
})
vta/hardware/chisel/src/main/scala/core/EventCounters.scala
......@@ -38,8 +38,7 @@ import vta.shell._
* If one would like to add an event counter, then the value of nECnt must be
* changed in VCRParams together with the corresponding counting logic here.
*/
class EventCounters(debug: Boolean = false)(implicit p: Parameters)
extends Module {
class EventCounters(debug: Boolean = false)(implicit p: Parameters) extends Module {
val vp = p(ShellKey).vcrParams
val io = IO(new Bundle {
val launch = Input(Bool())
......
vta/hardware/chisel/src/main/scala/core/Fetch.scala
......@@ -116,8 +116,7 @@ class Fetch(debug: Boolean = false)(implicit p: Parameters) extends Module {
rlen := xrem
ilen := xrem >> 1.U
xrem := 0.U
}
.otherwise {
}.otherwise {
state := sReadCmd
rlen := xmax - 1.U
ilen := (xmax >> 1.U) - 1.U
......
vta/hardware/chisel/src/main/scala/core/Load.scala
......@@ -111,8 +111,7 @@ class Load(debug: Boolean = false)(implicit p: Parameters) extends Module {
printf("[Load] start sync\n")
}.elsewhen(dec.io.isInput) {
printf("[Load] start input\n")
}
.elsewhen(dec.io.isWeight) {
}.elsewhen(dec.io.isWeight) {
printf("[Load] start weight\n")
}
}
......
vta/hardware/chisel/src/main/scala/core/LoadUop.scala
......@@ -116,8 +116,7 @@ class LoadUop(debug: Boolean = false)(implicit p: Parameters) extends Module {
state := sReadCmd
xlen := xrem
xrem := 0.U
}
.otherwise {
}.otherwise {
state := sReadCmd
xlen := xmax - 1.U
xrem := xrem - xmax
......@@ -171,8 +170,7 @@ class LoadUop(debug: Boolean = false)(implicit p: Parameters) extends Module {
}.otherwise {
wmask := "b_11".U.asTypeOf(wmask)
}
}
.elsewhen(io.vme_rd.data.fire()) {
}.elsewhen(io.vme_rd.data.fire()) {
when((xcnt === xlen - 1.U) && (xrem === 0.U)) {
wmask := "b_01".U.asTypeOf(wmask)
}.otherwise {
......
vta/hardware/chisel/src/main/scala/core/Semaphore.scala
......@@ -29,8 +29,7 @@ import chisel3.util._
* depending on the push and pop fields on instructions to prevent RAW and WAR
* hazards.
*/
class Semaphore(counterBits: Int = 1, counterInitValue: Int = 1)
extends Module {
class Semaphore(counterBits: Int = 1, counterInitValue: Int = 1) extends Module {
val io = IO(new Bundle {
val spost = Input(Bool())
val swait = Input(Bool())
......
vta/hardware/chisel/src/main/scala/core/TensorAlu.scala
......@@ -39,11 +39,8 @@ class Alu(implicit p: Parameters) extends Module {
val m = ~ub(width - 1, 0) + 1.U
val n = ub(width - 1, 0)
val fop = Seq(Mux(io.a < io.b, io.a, io.b),
Mux(io.a < io.b, io.b, io.a),
io.a + io.b,
io.a >> n,
io.a << m)
val fop = Seq(Mux(io.a < io.b, io.a, io.b), Mux(io.a < io.b, io.b, io.a),
io.a + io.b, io.a >> n, io.a << m)
val opmux = Seq.tabulate(ALU_OP_NUM)(i => ALU_OP(i) -> fop(i))
io.y := MuxLookup(io.opcode, io.a, opmux)
......@@ -203,11 +200,7 @@ class TensorAlu(debug: Boolean = false)(implicit p: Parameters) extends Module {
cnt_i := 0.U
dst_i := dst_o
src_i := src_o
}
.elsewhen(
state === sExe &&
alu.io.out.data.valid &&
uop_idx === uop_end - 1.U) {
}.elsewhen(state === sExe && alu.io.out.data.valid && uop_idx === uop_end - 1.U) {
cnt_i := cnt_i + 1.U
dst_i := dst_i + dec.dst_1
src_i := src_i + dec.src_1
......
vta/hardware/chisel/src/main/scala/core/TensorGemm.scala
......@@ -86,8 +86,7 @@ class Adder(aBits: Int = 8, bBits: Int = 8) extends Module {
}
/** Pipelined DotProduct based on MAC and PipeAdder */
class DotProduct(aBits: Int = 8, bBits: Int = 8, size: Int = 16)
extends Module {
class DotProduct(aBits: Int = 8, bBits: Int = 8, size: Int = 16) extends Module {
val errorMsg =
s"\n\n[VTA] [DotProduct] size must be greater than 4 and a power of 2\n\n"
require(size >= 2 && isPow2(size), errorMsg)
......@@ -183,8 +182,7 @@ class MatrixVectorMultiplication(implicit p: Parameters) extends Module {
* Also, the TensorGemm uses the reset field in the Gemm instruction to
* clear or zero-out the acc-scratchpad locations based on the micro-ops.
*/
class TensorGemm(debug: Boolean = false)(implicit p: Parameters)
extends Module {
class TensorGemm(debug: Boolean = false)(implicit p: Parameters) extends Module {
val io = IO(new Bundle {
val start = Input(Bool())
val done = Output(Bool())
......@@ -269,8 +267,7 @@ class TensorGemm(debug: Boolean = false)(implicit p: Parameters)
inflight := inflight
}.elsewhen(state === sReadTensor) { // issue a tensor
inflight := inflight + 1.U
}
.elsewhen(mvc.io.acc_o.data.valid) { // commit a tensor
}.elsewhen(mvc.io.acc_o.data.valid) { // commit a tensor
inflight := inflight - 1.U
}
}
......@@ -309,8 +306,7 @@ class TensorGemm(debug: Boolean = false)(implicit p: Parameters)
acc_i := acc_o
inp_i := inp_o
wgt_i := wgt_o
}
.elsewhen(state === sExe && uop_idx === uop_end - 1.U) {
}.elsewhen(state === sExe && uop_idx === uop_end - 1.U) {
cnt_i := cnt_i + 1.U
acc_i := acc_i + dec.acc_1
inp_i := inp_i + dec.inp_1
......@@ -351,9 +347,8 @@ class TensorGemm(debug: Boolean = false)(implicit p: Parameters)
mvc.io.acc_i.data <> io.acc.rd.data
// acc_o
io.acc.wr.valid := mvc.io.acc_o.data.valid & Mux(dec.reset,
true.B,
wrpipe.io.deq.valid)
io.acc.wr.valid := mvc.io.acc_o.data.valid &
Mux(dec.reset, true.B, wrpipe.io.deq.valid)
io.acc.wr.bits.idx := Mux(dec.reset, uop_acc, wrpipe.io.deq.bits)
io.acc.wr.bits.data <> mvc.io.acc_o.data.bits
......@@ -371,10 +366,7 @@ class TensorGemm(debug: Boolean = false)(implicit p: Parameters)
}
when(state === sReadTensor && ~dec.reset) {
printf("[TensorGemm] [uop] acc:%x inp:%x wgt:%x\n",
uop_acc,
uop_inp,
uop_wgt)
printf("[TensorGemm] [uop] acc:%x inp:%x wgt:%x\n", uop_acc, uop_inp, uop_wgt)
}
io.inp.rd.data.bits.zipWithIndex.foreach {
......
vta/hardware/chisel/src/main/scala/core/TensorLoad.scala
......@@ -72,8 +72,7 @@ class TensorLoad(tensorType: String = "none", debug: Boolean = false)(
state := sYPad0
}.elsewhen(dec.xpad_0 =/= 0.U) {
state := sXPad0
}
.otherwise {
}.otherwise {
state := sReadCmd
}
}
......@@ -215,8 +214,7 @@ class TensorLoad(tensorType: String = "none", debug: Boolean = false)(
}.elsewhen((io.vme_rd.data
.fire() || isZeroPad) && set === (tp.tensorLength - 1).U && tag === (tp.numMemBlock - 1).U) {
waddr_cur := waddr_cur + 1.U
}
.elsewhen(dataCtrl.io.stride) {
}.elsewhen(dataCtrl.io.stride) {
waddr_cur := waddr_nxt + dec.xsize
waddr_nxt := waddr_nxt + dec.xsize
}
......
vta/hardware/chisel/src/main/scala/core/TensorStore.scala
......@@ -115,8 +115,7 @@ class TensorStore(tensorType: String = "none", debug: Boolean = false)(
state := sWriteCmd
xlen := xrem
xrem := 0.U
}
.otherwise {
}.otherwise {
state := sWriteCmd
xlen := xmax - 1.U
xrem := xrem - xmax
......@@ -178,8 +177,7 @@ class TensorStore(tensorType: String = "none", debug: Boolean = false)(
}.elsewhen(io.vme_wr.data
.fire() && set === (tensorLength - 1).U && tag === (numMemBlock - 1).U) {
raddr_cur := raddr_cur + 1.U
}
.elsewhen(stride) {
}.elsewhen(stride) {
raddr_cur := raddr_nxt + dec.xsize
raddr_nxt := raddr_nxt + dec.xsize
}
......@@ -200,12 +198,9 @@ class TensorStore(tensorType: String = "none", debug: Boolean = false)(
elemBytes)))
}.elsewhen(state === sWriteAck && io.vme_wr.ack && xrem =/= 0.U) {
waddr_cur := waddr_cur + xmax_bytes
}
.elsewhen(stride) {
waddr_cur := waddr_nxt + (dec.xstride << log2Ceil(
tensorLength * tensorWidth))
waddr_nxt := waddr_nxt + (dec.xstride << log2Ceil(
tensorLength * tensorWidth))
}.elsewhen(stride) {
waddr_cur := waddr_nxt + (dec.xstride << log2Ceil(tensorLength * tensorWidth))
waddr_nxt := waddr_nxt + (dec.xstride << log2Ceil(tensorLength * tensorWidth))
}
io.vme_wr.cmd.valid := state === sWriteCmd
......@@ -231,12 +226,7 @@ class TensorStore(tensorType: String = "none", debug: Boolean = false)(
if (debug) {
when(io.vme_wr.cmd.fire()) {
printf("[TensorStore] ysize:%x ycnt:%x raddr:%x waddr:%x len:%x rem:%x\n",
ysize,
ycnt,
raddr_cur,
waddr_cur,
xlen,
xrem)
ysize, ycnt, raddr_cur, waddr_cur, xlen, xrem)
}
when(io.vme_wr.data.fire()) {
printf("[TensorStore] data:%x\n", io.vme_wr.data.bits)
......
vta/hardware/chisel/src/main/scala/core/TensorUtil.scala
......@@ -30,8 +30,7 @@ import vta.shell._
* weights (wgt), biases (acc), and outputs (out). This is used to avoid
* doing the same boring calculations over and over again.
*/
class TensorParams(tensorType: String = "none")(implicit p: Parameters)
extends Bundle {
class TensorParams(tensorType: String = "none")(implicit p: Parameters) extends Bundle {
val errorMsg =
s"\n\n[VTA] [TensorParams] only inp, wgt, acc, and out supported\n\n"
......@@ -72,8 +71,8 @@ class TensorParams(tensorType: String = "none")(implicit p: Parameters)
* biases (acc), and outputs (out).
*
*/
class TensorMaster(tensorType: String = "none")(implicit p: Parameters)
extends TensorParams(tensorType) {
class TensorMaster(tensorType: String = "none")
(implicit p: Parameters) extends TensorParams(tensorType) {
val rd = new Bundle {
val idx = ValidIO(UInt(memAddrBits.W))
val data = Flipped(
......@@ -106,8 +105,8 @@ class TensorMaster(tensorType: String = "none")(implicit p: Parameters)
* The TensorLoad unit uses this interface for receiving read and write requests from
* the TensorGemm unit.
*/
class TensorClient(tensorType: String = "none")(implicit p: Parameters)
extends TensorParams(tensorType) {
class TensorClient(tensorType: String = "none")
(implicit p: Parameters) extends TensorParams(tensorType) {
val rd = new Bundle {
val idx = Flipped(ValidIO(UInt(memAddrBits.W)))
val data = ValidIO(
......@@ -135,8 +134,8 @@ class TensorClient(tensorType: String = "none")(implicit p: Parameters)
* is based on the TensorMaster interface, which means this is an input. This interface
* is used on datapath only module such MatrixVectorCore or AluVector.
*/
class TensorMasterData(tensorType: String = "none")(implicit p: Parameters)
extends TensorParams(tensorType) {
class TensorMasterData(tensorType: String = "none")
(implicit p: Parameters) extends TensorParams(tensorType) {
val data = Flipped(
ValidIO(Vec(tensorLength, Vec(tensorWidth, UInt(tensorElemBits.W)))))
override def cloneType =
......@@ -149,8 +148,8 @@ class TensorMasterData(tensorType: String = "none")(implicit p: Parameters)
* is based on the TensorClient interface, which means this is an output. This interface
* is used on datapath only module such MatrixVectorCore or AluVector.
*/
class TensorClientData(tensorType: String = "none")(implicit p: Parameters)
extends TensorParams(tensorType) {
class TensorClientData(tensorType: String = "none")
(implicit p: Parameters) extends TensorParams(tensorType) {
val data = ValidIO(
Vec(tensorLength, Vec(tensorWidth, UInt(tensorElemBits.W))))
override def cloneType =
......@@ -158,8 +157,7 @@ class TensorClientData(tensorType: String = "none")(implicit p: Parameters)
}
/** TensorPadCtrl. Zero-padding controller for TensorLoad. */
class TensorPadCtrl(padType: String = "none", sizeFactor: Int = 1)
extends Module {
class TensorPadCtrl(padType: String = "none", sizeFactor: Int = 1) extends Module {
val errorMsg =
s"\n\n\n[VTA-ERROR] only YPad0, YPad1, XPad0, or XPad1 supported\n\n\n"
require(padType == "YPad0" || padType == "YPad1"
......@@ -233,9 +231,7 @@ class TensorPadCtrl(padType: String = "none", sizeFactor: Int = 1)
/** TensorDataCtrl. Data controller for TensorLoad. */
class TensorDataCtrl(tensorType: String = "none",
sizeFactor: Int = 1,
strideFactor: Int = 1)(implicit p: Parameters)
extends Module {
sizeFactor: Int = 1, strideFactor: Int = 1)(implicit p: Parameters) extends Module {
val mp = p(ShellKey).memParams
val io = IO(new Bundle {
val start = Input(Bool())
......
vta/hardware/chisel/src/main/scala/dpi/VTAHostDPI.scala
......@@ -78,8 +78,7 @@ class VTAHostDPI extends BlackBox with HasBlackBoxResource {
*
* Convert Host DPI to AXI for VTAShell
*/
class VTAHostDPIToAXI(debug: Boolean = false)(implicit p: Parameters)
extends Module {
class VTAHostDPIToAXI(debug: Boolean = false)(implicit p: Parameters) extends Module {
val io = IO(new Bundle {
val dpi = new VTAHostDPIClient
val axi = new AXILiteMaster(p(ShellKey).hostParams)
......
vta/hardware/chisel/src/main/scala/dpi/VTAMemDPI.scala
......@@ -75,8 +75,7 @@ class VTAMemDPI extends BlackBox with HasBlackBoxResource {
setResource("/verilog/VTAMemDPI.v")
}
class VTAMemDPIToAXI(debug: Boolean = false)(implicit p: Parameters)
extends Module {
class VTAMemDPIToAXI(debug: Boolean = false)(implicit p: Parameters) extends Module {
val io = IO(new Bundle {
val dpi = new VTAMemDPIMaster
val axi = new AXIClient(p(ShellKey).memParams)
......
vta/hardware/chisel/src/main/scala/shell/Configs.scala
......@@ -25,8 +25,7 @@ import vta.util.config._
import vta.interface.axi._
/** PynqConfig. Shell configuration for Pynq */
class PynqConfig
extends Config((site, here, up) => {
class PynqConfig extends Config((site, here, up) => {
case ShellKey =>
ShellParams(
hostParams = AXIParams(coherent = false,
......@@ -42,11 +41,10 @@ class PynqConfig
vcrParams = VCRParams(),
vmeParams = VMEParams()
)
})
})
/** F1Config. Shell configuration for F1 */
class F1Config
extends Config((site, here, up) => {
class F1Config extends Config((site, here, up) => {
case ShellKey =>
ShellParams(
hostParams = AXIParams(coherent = false,
......@@ -62,11 +60,10 @@ class F1Config
vcrParams = VCRParams(),
vmeParams = VMEParams()
)
})
})
/** De10Config. Shell configuration for De10 */
class De10Config
extends Config((site, here, up) => {
class De10Config extends Config((site, here, up) => {
case ShellKey =>
ShellParams(
hostParams =
......@@ -80,4 +77,4 @@ class De10Config
vcrParams = VCRParams(),
vmeParams = VMEParams()
)
})
})
vta/hardware/chisel/src/main/scala/shell/VCR.scala
......@@ -38,8 +38,7 @@ case class VCRParams() {
}
/** VCRBase. Parametrize base class. */
abstract class VCRBase(implicit p: Parameters)
extends GenericParameterizedBundle(p)
abstract class VCRBase(implicit p: Parameters) extends GenericParameterizedBundle(p)
/** VCRMaster.
*
......
vta/hardware/chisel/src/main/scala/shell/VME.scala
......@@ -40,8 +40,7 @@ case class VMEParams() {
}
/** VMEBase. Parametrize base class. */
abstract class VMEBase(implicit p: Parameters)
extends GenericParameterizedBundle(p)
abstract class VMEBase(implicit p: Parameters) extends GenericParameterizedBundle(p)
/** VMECmd.
*
......
vta/hardware/chisel/src/main/scala/util/GenericParameterizedBundle.scala
......@@ -23,8 +23,8 @@ package vta.util.genericbundle
import chisel3._
abstract class GenericParameterizedBundle[+T <: Object](val params: T)
extends Bundle {
abstract class GenericParameterizedBundle[+T <: Object]
(val params: T) extends Bundle {
override def cloneType = {
try {
this.getClass.getConstructors.head
......
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