/* Generated by Yosys 0.7 (git sha1 UNKNOWN, clang 3.4.2 -fPIC -Os) */

(* src = "top.v:1" *)
module top(clk, rst, count);
  (* src = "top.v:3" *)
  wire _0_;
  wire _1_;
  wire _2_;
  (* src = "top.v:1" *)
  input clk;
  (* src = "top.v:1" *)
  output count;
  (* src = "top.v:1" *)
  input rst;
  INV_X2X2 _3_ (
    .A(rst),
    .Y(_1_)
  );
  TIEHL _4_ (
    .tiehi(_2_)
  );
  DFFARAS_X2X2 _5_ (
    .CLK(clk),
    .D(_0_),
    .Q(count),
    .QN(_0_),
    .RN(_1_),
    .SN(_2_)
  );
endmodule
