/* AUTOMATICALLY GENERATED VERILOG-2001 SOURCE CODE.
** GENERATED BY CLASH 0.99. DO NOT MODIFY.
*/
module TopEntity
    ( // Inputs
      input  CLOCK // clock
    , input  RESET // asynchronous reset: active high
    , input  RX
    , input  SDO

      // Outputs
    , output wire  MANRST
    , output wire  TX
    , output wire [6:0] LED
    , output wire  CLK_OUT
    , output wire [2:0] C1
    , output wire [2:0] C2
    , output wire [3:0] DATA
    , output wire  LAT
    , output wire  OE
    , output wire  CS_AG
    , output wire  CS_M
    , output wire  CS_ALT
    , output wire  SDI
    , output wire  SCK
    , output wire  INT
    , output wire  DRDY_M
    , output wire  PM1_0
    , output wire  PM1_2
    , output wire  PM1_5
    , output wire  PM1_7
    );
  wire  c$ds1_app_arg;
  wire  b;
  wire [1:0] ds1;
  wire  a;
  reg [26:0] c$initalCounter_app_arg;
  reg  c$tup_case_alt;
  wire [26:0] initalCounter;
  wire  shot;
  wire [75:0] enemies;
  wire [7:0] rotation;
  wire [3:0] x;
  wire [8:0] scrut3;
  wire [17:0] scrut2;
  wire [26:0] scrut1;
  wire [35:0] scrut;
  wire [0:0] scrut3_0;
  wire [1:0] scrut2_0;
  wire [2:0] scrut1_0;
  wire [8:0] c$ds1_case_scrut;
  wire [8:0] c$ds1_case_scrut_0;
  wire [8:0] c$ds1_case_scrut_1;
  wire [8:0] c$ds1_case_scrut_2;
  wire [7:0] a4;
  wire  r4;
  wire [7:0] a3;
  wire  ramreqsine;
  wire [7:0] a2;
  wire  r2;
  wire [7:0] a1;
  wire  r1;
  wire [18:0] result_0;
  wire [7:0] c$app_arg;
  wire [7:0] c$app_arg_0;
  wire [18:0] result_1;
  reg [7:0] result_2;
  reg [2:0] result_3;
  reg [7:0] result_4;
  wire [7:0] c$o_angle_case_alt;
  wire [7:0] c$o_angle_case_alt_0;
  wire [2:0] c$o_color_case_alt;
  wire [2:0] c$o_color_case_alt_0;
  wire [7:0] \c$_INTERNAL_.o_radius_case_alt ;
  reg [7:0] \c$_INTERNAL_.o_radius_case_alt_0 ;
  wire [7:0] \c$_INTERNAL_.o_radius_case_alt_1 ;
  wire [7:0] \c$_INTERNAL_.o_radius_case_alt_2 ;
  wire [1:0] bs;
  wire [1:0] bs_0;
  wire [2:0] bs_1;
  wire [7:0] c_radius;
  wire [7:0] dt;
  wire [7:0] dt_0;
  wire [2:0] dt_1;
  wire [6:0] result_5;
  wire [7:0] dt_2;
  wire  c$cout_app_arg;
  wire  c$cout_app_arg_0;
  wire [1:0] cin;
  reg [0:0] c$cin_app_arg;
  reg [0:0] c$cin_app_arg_0;
  wire [0:0] c$cout_app_arg_1;
  wire  c$cout_app_arg_2;
  wire  clock;
  wire [18:0] enemies4;
  wire [18:0] result_6;
  wire [7:0] c$app_arg_1;
  wire [7:0] c$app_arg_2;
  wire [18:0] result_7;
  reg [7:0] result_8;
  reg [2:0] result_9;
  reg [7:0] result_10;
  wire [7:0] c$o_angle_case_alt_1;
  wire [7:0] c$o_angle_case_alt_2;
  wire [2:0] c$o_color_case_alt_1;
  wire [2:0] c$o_color_case_alt_2;
  wire [7:0] \c$_INTERNAL_.o_radius_case_alt_3 ;
  reg [7:0] \c$_INTERNAL_.o_radius_case_alt_4 ;
  wire [7:0] \c$_INTERNAL_.o_radius_case_alt_5 ;
  wire [7:0] \c$_INTERNAL_.o_radius_case_alt_6 ;
  wire [1:0] bs_2;
  wire [1:0] bs_3;
  wire [2:0] bs_4;
  wire [7:0] c_radius_0;
  wire [7:0] dt_3;
  wire [7:0] dt_4;
  wire [2:0] dt_5;
  wire [6:0] result_11;
  wire [7:0] dt_6;
  wire  c$cout_app_arg_3;
  wire  c$cout_app_arg_4;
  wire [1:0] cin_0;
  reg [0:0] c$cin_app_arg_1;
  reg [0:0] c$cin_app_arg_2;
  wire [0:0] c$cout_app_arg_5;
  wire  c$cout_app_arg_6;
  wire  clock_0;
  wire [37:0] enemies5;
  wire [18:0] result_12;
  wire [7:0] c$app_arg_3;
  wire [7:0] c$app_arg_4;
  wire [18:0] result_13;
  reg [7:0] result_14;
  reg [2:0] result_15;
  reg [7:0] result_16;
  wire [7:0] c$o_angle_case_alt_3;
  wire [7:0] c$o_angle_case_alt_4;
  wire [2:0] c$o_color_case_alt_3;
  wire [2:0] c$o_color_case_alt_4;
  wire [7:0] \c$_INTERNAL_.o_radius_case_alt_7 ;
  reg [7:0] \c$_INTERNAL_.o_radius_case_alt_8 ;
  wire [7:0] \c$_INTERNAL_.o_radius_case_alt_9 ;
  wire [7:0] \c$_INTERNAL_.o_radius_case_alt_10 ;
  wire [1:0] bs_5;
  wire [1:0] bs_6;
  wire [2:0] bs_7;
  wire [7:0] c_radius_1;
  wire [7:0] dt_7;
  wire [7:0] dt_8;
  wire [2:0] dt_9;
  wire [6:0] result_17;
  wire [7:0] dt_10;
  wire  c$cout_app_arg_7;
  wire  c$cout_app_arg_8;
  wire [1:0] cin_1;
  reg [0:0] c$cin_app_arg_3;
  reg [0:0] c$cin_app_arg_4;
  wire [0:0] c$cout_app_arg_9;
  wire  c$cout_app_arg_10;
  wire  clock_1;
  wire [91:0] result_18;
  reg [35:0] result_19;
  reg [7:0] result_20;
  reg [2:0] result_21;
  reg [3:0] result_22;
  reg [23:0] result_23;
  reg [9:0] result_24;
  reg  result_25;
  reg [2:0] result_26;
  reg [2:0] result_27;
  wire [35:0] c$o_resets_case_alt;
  reg [35:0] c$o_resets_case_alt_0;
  wire [7:0] \c$_INTERNAL_.o_newangle_case_alt ;
  wire [7:0] \c$_INTERNAL_.o_newangle_case_alt_0 ;
  wire [2:0] c$o_scorecolor_case_alt;
  wire [2:0] c$o_scorecolor_case_alt_0;
  wire [3:0] c$o_moveticks_case_alt;
  reg [3:0] c$o_moveticks_case_alt_0;
  wire [23:0] \c$_INTERNAL_.o_movementclock_case_alt ;
  wire [23:0] \c$_INTERNAL_.o_movementclock_case_alt_0 ;
  wire [9:0] \c$_INTERNAL_.o_score_case_alt ;
  reg [9:0] \c$_INTERNAL_.o_score_case_alt_0 ;
  wire  c$o_gameover_case_alt;
  reg  c$o_gameover_case_alt_0;
  wire [2:0] \c$_INTERNAL_.o_counter_case_alt ;
  wire [2:0] \c$_INTERNAL_.o_counter_case_alt_0 ;
  wire [2:0] \c$_INTERNAL_.o_shotCounter_case_alt ;
  reg [2:0] \c$_INTERNAL_.o_shotCounter_case_alt_0 ;
  wire [35:0] c$o_resets_case_alt_1;
  reg [35:0] c$o_resets_case_alt_2;
  wire [3:0] c$o_moveticks_case_alt_1;
  wire [3:0] c$o_moveticks_case_alt_2;
  wire [9:0] \c$_INTERNAL_.o_score_case_alt_1 ;
  wire [9:0] \c$_INTERNAL_.o_score_case_alt_2 ;
  wire  c$o_gameover_case_alt_1;
  wire  c$o_gameover_case_alt_2;
  wire [2:0] \c$_INTERNAL_.o_shotCounter_case_alt_1 ;
  reg [2:0] \c$_INTERNAL_.o_shotCounter_case_alt_2 ;
  wire [3:0] bs_8;
  wire [35:0] c$o_resets_case_alt_3;
  wire [35:0] c$o_resets_case_alt_4;
  wire [1:0] bs_9;
  wire [1:0] bs_10;
  wire [2:0] bs_11;
  wire [1:0] bs_12;
  wire [2:0] bs_13;
  wire [2:0] bs_14;
  wire [1:0] bs_15;
  wire [3:0] bs_16;
  wire [2:0] \c$_INTERNAL_.o_shotCounter_case_alt_3 ;
  wire [2:0] \c$_INTERNAL_.o_shotCounter_case_alt_4 ;
  wire [2:0] c_counter;
  wire [2:0] c_shotCounter;
  wire [9:0] c_score;
  wire [23:0] c_movementclock;
  wire [7:0] c_newangle;
  wire [35:0] dt_11;
  wire [2:0] dt_12;
  wire [3:0] dt_13;
  wire  dt_14;
  wire [7:0] dt_15;
  wire [2:0] dt_16;
  reg [2:0] result_28;
  reg [23:0] c$dt_case_alt;
  wire [24:0] result_29;
  wire [35:0] dt_17;
  wire  c$dt_case_scrut;
  wire [10:0] ds1_0;
  wire [9:0] dt_18;
  wire [7:0] r1_0;
  wire [7:0] \r2' ;
  wire [7:0] \r4' ;
  reg [2:0] result_30;
  wire [7:0] \r3' ;
  reg [2:0] c$case_alt;
  reg [2:0] c$case_alt_0;
  reg [3:0] c$dt_case_alt_0;
  wire [12:0] c;
  reg [10:0] c$dt_app_arg;
  reg [35:0] dt_19;
  wire [18:0] c$dt_case_scrut_0;
  wire [7:0] r2_0;
  wire [7:0] r3;
  wire [2:0] c3;
  wire [7:0] r4_0;
  wire [2:0] c4;
  wire [2:0] dt_20;
  wire  w26;
  wire  w30;
  wire [18:0] c$dt_case_scrut_1;
  wire [18:0] c$dt_case_scrut_2;
  wire [18:0] c$dt_case_scrut_3;
  reg [10:0] c$tupIn;
  wire  w29;
  wire [56:0] scrut_0;
  wire [37:0] scrut1_1;
  wire [18:0] scrut2_1;
  reg  c$dt_app_arg_0;
  wire  w11;
  wire [2:0] c1;
  wire [2:0] c2;
  reg  c$dt_app_arg_1;
  wire  w22;
  wire  w16;
  wire  c$w26_app_arg;
  wire  c$w11_app_arg;
  reg  c$dt_app_arg_2;
  wire [4:0] cin_2;
  wire  w10;
  wire  w9;
  wire  \_INTERNAL_.w6 ;
  wire  c$w16_app_arg;
  reg  c$dt_case_alt_1;
  wire  w8;
  wire  w13;
  wire  c$w29_app_arg;
  wire  c$w26_app_arg_0;
  reg [0:0] result_31;
  reg  c$dt_case_alt_2;
  wire  w15;
  wire  \_INTERNAL_.w7 ;
  wire  w20;
  wire  c$w13_app_arg;
  wire  \c$_INTERNAL_.w6_app_arg ;
  reg [0:0] c$cin_app_arg_5;
  wire  w12;
  wire  c$cout_app_arg_11;
  reg [0:0] c$cin_app_arg_6;
  reg  result_32;
  wire  w18;
  wire  w19;
  reg [0:0] result_33;
  reg [0:0] result_34;
  reg  result_35;
  wire [7:0] c$app_arg_5;
  wire  w1;
  wire  \c$_INTERNAL_.w7_app_arg ;
  wire  b_0;
  wire  b_1;
  reg [7:0] c$triggerresetall1_$jOut_app_arg;
  wire  c$w1_app_arg;
  wire [18:0] c$angle_case_scrut;
  wire [0:0] c$cout_app_arg_12;
  wire signed [63:0] wild;
  wire  w32;
  wire  w21;
  wire  w33;
  wire [0:0] c$cout_app_arg_13;
  wire [56:0] enemies6;
  wire [18:0] result_36;
  wire [7:0] c$app_arg_6;
  wire [7:0] c$app_arg_7;
  wire [18:0] result_37;
  reg [7:0] result_38;
  reg [2:0] result_39;
  reg [7:0] result_40;
  wire [7:0] c$o_angle_case_alt_5;
  wire [7:0] c$o_angle_case_alt_6;
  wire [2:0] c$o_color_case_alt_5;
  wire [2:0] c$o_color_case_alt_6;
  wire [7:0] \c$_INTERNAL_.o_radius_case_alt_11 ;
  reg [7:0] \c$_INTERNAL_.o_radius_case_alt_12 ;
  wire [7:0] \c$_INTERNAL_.o_radius_case_alt_13 ;
  wire [7:0] \c$_INTERNAL_.o_radius_case_alt_14 ;
  wire [1:0] bs_17;
  wire [1:0] bs_18;
  wire [2:0] bs_19;
  wire [7:0] c_radius_2;
  wire [7:0] dt_21;
  wire [7:0] dt_22;
  wire [2:0] dt_23;
  wire [6:0] result_41;
  wire [7:0] dt_24;
  wire  c$cout_app_arg_14;
  wire  c$cout_app_arg_15;
  wire [1:0] cin_3;
  reg [0:0] c$cin_app_arg_7;
  reg [0:0] c$cin_app_arg_8;
  wire [0:0] c$cout_app_arg_16;
  wire  c$cout_app_arg_17;
  wire  clock_2;
  wire [75:0] enemies7;
  wire [89:0] result_42;
  wire [12:0] result_43;
  wire [36:0] result_44;
  reg [4:0] result_45;
  reg [4:0] result_46;
  reg [2:0] result_47;
  reg [2:0] result_48;
  reg [7:0] result_49;
  reg [4:0] result_50;
  reg [4:0] result_51;
  reg [2:0] result_52;
  wire [4:0] c$o_bxcoord_case_alt;
  wire [4:0] c$o_bxcoord_case_alt_0;
  wire [4:0] c$o_bycoord_case_alt;
  wire [4:0] c$o_bycoord_case_alt_0;
  wire [2:0] c$o_color_case_alt_7;
  reg [2:0] c$o_color_case_alt_8;
  wire [2:0] \c$_INTERNAL_.o_tmpcolor_case_alt ;
  reg [2:0] \c$_INTERNAL_.o_tmpcolor_case_alt_0 ;
  wire [7:0] \c$_INTERNAL_.o_tmpdist_case_alt ;
  reg [7:0] \c$_INTERNAL_.o_tmpdist_case_alt_0 ;
  wire [4:0] \c$_INTERNAL_.o_xcoord_case_alt ;
  wire [4:0] \c$_INTERNAL_.o_xcoord_case_alt_0 ;
  wire [4:0] \c$_INTERNAL_.o_ycoord_case_alt ;
  wire [4:0] \c$_INTERNAL_.o_ycoord_case_alt_0 ;
  wire [2:0] \c$_INTERNAL_.o_counter_case_alt_1 ;
  wire [2:0] \c$_INTERNAL_.o_counter_case_alt_2 ;
  wire [2:0] c$o_color_case_alt_9;
  wire [2:0] c$o_color_case_alt_10;
  wire [2:0] \c$_INTERNAL_.o_tmpcolor_case_alt_1 ;
  wire [2:0] \c$_INTERNAL_.o_tmpcolor_case_alt_2 ;
  wire [7:0] \c$_INTERNAL_.o_tmpdist_case_alt_1 ;
  wire [7:0] \c$_INTERNAL_.o_tmpdist_case_alt_2 ;
  wire [1:0] bs_20;
  wire [1:0] bs_21;
  wire [2:0] bs_22;
  wire [2:0] bs_23;
  wire [2:0] bs_24;
  wire [1:0] bs_25;
  wire [1:0] bs_26;
  wire [1:0] bs_27;
  wire [7:0] c_tmpdist;
  wire [4:0] c_xcoord;
  wire [4:0] c_ycoord;
  wire [2:0] c_counter_0;
  wire [2:0] c_tmpcolor;
  wire [4:0] dt_25;
  wire [4:0] dt_26;
  wire [4:0] dt_27;
  wire [4:0] dt_28;
  wire [2:0] dt_29;
  wire [5:0] dt_30;
  wire [7:0] dt_31;
  wire [4:0] dt_32;
  wire [4:0] dt_33;
  wire [2:0] dt_34;
  wire [18:0] result_53;
  wire  w13_0;
  wire  c$w13_app_arg_0;
  wire [5:0] cin_4;
  wire [0:0] \c$_INTERNAL_.cout_app_arg ;
  reg [0:0] result_54;
  wire  w11_0;
  reg [0:0] result_55;
  wire [2:0] w17;
  wire [0:0] \c$_INTERNAL_.cout_app_arg_0 ;
  reg [0:0] result_56;
  wire  b_2;
  reg  result_57;
  wire  w12_0;
  reg [0:0] result_58;
  wire  b_3;
  wire [7:0] relativ_angle;
  reg  result_59;
  reg  \$j1 ;
  reg  c$case_alt_1;
  wire  c$b_case_scrut;
  reg [0:0] result_60;
  reg [0:0] result_61;
  wire  b_4;
  reg [7:0] c$$sincmod3_$jOut_app_arg;
  wire  b_5;
  wire  b_6;
  wire [18:0] c$eta14_case_scrut;
  wire signed [63:0] wild_0;
  wire  w7;
  wire [0:0] \c$_INTERNAL_.cout_app_arg_1 ;
  wire [0:0] \c$_INTERNAL_.cout_app_arg_2 ;
  wire  \c$_INTERNAL_.cout_app_arg_3 ;
  wire [12:0] result_62;
  wire [57:0] result_63;
  reg [2:0] result_64;
  reg [2:0] result_65;
  reg [2:0] result_66;
  reg [4:0] result_67;
  reg [4:0] result_68;
  reg [7:0] result_69;
  reg [7:0] result_70;
  reg [4:0] result_71;
  reg [4:0] result_72;
  reg [7:0] result_73;
  reg [4:0] result_74;
  wire [2:0] c$o_color_case_alt_11;
  reg [2:0] c$o_color_case_alt_12;
  wire [2:0] \c$_INTERNAL_.o_tmpcolor_case_alt_3 ;
  reg [2:0] \c$_INTERNAL_.o_tmpcolor_case_alt_4 ;
  wire [2:0] \c$_INTERNAL_.o_buffercolor_case_alt ;
  wire [2:0] \c$_INTERNAL_.o_buffercolor_case_alt_0 ;
  wire [4:0] c$o_outy_case_alt;
  wire [4:0] c$o_outy_case_alt_0;
  wire [4:0] c$o_outx_case_alt;
  wire [4:0] c$o_outx_case_alt_0;
  wire [7:0] c$o_ramreqsine_case_alt;
  wire [7:0] c$o_ramreqsine_case_alt_0;
  wire [7:0] c$o_ramreqcosine_case_alt;
  wire [7:0] c$o_ramreqcosine_case_alt_0;
  wire [4:0] \c$_INTERNAL_.o_ycoord_case_alt_1 ;
  wire [4:0] \c$_INTERNAL_.o_ycoord_case_alt_2 ;
  wire [4:0] \c$_INTERNAL_.o_xcoord_case_alt_1 ;
  wire [4:0] \c$_INTERNAL_.o_xcoord_case_alt_2 ;
  wire [7:0] \c$_INTERNAL_.o_bufferdradius_case_alt ;
  wire [7:0] \c$_INTERNAL_.o_bufferdradius_case_alt_0 ;
  wire [4:0] \c$_INTERNAL_.o_counter_case_alt_3 ;
  wire [4:0] \c$_INTERNAL_.o_counter_case_alt_4 ;
  wire [2:0] c$o_color_case_alt_13;
  wire [2:0] c$o_color_case_alt_14;
  wire [2:0] \c$_INTERNAL_.o_tmpcolor_case_alt_5 ;
  wire [2:0] \c$_INTERNAL_.o_tmpcolor_case_alt_6 ;
  wire [2:0] bs_28;
  wire [2:0] bs_29;
  wire [1:0] bs_30;
  wire [1:0] bs_31;
  wire [1:0] bs_32;
  wire [1:0] bs_33;
  wire [1:0] bs_34;
  wire [1:0] bs_35;
  wire [1:0] bs_36;
  wire [1:0] bs_37;
  wire [1:0] bs_38;
  wire [4:0] c_ycoord_0;
  wire [4:0] c_xcoord_0;
  wire [7:0] c_bufferdradius;
  wire [4:0] c_counter_1;
  wire [2:0] c_buffercolor;
  wire [2:0] dt_35;
  wire [5:0] dt_36;
  wire [5:0] dt_37;
  wire [4:0] dt_38;
  wire [4:0] dt_39;
  wire [4:0] dt_40;
  wire [4:0] dt_41;
  wire [7:0] dt_42;
  wire [7:0] dt_43;
  wire [7:0] dt_44;
  wire [7:0] w30_0;
  wire [2:0] c_tmpcolor_0;
  wire [4:0] dt_45;
  wire [4:0] dt_46;
  wire [4:0] dt_47;
  wire [23:0] result_75;
  wire [18:0] c$dt_case_scrut_4;
  wire  w11_1;
  wire signed [63:0] wild_1;
  wire  c$w11_app_arg_0;
  wire [4:0] cin_5;
  reg [0:0] result_76;
  reg [0:0] result_77;
  reg [0:0] result_78;
  wire  b_7;
  reg  result_79;
  reg [0:0] result_80;
  reg [0:0] result_81;
  wire  b_8;
  wire [4:0] c$b_app_arg;
  reg  \$j ;
  wire  w8_0;
  wire  b_9;
  wire  b_10;
  wire [4:0] c$b_app_arg_0;
  wire signed [15:0] r;
  wire [15:0] c$app_arg_8;
  wire [14:0] \r' ;
  reg signed [14:0] c$case_alt_2;
  reg signed [14:0] result_82;
  wire signed [15:0] r_0;
  wire [15:0] c$app_arg_9;
  wire [14:0] \c$r'_0 ;
  reg signed [14:0] c$case_alt_3;
  reg signed [14:0] result_83;
  reg signed [14:0] result_84;
  reg signed [14:0] c$case_alt_4;
  wire [9:0] rL;
  wire [19:0] rR;
  wire [29:0] ds3;
  wire [10:0] x_0;
  wire signed [29:0] c$ds3_app_arg;
  reg signed [14:0] result_85;
  reg signed [14:0] c$case_alt_5;
  wire [9:0] rL_0;
  wire [19:0] rR_0;
  wire [29:0] ds3_0;
  wire [10:0] x_1;
  wire signed [29:0] c$ds3_app_arg_0;
  wire signed [30:0] c$case_scrut;
  wire signed [14:0] c$case_alt_6;
  reg signed [14:0] c$case_alt_7;
  reg signed [14:0] c$case_alt_8;
  wire signed [30:0] shiftedR;
  reg signed [14:0] result_86;
  wire signed [30:0] ds;
  wire [0:0] \c$_INTERNAL_.cout_app_arg_4 ;
  wire [0:0] \c$_INTERNAL_.cout_app_arg_5 ;
  wire  \c$_INTERNAL_.cout_app_arg_6 ;
  wire  \c$_INTERNAL_.cout_app_arg_7 ;
  wire signed [14:0] result_87;
  reg [14:0] bv;
  wire signed [63:0] wild_2;
  wire signed [14:0] result_88;
  reg [14:0] bv_0;
  wire signed [63:0] wild_3;
  wire [7:0] a_0;
  wire [7:0] a_1;
  wire [12:0] result_89;
  wire [22:0] result_90;
  reg [2:0] result_91;
  reg [4:0] result_92;
  reg [4:0] result_93;
  reg [4:0] result_94;
  reg [4:0] result_95;
  wire [2:0] c$o_actcolor_case_alt;
  reg [2:0] c$o_actcolor_case_alt_0;
  wire [4:0] c$o_bxcoord_case_alt_1;
  wire [4:0] c$o_bxcoord_case_alt_2;
  wire [4:0] c$o_bycoord_case_alt_1;
  wire [4:0] c$o_bycoord_case_alt_2;
  wire [4:0] \c$_INTERNAL_.o_xcoord_case_alt_3 ;
  wire [4:0] \c$_INTERNAL_.o_xcoord_case_alt_4 ;
  wire [4:0] \c$_INTERNAL_.o_ycoord_case_alt_3 ;
  wire [4:0] \c$_INTERNAL_.o_ycoord_case_alt_4 ;
  wire [2:0] c$o_actcolor_case_alt_1;
  reg [2:0] c$o_actcolor_case_alt_2;
  wire [3:0] bs_39;
  wire [2:0] c$o_actcolor_case_alt_3;
  wire [2:0] c$o_actcolor_case_alt_4;
  wire [1:0] bs_40;
  wire [1:0] bs_41;
  wire [1:0] bs_42;
  wire [1:0] bs_43;
  wire [2:0] dt_48;
  wire [4:0] dt_49;
  wire [4:0] dt_50;
  wire [4:0] dt_51;
  wire [4:0] dt_52;
  wire [4:0] dt_53;
  wire [4:0] dt_54;
  wire [4:0] c_xcoord_1;
  wire [4:0] c_ycoord_1;
  wire [11:0] result_96;
  wire [2:0] dt_55;
  wire  c$cout_app_arg_18;
  wire [4:0] cin_6;
  reg [0:0] c$cin_app_arg_9;
  reg [0:0] result_97;
  reg [0:0] result_98;
  wire  b_11;
  reg [0:0] result_99;
  reg [0:0] result_100;
  wire  b_12;
  wire  b_13;
  wire  b_14;
  wire  c$cout_app_arg_19;
  wire  w9_0;
  wire  c$w9_app_arg;
  wire [2:0] score_color;
  wire [9:0] score;
  wire  gameover;
  wire [1:0] gamemode;
  reg [12:0] result_101;
  wire [12:0] c$o_outpoint_case_alt;
  reg [12:0] c$o_outpoint_case_alt_0;
  wire [12:0] c$o_outpoint_case_alt_1;
  reg [12:0] c$o_outpoint_case_alt_2;
  wire [12:0] c$o_outpoint_case_alt_3;
  wire [12:0] c$o_outpoint_case_alt_4;
  wire [3:0] result_102;
  wire [12:0] dt_56;
  wire [12:0] dt_57;
  wire [3:0] result_103;
  wire  w5;
  wire  w6;
  wire [3:0] cin_7;
  reg [0:0] c$cin_app_arg_10;
  reg [0:0] result_104;
  reg [0:0] result_105;
  reg [0:0] result_106;
  reg  b_15;
  reg  b_16;
  reg  b_17;
  reg  result_107;
  wire [15:0] result_108;
  wire [51:0] result_109;
  reg  result_110;
  reg [2:0] result_111;
  reg [2:0] result_112;
  reg [2:0] result_113;
  reg [13:0] result_114;
  reg [9:0] result_115;
  reg [3:0] result_116;
  reg  result_117;
  reg  result_118;
  reg [4:0] result_119;
  reg [6:0] result_120;
  wire  c$o_bufferPin_case_alt;
  reg  c$o_bufferPin_case_alt_0;
  wire [2:0] c$o_color_case_alt_15;
  wire [2:0] c$o_color_case_alt_16;
  wire [2:0] c$o_color1_case_alt;
  wire [2:0] c$o_color1_case_alt_0;
  wire [2:0] c$o_color2_case_alt;
  wire [2:0] c$o_color2_case_alt_0;
  wire [13:0] c$o_ramwrite_case_alt;
  reg [13:0] c$o_ramwrite_case_alt_0;
  wire [9:0] c$o_rampos_case_alt;
  reg [9:0] c$o_rampos_case_alt_0;
  wire [3:0] \c$_INTERNAL_.o_coordy_case_alt ;
  wire [3:0] \c$_INTERNAL_.o_coordy_case_alt_0 ;
  wire  c$o_extclock_case_alt;
  reg  c$o_extclock_case_alt_0;
  wire  c$o_driverPin_case_alt;
  wire  c$o_driverPin_case_alt_0;
  wire [4:0] \c$_INTERNAL_.o_coordx_case_alt ;
  wire [4:0] \c$_INTERNAL_.o_coordx_case_alt_0 ;
  wire [6:0] \c$_INTERNAL_.o_waitcounter_case_alt ;
  wire [6:0] \c$_INTERNAL_.o_waitcounter_case_alt_0 ;
  wire  c$o_bufferPin_case_alt_1;
  wire  c$o_bufferPin_case_alt_2;
  wire [13:0] c$o_ramwrite_case_alt_1;
  wire [13:0] c$o_ramwrite_case_alt_2;
  wire [9:0] c$o_rampos_case_alt_1;
  reg [9:0] c$o_rampos_case_alt_2;
  wire  c$o_extclock_case_alt_1;
  wire  c$o_extclock_case_alt_2;
  wire [2:0] bs_44;
  wire [1:0] bs_45;
  wire [1:0] bs_46;
  wire [1:0] bs_47;
  wire [2:0] bs_48;
  wire [3:0] bs_49;
  wire [9:0] c$o_rampos_case_alt_3;
  wire [9:0] c$o_rampos_case_alt_4;
  wire [1:0] bs_50;
  wire [2:0] bs_51;
  wire [1:0] bs_52;
  wire [1:0] bs_53;
  wire [1:0] bs_54;
  wire [4:0] c_coordx;
  wire [6:0] c_waitcounter;
  wire [3:0] c_coordy;
  wire  dt_58;
  wire [2:0] dt_59;
  wire [2:0] dt_60;
  wire [2:0] dt_61;
  wire [2:0] dt_62;
  wire [13:0] dt_63;
  wire [9:0] dt_64;
  wire [3:0] dt_65;
  wire  dt_66;
  wire  dt_67;
  wire [3:0] w23;
  wire [9:0] dt_68;
  wire [4:0] dt_69;
  wire [6:0] dt_70;
  wire [9:0] c$dt_app_arg_3;
  wire [26:0] result_121;
  wire [13:0] dt_71;
  wire [9:0] dt_72;
  wire [9:0] c$dt_app_arg_4;
  wire [9:0] dt_73;
  wire  w129;
  wire  c$cout_app_arg_20;
  wire  \_INTERNAL_.w62 ;
  wire  c$w129_app_arg;
  wire [2:0] cin_8;
  wire  w106;
  wire  \_INTERNAL_.w61 ;
  wire  \c$_INTERNAL_.w6_0 ;
  wire  c$cout_app_arg_21;
  wire  w50;
  wire  w104;
  wire  w102;
  reg [0:0] result_122;
  wire  \c$_INTERNAL_.w7_0 ;
  wire  c$w104_app_arg;
  reg [0:0] result_123;
  reg [0:0] result_124;
  wire  b_18;
  wire  w101;
  wire  \_INTERNAL_.w28 ;
  wire  w90;
  wire  \c$_INTERNAL_.w61_app_arg ;
  wire  \c$_INTERNAL_.w61_app_arg_0 ;
  wire  b_19;
  wire  b_20;
  wire  w39;
  wire  \_INTERNAL_.w31 ;
  wire  \_INTERNAL_.w8 ;
  wire  \_INTERNAL_.w24 ;
  wire  \_INTERNAL_.w14 ;
  wire  \_INTERNAL_.w59 ;
  wire  w53;
  wire  w77;
  wire  c$cout_app_arg_22;
  wire  c$w101_app_arg;
  wire  c$w50_app_arg;
  wire  w48;
  wire  \_INTERNAL_.w19 ;
  wire  w116;
  wire  w57;
  wire  c$cout_app_arg_23;
  wire  c$w77_app_arg;
  wire  \c$_INTERNAL_.w6_app_arg_0 ;
  wire  c$w53_app_arg;
  wire  \c$_INTERNAL_.w59_app_arg ;
  wire  \c$_INTERNAL_.w14_app_arg ;
  wire  \c$_INTERNAL_.w14_app_arg_0 ;
  wire  w32_0;
  wire  w107;
  wire  \_INTERNAL_.w12 ;
  wire  \_INTERNAL_.w13 ;
  wire  \_INTERNAL_.w15 ;
  wire  \_INTERNAL_.w38 ;
  wire  \_INTERNAL_.w123 ;
  wire  w56;
  wire  w52;
  wire  w76;
  wire  \c$_INTERNAL_.w19_app_arg ;
  wire  c$w101_app_arg_0;
  wire  c$w48_app_arg;
  wire  c$w48_app_arg_0;
  wire  \_INTERNAL_.w35 ;
  wire  w99;
  wire  w10_0;
  wire  \_INTERNAL_.w87 ;
  wire  \_INTERNAL_.w29 ;
  wire  w69;
  wire  \_INTERNAL_.w9 ;
  wire  w45;
  wire  \_INTERNAL_.w5 ;
  wire  \_INTERNAL_.w4 ;
  wire  \_INTERNAL_.w18 ;
  wire  w37;
  wire  w74;
  wire  \c$_INTERNAL_.w7_app_arg_0 ;
  wire  \c$_INTERNAL_.w15_app_arg ;
  wire  \c$_INTERNAL_.w12_app_arg ;
  wire  \c$_INTERNAL_.w12_app_arg_0 ;
  wire  c$w107_app_arg;
  wire  \c$_INTERNAL_.w31_app_arg ;
  wire  w26_0;
  wire  w64;
  wire  w97;
  wire  \_INTERNAL_.w22 ;
  wire  \_INTERNAL_.w23 ;
  wire  w68;
  wire  w94;
  wire  w66;
  wire  w73;
  wire  w82;
  wire  c$w45_app_arg;
  wire  \c$_INTERNAL_.w87_app_arg ;
  wire  \c$_INTERNAL_.w87_app_arg_0 ;
  wire  w33_0;
  wire  w34;
  wire  \_INTERNAL_.w11 ;
  wire  \_INTERNAL_.w16 ;
  wire  w36;
  wire  w78;
  wire  c$w82_app_arg;
  wire  c$w76_app_arg;
  wire  c$w66_app_arg;
  wire  c$w94_app_arg;
  wire  \c$_INTERNAL_.w23_app_arg ;
  wire  w27;
  wire  \_INTERNAL_.w17 ;
  wire  \_INTERNAL_.w41 ;
  wire  w46;
  wire  w65;
  wire  c$w74_app_arg;
  wire  w40;
  wire  w85;
  wire  c$cout_app_arg_24;
  wire  \c$_INTERNAL_.w22_app_arg ;
  wire  w92;
  wire  w79;
  wire  w93;
  wire  w81;
  wire [0:0] c$cout_app_arg_25;
  wire  w58;
  wire [1:0] \$d(%,%)1 ;
  reg [2:0] result_125;
  reg  c$ds_app_arg;
  wire [13:0] wrM;
  reg [12:0] tup;
  wire signed [63:0] wild_4;
  wire signed [63:0] wild_5;
  wire [9:0] x_2;
  wire [9:0] x_3;
  wire [12:0] x_4;
  wire [16:0] result_126;
  wire [3:0] sensorOut;
  wire [1:0] result_127;
  wire  b_21;
  wire  b_22;
  reg  b_23;
  reg [0:0] result_128;
  reg [0:0] result_129;
  reg  b_24;
  reg [0:0] result_130;
  wire  b_25;
  reg [0:0] result_131;
  reg [0:0] result_132;
  wire  w7_0;
  wire [4:0] cin_9;
  wire  c$w9_app_arg_0;
  wire  w9_1;
  wire  dt_74;
  wire  dt_75;
  wire [5:0] cout;
  wire [2:0] bs_55;
  wire [2:0] bs_56;
  wire  c$o_shot_case_alt;
  wire  c$o_shot_case_alt_0;
  wire  c$o_reset_case_alt;
  wire  c$o_reset_case_alt_0;
  reg  c$o_shot_case_alt_1;
  wire  c$o_shot_case_alt_2;
  reg  c$o_reset_case_alt_1;
  wire  c$o_reset_case_alt_2;
  reg  result_133;
  reg  result_134;
  wire [1:0] result_135;
  wire [7:0] c$case_alt_9;
  wire  b_26;
  wire  b_27;
  wire  b_28;
  reg [0:0] result_136;
  reg [0:0] result_137;
  reg  b_29;
  reg [0:0] result_138;
  reg  b_30;
  reg [0:0] result_139;
  reg  b_31;
  reg [0:0] result_140;
  reg [0:0] result_141;
  wire [5:0] cin_10;
  wire  c$w9_app_arg_1;
  wire  c$w11_app_arg_1;
  wire  w8_1;
  wire  w9_2;
  wire  w10_1;
  wire  w11_2;
  wire [27:0] dt_76;
  wire signed [27:0] dt_77;
  wire signed [27:0] c$dt_app_arg_5;
  wire signed [27:0] dt_78;
  wire [7:0] dt_79;
  wire signed [27:0] c_internalRotation;
  wire [7:0] \_INTERNAL_.cout ;
  wire signed [27:0] c$dt_app_arg_6;
  wire [9:0] c_prescaler;
  wire [9:0] dt_80;
  wire [9:0] dt_81;
  wire signed [27:0] dt_82;
  wire [7:0] dt_83;
  wire [1:0] bs_57;
  wire signed [27:0] \c$_INTERNAL_.o_internalRotation_case_alt ;
  wire signed [27:0] \c$_INTERNAL_.o_internalRotation_case_alt_0 ;
  wire [3:0] bs_58;
  wire [1:0] bs_59;
  reg signed [27:0] \c$_INTERNAL_.o_internalRotation_case_alt_1 ;
  wire signed [27:0] \c$_INTERNAL_.o_internalRotation_case_alt_2 ;
  wire [9:0] \c$_INTERNAL_.o_prescaler_case_alt ;
  wire [9:0] \c$_INTERNAL_.o_prescaler_case_alt_0 ;
  reg signed [27:0] \c$_INTERNAL_.o_internalRotation_case_alt_3 ;
  wire signed [27:0] \c$_INTERNAL_.o_internalRotation_case_alt_4 ;
  wire [7:0] c$o_rotation_case_alt;
  wire [7:0] c$o_rotation_case_alt_0;
  reg [9:0] result_142;
  reg signed [27:0] result_143;
  reg [7:0] result_144;
  wire [45:0] result_145;
  wire [63:0] result_146;
  reg [23:0] result_147;
  reg [9:0] result_148;
  reg [1:0] result_149;
  reg signed [27:0] result_150;
  wire [23:0] \c$_INTERNAL_.o_reseter_case_alt ;
  wire [23:0] \c$_INTERNAL_.o_reseter_case_alt_0 ;
  wire [9:0] \c$_INTERNAL_.o_prescaler_case_alt_1 ;
  wire [9:0] \c$_INTERNAL_.o_prescaler_case_alt_2 ;
  wire [1:0] \c$_INTERNAL_.o_gamemode_case_alt ;
  reg [1:0] \c$_INTERNAL_.o_gamemode_case_alt_0 ;
  wire signed [27:0] \c$_INTERNAL_.o_rotation_case_alt ;
  reg signed [27:0] \c$_INTERNAL_.o_rotation_case_alt_0 ;
  wire [7:0] vs;
  wire [1:0] \c$_INTERNAL_.o_gamemode_case_alt_1 ;
  reg [1:0] \c$_INTERNAL_.o_gamemode_case_alt_2 ;
  wire signed [27:0] \c$_INTERNAL_.o_rotation_case_alt_1 ;
  wire signed [27:0] \c$_INTERNAL_.o_rotation_case_alt_2 ;
  wire [1:0] c_gamemode;
  wire [1:0] bs_60;
  wire [1:0] bs_61;
  wire [3:0] bs_62;
  wire [1:0] \c$_INTERNAL_.o_gamemode_case_alt_3 ;
  wire [1:0] \c$_INTERNAL_.o_gamemode_case_alt_4 ;
  wire [2:0] bs_63;
  wire [23:0] c_reseter;
  wire [9:0] c_prescaler_0;
  wire signed [27:0] c_rotation;
  wire [23:0] dt_84;
  wire [9:0] dt_85;
  wire [10:0] result_151;
  wire signed [27:0] dt_86;
  wire  w43;
  wire  w40_0;
  wire  w38;
  wire  w37_0;
  wire  w39_0;
  wire  w36_0;
  wire  w28;
  wire [8:0] cin_11;
  wire  \_INTERNAL_.w33 ;
  wire  c$w28_app_arg;
  wire  w23_0;
  wire  w27_0;
  reg [0:0] result_152;
  wire  c$w23_app_arg;
  reg [0:0] result_153;
  wire  b_32;
  wire  w16_0;
  wire  w12_1;
  wire  \c$_INTERNAL_.w15_0 ;
  reg [0:0] result_154;
  wire  b_33;
  wire  \_INTERNAL_.w20 ;
  wire  w13_1;
  wire  c$w27_app_arg;
  wire  \c$_INTERNAL_.w33_app_arg ;
  wire  c$w12_app_arg;
  reg [0:0] result_155;
  reg  b_34;
  wire  w10_2;
  reg [0:0] result_156;
  reg  b_35;
  wire  \c$_INTERNAL_.w18_0 ;
  wire  c$w27_app_arg_0;
  wire  \c$_INTERNAL_.w33_app_arg_0 ;
  wire  \c$_INTERNAL_.w15_app_arg_0 ;
  reg [0:0] result_157;
  reg  b_36;
  reg [0:0] result_158;
  wire  b_37;
  wire  \c$_INTERNAL_.w18_app_arg ;
  reg [0:0] result_159;
  reg [0:0] result_160;
  wire  b_38;
  wire  b_39;
  wire  b_40;
  wire [1:0] result_161;
  wire  c$tup_app_arg;
  wire  c$tup_app_arg_0;
  wire  c$tup_app_arg_1;
  wire  c$tup_app_arg_2;
  wire [17:0] spiOutput;
  wire [17:0] c$ds1_app_arg_0;
  wire [34:0] result_162;
  reg [13:0] result_163;
  reg [1:0] result_164;
  reg [17:0] result_165;
  reg  result_166;
  wire [13:0] c$o_regmanage_case_alt;
  reg [13:0] c$o_regmanage_case_alt_0;
  wire [1:0] c$o_sensorType_case_alt;
  wire [1:0] c$o_sensorType_case_alt_0;
  wire [17:0] c$o_sensorcontrol_case_alt;
  reg [17:0] c$o_sensorcontrol_case_alt_0;
  wire  c$o_status_case_alt;
  reg  c$o_status_case_alt_0;
  wire [13:0] c$o_regmanage_case_alt_1;
  reg [13:0] c$o_regmanage_case_alt_2;
  wire [17:0] c$o_sensorcontrol_case_alt_1;
  reg [17:0] c$o_sensorcontrol_case_alt_2;
  wire  c$o_status_case_alt_1;
  wire  c$o_status_case_alt_2;
  wire [7:0] bs_64;
  wire [13:0] c$o_regmanage_case_alt_3;
  reg [13:0] c$o_regmanage_case_alt_4;
  wire [1:0] bs_65;
  wire [7:0] bs_66;
  wire [17:0] c$o_sensorcontrol_case_alt_3;
  reg [17:0] c$o_sensorcontrol_case_alt_4;
  wire [2:0] bs_67;
  wire [13:0] c$o_regmanage_case_alt_5;
  reg [13:0] c$o_regmanage_case_alt_6;
  wire [13:0] dt_87;
  wire [1:0] dt_88;
  wire [17:0] c$o_sensorcontrol_case_alt_5;
  reg [17:0] c$o_sensorcontrol_case_alt_6;
  wire [17:0] dt_89;
  wire  dt_90;
  wire [13:0] c$o_regmanage_case_alt_7;
  reg [13:0] c$o_regmanage_case_alt_8;
  wire [17:0] c$o_sensorcontrol_case_alt_7;
  reg [17:0] c$o_sensorcontrol_case_alt_8;
  wire [13:0] c$o_regmanage_case_alt_9;
  reg [13:0] c$o_regmanage_case_alt_10;
  wire [17:0] c$o_sensorcontrol_case_alt_9;
  reg [17:0] c$o_sensorcontrol_case_alt_10;
  wire [13:0] c$o_regmanage_case_alt_11;
  wire [13:0] c$o_regmanage_case_alt_12;
  wire [17:0] c$o_sensorcontrol_case_alt_11;
  wire [17:0] c$o_sensorcontrol_case_alt_12;
  wire [20:0] result_167;
  reg [13:0] dt_91;
  wire [0:0] c$cout_app_arg_26;
  wire  w10_3;
  reg [13:0] dt_92;
  wire  w9_3;
  wire  w8_2;
  wire  c$cout_app_arg_27;
  wire  \c$_INTERNAL_.w4_0 ;
  wire  \_INTERNAL_.w3 ;
  wire  \c$_INTERNAL_.w5_0 ;
  wire [0:0] c$cout_app_arg_28;
  wire  c$w9_app_arg_2;
  reg [13:0] dt_93;
  wire [15:0] ds2;
  wire [1:0] cin_12;
  wire  w12_2;
  wire [0:0] c$cout_app_arg_29;
  wire  w17_0;
  wire  w11_3;
  wire [0:0] c$cout_app_arg_30;
  reg [0:0] result_168;
  reg [0:0] c$cin_app_arg_11;
  reg [13:0] dt_94;
  wire  w16_1;
  wire  w18_0;
  wire [0:0] c$cout_app_arg_31;
  wire  c$w11_app_arg_2;
  reg  b_41;
  wire  w15_0;
  wire [0:0] c$cout_app_arg_32;
  wire  \c$_INTERNAL_.w4_app_arg ;
  wire  c$w16_app_arg_0;
  reg [13:0] dt_95;
  wire  w20_0;
  wire  w14;
  wire  w19_0;
  wire  w6_0;
  wire  c$w14_app_arg;
  wire  \c$_INTERNAL_.w3_app_arg ;
  reg [13:0] dt_96;
  wire  w24;
  wire  \c$_INTERNAL_.w3_app_arg_0 ;
  wire  c$w24_app_arg;
  wire [7:0] dat;
  wire  w7_1;
  wire [34:0] result_169;
  reg [13:0] result_170;
  reg [1:0] result_171;
  reg [17:0] result_172;
  reg  result_173;
  wire [13:0] c$o_regmanage_case_alt_13;
  wire [13:0] c$o_regmanage_case_alt_14;
  wire [1:0] c$o_sensorType_case_alt_1;
  reg [1:0] c$o_sensorType_case_alt_2;
  wire [17:0] c$o_sensorcontrol_case_alt_13;
  reg [17:0] c$o_sensorcontrol_case_alt_14;
  wire  c$o_status_case_alt_3;
  reg  c$o_status_case_alt_4;
  wire [1:0] c$o_sensorType_case_alt_3;
  wire [1:0] c$o_sensorType_case_alt_4;
  wire [17:0] c$o_sensorcontrol_case_alt_15;
  reg [17:0] c$o_sensorcontrol_case_alt_16;
  wire  c$o_status_case_alt_5;
  wire  c$o_status_case_alt_6;
  wire [1:0] bs_68;
  wire [2:0] bs_69;
  wire [8:0] bs_70;
  wire [17:0] c$o_sensorcontrol_case_alt_17;
  reg [17:0] c$o_sensorcontrol_case_alt_18;
  wire [2:0] bs_71;
  wire [13:0] dt_97;
  wire [1:0] dt_98;
  wire [17:0] c$o_sensorcontrol_case_alt_19;
  reg [17:0] c$o_sensorcontrol_case_alt_20;
  wire [17:0] dt_99;
  wire  dt_100;
  wire [17:0] c$o_sensorcontrol_case_alt_21;
  reg [17:0] c$o_sensorcontrol_case_alt_22;
  wire [17:0] c$o_sensorcontrol_case_alt_23;
  reg [17:0] c$o_sensorcontrol_case_alt_24;
  wire [17:0] c$o_sensorcontrol_case_alt_25;
  reg [17:0] c$o_sensorcontrol_case_alt_26;
  wire [16:0] result_174;
  wire [17:0] c$o_sensorcontrol_case_alt_27;
  wire [17:0] c$o_sensorcontrol_case_alt_28;
  wire  w31;
  wire  w21_0;
  wire  w32_1;
  wire  w7_2;
  wire  \c$_INTERNAL_.w6_1 ;
  wire  c$w32_app_arg;
  wire  c$w21_app_arg;
  wire  c$w21_app_arg_0;
  wire [1:0] cin_13;
  wire  w9_4;
  wire  w29_0;
  wire  \c$_INTERNAL_.w3_0 ;
  wire  c$w7_app_arg;
  wire  c$w7_app_arg_0;
  wire  w23_1;
  wire  w27_1;
  wire  \c$_INTERNAL_.w4_1 ;
  wire  \c$_INTERNAL_.w5_1 ;
  wire  c$w9_app_arg_3;
  reg [0:0] result_175;
  reg [0:0] c$cin_app_arg_12;
  wire  w8_3;
  wire  w10_4;
  reg  b_42;
  wire  w44;
  wire  w13_2;
  wire  c$w10_app_arg;
  wire  w24_0;
  wire  \c$_INTERNAL_.w3_app_arg_1 ;
  wire  w17_1;
  wire  w11_4;
  wire  w16_2;
  wire  w19_1;
  wire  \c$_INTERNAL_.w4_app_arg_0 ;
  wire  w14_0;
  wire [34:0] result_176;
  reg [13:0] result_177;
  reg [1:0] result_178;
  reg [17:0] result_179;
  reg  result_180;
  wire [13:0] c$o_regmanage_case_alt_15;
  reg [13:0] c$o_regmanage_case_alt_16;
  wire [1:0] c$o_sensorType_case_alt_5;
  wire [1:0] c$o_sensorType_case_alt_6;
  wire [17:0] c$o_sensorcontrol_case_alt_29;
  reg [17:0] c$o_sensorcontrol_case_alt_30;
  wire  c$o_status_case_alt_7;
  reg  c$o_status_case_alt_8;
  wire [13:0] c$o_regmanage_case_alt_17;
  reg [13:0] c$o_regmanage_case_alt_18;
  wire [17:0] c$o_sensorcontrol_case_alt_31;
  reg [17:0] c$o_sensorcontrol_case_alt_32;
  wire  c$o_status_case_alt_9;
  wire  c$o_status_case_alt_10;
  wire [7:0] bs_72;
  wire [13:0] c$o_regmanage_case_alt_19;
  reg [13:0] c$o_regmanage_case_alt_20;
  wire [1:0] bs_73;
  wire [7:0] bs_74;
  wire [17:0] c$o_sensorcontrol_case_alt_33;
  reg [17:0] c$o_sensorcontrol_case_alt_34;
  wire [2:0] bs_75;
  wire [13:0] c$o_regmanage_case_alt_21;
  reg [13:0] c$o_regmanage_case_alt_22;
  wire [13:0] dt_101;
  wire [1:0] dt_102;
  wire [17:0] c$o_sensorcontrol_case_alt_35;
  reg [17:0] c$o_sensorcontrol_case_alt_36;
  wire [17:0] dt_103;
  wire  dt_104;
  wire [13:0] c$o_regmanage_case_alt_23;
  reg [13:0] c$o_regmanage_case_alt_24;
  wire [17:0] c$o_sensorcontrol_case_alt_37;
  reg [17:0] c$o_sensorcontrol_case_alt_38;
  wire [13:0] c$o_regmanage_case_alt_25;
  reg [13:0] c$o_regmanage_case_alt_26;
  wire [17:0] c$o_sensorcontrol_case_alt_39;
  reg [17:0] c$o_sensorcontrol_case_alt_40;
  wire [13:0] c$o_regmanage_case_alt_27;
  wire [13:0] c$o_regmanage_case_alt_28;
  wire [17:0] c$o_sensorcontrol_case_alt_41;
  wire [17:0] c$o_sensorcontrol_case_alt_42;
  wire [20:0] result_181;
  reg [13:0] dt_105;
  wire [0:0] c$cout_app_arg_33;
  wire  w10_5;
  reg [13:0] dt_106;
  wire  w9_5;
  wire  w8_4;
  wire  c$cout_app_arg_34;
  wire  \c$_INTERNAL_.w4_2 ;
  wire  \c$_INTERNAL_.w3_1 ;
  wire  \c$_INTERNAL_.w5_2 ;
  wire [0:0] c$cout_app_arg_35;
  wire  c$w9_app_arg_4;
  reg [13:0] dt_107;
  wire [15:0] ds2_0;
  wire [1:0] cin_14;
  wire  w12_3;
  wire [0:0] c$cout_app_arg_36;
  wire  w17_2;
  wire  w11_5;
  wire [0:0] c$cout_app_arg_37;
  reg [0:0] result_182;
  reg [0:0] c$cin_app_arg_13;
  reg [13:0] dt_108;
  wire  w16_3;
  wire  w18_1;
  wire [0:0] c$cout_app_arg_38;
  wire  c$w11_app_arg_3;
  reg  b_43;
  wire  w15_1;
  wire [0:0] c$cout_app_arg_39;
  wire  \c$_INTERNAL_.w4_app_arg_1 ;
  wire  c$w16_app_arg_1;
  reg [13:0] dt_109;
  wire  w20_1;
  wire  w14_1;
  wire  w19_2;
  wire  w6_1;
  wire  c$w14_app_arg_0;
  wire  \c$_INTERNAL_.w3_app_arg_2 ;
  reg [13:0] dt_110;
  wire  w24_1;
  wire  \c$_INTERNAL_.w3_app_arg_3 ;
  wire  c$w24_app_arg_0;
  wire [7:0] dat_0;
  wire  w7_3;
  wire [34:0] result_183;
  reg [13:0] result_184;
  reg [1:0] result_185;
  reg [17:0] result_186;
  reg  result_187;
  wire [13:0] c$o_regmanage_case_alt_29;
  reg [13:0] c$o_regmanage_case_alt_30;
  wire [1:0] c$o_sensorType_case_alt_7;
  wire [1:0] c$o_sensorType_case_alt_8;
  wire [17:0] c$o_sensorcontrol_case_alt_43;
  reg [17:0] c$o_sensorcontrol_case_alt_44;
  wire  c$o_status_case_alt_11;
  reg  c$o_status_case_alt_12;
  wire [13:0] c$o_regmanage_case_alt_31;
  reg [13:0] c$o_regmanage_case_alt_32;
  wire [17:0] c$o_sensorcontrol_case_alt_45;
  reg [17:0] c$o_sensorcontrol_case_alt_46;
  wire  c$o_status_case_alt_13;
  wire  c$o_status_case_alt_14;
  wire [7:0] bs_76;
  wire [13:0] c$o_regmanage_case_alt_33;
  reg [13:0] c$o_regmanage_case_alt_34;
  wire [1:0] bs_77;
  wire [7:0] bs_78;
  wire [17:0] c$o_sensorcontrol_case_alt_47;
  reg [17:0] c$o_sensorcontrol_case_alt_48;
  wire [2:0] bs_79;
  wire [13:0] c$o_regmanage_case_alt_35;
  reg [13:0] c$o_regmanage_case_alt_36;
  wire [13:0] dt_111;
  wire [1:0] dt_112;
  wire [17:0] c$o_sensorcontrol_case_alt_49;
  reg [17:0] c$o_sensorcontrol_case_alt_50;
  wire [17:0] dt_113;
  wire  dt_114;
  wire [13:0] c$o_regmanage_case_alt_37;
  reg [13:0] c$o_regmanage_case_alt_38;
  wire [17:0] c$o_sensorcontrol_case_alt_51;
  reg [17:0] c$o_sensorcontrol_case_alt_52;
  wire [13:0] c$o_regmanage_case_alt_39;
  reg [13:0] c$o_regmanage_case_alt_40;
  wire [17:0] c$o_sensorcontrol_case_alt_53;
  reg [17:0] c$o_sensorcontrol_case_alt_54;
  wire [13:0] c$o_regmanage_case_alt_41;
  wire [13:0] c$o_regmanage_case_alt_42;
  wire [17:0] c$o_sensorcontrol_case_alt_55;
  wire [17:0] c$o_sensorcontrol_case_alt_56;
  wire [20:0] result_188;
  reg [13:0] dt_115;
  wire [0:0] c$cout_app_arg_40;
  wire  w10_6;
  reg [13:0] dt_116;
  wire  w9_6;
  wire  w8_5;
  wire  c$cout_app_arg_41;
  wire  \c$_INTERNAL_.w4_3 ;
  wire  \c$_INTERNAL_.w3_2 ;
  wire  \c$_INTERNAL_.w5_3 ;
  wire [0:0] c$cout_app_arg_42;
  wire  c$w9_app_arg_5;
  reg [13:0] dt_117;
  wire [15:0] ds2_1;
  wire [1:0] cin_15;
  wire  w12_4;
  wire [0:0] c$cout_app_arg_43;
  wire  w17_3;
  wire  w11_6;
  wire [0:0] c$cout_app_arg_44;
  reg [0:0] result_189;
  reg [0:0] c$cin_app_arg_14;
  reg [13:0] dt_118;
  wire  w16_4;
  wire  w18_2;
  wire [0:0] c$cout_app_arg_45;
  wire  c$w11_app_arg_4;
  reg  b_44;
  wire  w15_2;
  wire [0:0] c$cout_app_arg_46;
  wire  \c$_INTERNAL_.w4_app_arg_2 ;
  wire  c$w16_app_arg_2;
  reg [13:0] dt_119;
  wire  w20_2;
  wire  w14_2;
  wire  w19_3;
  wire  w6_2;
  wire  c$w14_app_arg_1;
  wire  \c$_INTERNAL_.w3_app_arg_4 ;
  reg [13:0] dt_120;
  wire  w24_2;
  wire  \c$_INTERNAL_.w3_app_arg_5 ;
  wire  c$w24_app_arg_1;
  wire [7:0] dat_1;
  wire  w7_4;
  reg [3:0] result_190;
  wire [3:0] c$o_partcontrol_case_alt;
  reg [3:0] c$o_partcontrol_case_alt_0;
  wire [3:0] c$o_partcontrol_case_alt_1;
  reg [3:0] c$o_partcontrol_case_alt_2;
  wire [3:0] c$o_partcontrol_case_alt_3;
  reg [3:0] c$o_partcontrol_case_alt_4;
  wire [3:0] c$o_partcontrol_case_alt_5;
  reg [3:0] c$o_partcontrol_case_alt_6;
  wire [3:0] dt_121;
  wire [5:0] result_191;
  wire [3:0] c$o_partcontrol_case_alt_7;
  wire [3:0] c$o_partcontrol_case_alt_8;
  wire [5:0] result_192;
  wire  \_INTERNAL_.w37 ;
  wire  w19_4;
  wire  w17_4;
  wire  w6_3;
  wire  \c$_INTERNAL_.w5_4 ;
  wire  c$cout_app_arg_47;
  wire  c$w17_app_arg;
  wire [3:0] cin_16;
  wire  \c$_INTERNAL_.w7_1 ;
  wire  w33_1;
  wire  c$cout_app_arg_48;
  wire  c$cout_app_arg_49;
  wire  c$cout_app_arg_50;
  wire  w9_7;
  wire  \c$_INTERNAL_.w8_0 ;
  wire  w21_1;
  wire  w16_5;
  wire  c$cout_app_arg_51;
  wire  c$w6_app_arg;
  reg [0:0] c$cin_app_arg_15;
  wire  \c$_INTERNAL_.w29_0 ;
  wire  c$cout_app_arg_52;
  wire  c$w9_app_arg_6;
  reg [0:0] c$cin_app_arg_16;
  wire  w27_2;
  wire  c$w21_app_arg_1;
  wire  \c$_INTERNAL_.w8_app_arg ;
  reg [0:0] c$cin_app_arg_17;
  reg [0:0] c$cin_app_arg_18;
  wire  w12_5;
  wire  w18_3;
  wire  c$w27_app_arg_1;
  wire  c$w12_app_arg_0;
  wire [7:0] counter;
  wire  b_45;
  wire  b_46;
  wire  b_47;
  reg [0:0] result_193;
  reg [0:0] result_194;
  wire  b_48;
  reg [0:0] result_195;
  wire  b_49;
  reg [0:0] result_196;
  wire  b_50;
  reg [0:0] result_197;
  reg [0:0] result_198;
  wire [5:0] cin_17;
  wire  c$w8_app_arg;
  wire  w7_5;
  wire  w8_6;
  wire  dt_122;
  reg  c$dt_case_alt_3;
  reg  c$dt_case_alt_4;
  reg  c$dt_case_alt_5;
  reg  c$dt_case_alt_6;
  reg  c$dt_case_alt_7;
  reg  c$dt_case_alt_8;
  reg  c$dt_case_alt_9;
  reg  c$dt_case_alt_10;
  wire [7:0] ds_0;
  wire [3:0] cout_0;
  reg  result_199;
  wire [7:0] w13_3;
  reg  c$dt_case_alt_11;
  reg  c$dt_case_alt_12;
  reg  c$dt_case_alt_13;
  reg  c$dt_case_alt_14;
  reg  c$dt_case_alt_15;
  reg  c$dt_case_alt_16;
  reg  c$dt_case_alt_17;
  reg  c$dt_case_alt_18;
  wire [7:0] ds_1;
  reg  result_200;
  wire [3:0] result_201;
  wire  c$o_sdi_case_alt;
  wire  c$o_sdi_case_alt_0;
  reg  c$o_sdi_case_alt_1;
  wire  c$o_sdi_case_alt_2;
  reg  c$o_sdi_case_alt_3;
  wire  c$o_sdi_case_alt_4;
  reg  result_202;
  reg  result_203;
  wire  c$o_spc_case_alt;
  reg  c$o_spc_case_alt_0;
  wire  c$o_spc_case_alt_1;
  wire  c$o_spc_case_alt_2;
  wire [2:0] result_204;
  wire [2:0] cout_1;
  wire  dt_123;
  wire  result_205;
  wire [4:0] cin_18;
  reg [0:0] result_206;
  reg [0:0] result_207;
  wire  b_51;
  reg [0:0] result_208;
  wire  b_52;
  reg [0:0] result_209;
  reg [0:0] result_210;
  wire  b_53;
  wire  b_54;
  wire  b_55;
  wire  w12_6;
  wire  b_56;
  reg  b_57;
  wire  b_58;
  reg [0:0] result_211;
  reg [0:0] result_212;
  wire  b_59;
  reg [0:0] result_213;
  wire  b_60;
  reg [0:0] result_214;
  wire  c$cout_app_arg_53;
  wire  b_61;
  reg [0:0] result_215;
  wire  c$w32_app_arg_0;
  wire  b_62;
  reg [0:0] result_216;
  wire  b_63;
  reg [0:0] result_217;
  wire  \c$_INTERNAL_.w18_app_arg_0 ;
  wire  b_64;
  reg [0:0] result_218;
  wire  w32_2;
  reg [0:0] result_219;
  wire  \_INTERNAL_.w27 ;
  wire [8:0] cin_19;
  wire  c$w13_app_arg_1;
  wire  \c$_INTERNAL_.w23_0 ;
  wire  w29_1;
  wire  \c$_INTERNAL_.w18_app_arg_1 ;
  wire  w11_7;
  wire  w10_7;
  wire  w13_4;
  wire  c$w19_app_arg;
  wire  \c$_INTERNAL_.w18_1 ;
  wire  w22_0;
  wire  c$w34_app_arg;
  wire  w19_5;
  wire [0:0] c$cout_app_arg_54;
  wire  w34_0;
  wire [0:0] c$cout_app_arg_55;
  wire [7:0] dt_124;
  wire [15:0] ds1_1;
  wire [14:0] result_220;
  wire [7:0] dt_125;
  reg [7:0] dt_126;
  reg [7:0] dt_127;
  wire  dt_128;
  wire  dt_129;
  wire [7:0] dt_130;
  wire [7:0] dt_131;
  wire [7:0] c_prescaler_1;
  wire [7:0] c_counter_2;
  wire [1:0] bs_80;
  wire [2:0] bs_81;
  wire [2:0] bs_82;
  wire [2:0] bs_83;
  wire [1:0] bs_84;
  wire [1:0] bs_85;
  wire [7:0] \c$_INTERNAL_.o_counter_case_alt_5 ;
  wire [7:0] \c$_INTERNAL_.o_counter_case_alt_6 ;
  wire  c$o_cs_case_alt;
  wire  c$o_cs_case_alt_0;
  wire  c$o_finished_case_alt;
  wire  c$o_finished_case_alt_0;
  wire [7:0] \c$_INTERNAL_.o_prescaler_case_alt_3 ;
  wire [7:0] \c$_INTERNAL_.o_prescaler_case_alt_4 ;
  reg [7:0] \c$_INTERNAL_.o_counter_case_alt_7 ;
  wire [7:0] \c$_INTERNAL_.o_counter_case_alt_8 ;
  reg  c$o_cs_case_alt_1;
  wire  c$o_cs_case_alt_2;
  reg  c$o_finished_case_alt_1;
  wire  c$o_finished_case_alt_2;
  wire [7:0] c$o_writeaddress_case_alt;
  wire [7:0] c$o_writeaddress_case_alt_0;
  wire [7:0] c$o_writedata_case_alt;
  wire [7:0] c$o_writedata_case_alt_0;
  reg [7:0] result_221;
  reg [7:0] result_222;
  reg  result_223;
  reg  result_224;
  reg [7:0] result_225;
  reg [7:0] result_226;
  wire [33:0] result_227;
  wire [3:0] result_228;
  wire [7:0] counter_0;
  reg  result_229;
  wire  c$o_sdi_case_alt_5;
  reg  c$o_sdi_case_alt_6;
  wire  c$o_sdi_case_alt_7;
  wire  c$o_sdi_case_alt_8;
  wire [2:0] result_230;
  reg  result_231;
  wire [7:0] ds_2;
  reg  c$dt_case_alt_19;
  reg  c$dt_case_alt_20;
  reg  c$dt_case_alt_21;
  reg  c$dt_case_alt_22;
  reg  c$dt_case_alt_23;
  reg  c$dt_case_alt_24;
  reg  c$dt_case_alt_25;
  reg  c$dt_case_alt_26;
  wire [2:0] cout_2;
  wire  dt_132;
  wire  result_232;
  wire [4:0] cin_20;
  reg [0:0] result_233;
  reg [0:0] result_234;
  wire  b_65;
  reg [0:0] result_235;
  wire  b_66;
  reg [0:0] result_236;
  reg [0:0] result_237;
  wire  b_67;
  wire  b_68;
  wire  b_69;
  reg  result_238;
  wire  c$o_spc_case_alt_3;
  reg  c$o_spc_case_alt_4;
  wire  c$o_spc_case_alt_5;
  wire  c$o_spc_case_alt_6;
  wire [2:0] result_239;
  wire [2:0] cout_3;
  wire  dt_133;
  wire  result_240;
  wire [2:0] cin_21;
  reg [0:0] result_241;
  reg [0:0] result_242;
  reg [0:0] result_243;
  wire  b_70;
  wire  b_71;
  wire  b_72;
  wire [41:0] result_244;
  reg [8:0] result_245;
  reg [7:0] result_246;
  reg [7:0] result_247;
  reg  result_248;
  reg [7:0] result_249;
  reg [7:0] result_250;
  wire [8:0] c$o_readdata_case_alt;
  reg [8:0] c$o_readdata_case_alt_0;
  wire [7:0] \c$_INTERNAL_.o_readdatatemp_case_alt ;
  reg [7:0] \c$_INTERNAL_.o_readdatatemp_case_alt_0 ;
  wire [7:0] c$o_readaddress_case_alt;
  wire [7:0] c$o_readaddress_case_alt_0;
  wire  c$o_cs_case_alt_3;
  reg  c$o_cs_case_alt_4;
  wire [7:0] \c$_INTERNAL_.o_counter_case_alt_9 ;
  reg [7:0] \c$_INTERNAL_.o_counter_case_alt_10 ;
  wire [7:0] \c$_INTERNAL_.o_prescaler_case_alt_5 ;
  wire [7:0] \c$_INTERNAL_.o_prescaler_case_alt_6 ;
  wire [8:0] c$o_readdata_case_alt_1;
  wire [8:0] c$o_readdata_case_alt_2;
  wire [7:0] \c$_INTERNAL_.o_readdatatemp_case_alt_1 ;
  wire [7:0] \c$_INTERNAL_.o_readdatatemp_case_alt_2 ;
  wire  c$o_cs_case_alt_5;
  wire  c$o_cs_case_alt_6;
  wire [7:0] \c$_INTERNAL_.o_counter_case_alt_11 ;
  wire [7:0] \c$_INTERNAL_.o_counter_case_alt_12 ;
  wire [2:0] bs_86;
  wire [2:0] bs_87;
  wire [1:0] bs_88;
  wire [2:0] bs_89;
  wire [2:0] bs_90;
  wire [1:0] bs_91;
  wire [7:0] c_counter_3;
  wire [7:0] c_prescaler_2;
  wire [7:0] c_readdatatemp;
  wire [8:0] dt_134;
  wire [7:0] dt_135;
  wire  dt_136;
  reg [7:0] dt_137;
  wire [7:0] dt_138;
  wire [15:0] result_251;
  wire [8:0] dt_139;
  wire [7:0] dt_140;
  wire [7:0] x_5;
  wire [7:0] dt_141;
  wire  c$cout_app_arg_56;
  wire  w10_8;
  wire  \c$_INTERNAL_.w35_0 ;
  wire  c$cout_app_arg_57;
  wire [7:0] cin_22;
  wire  w30_1;
  wire  w25;
  wire  c$cout_app_arg_58;
  wire  c$cout_app_arg_59;
  wire  w17_5;
  wire  \c$_INTERNAL_.w14_0 ;
  wire [0:0] c$cout_app_arg_60;
  reg [0:0] result_252;
  wire  w9_8;
  wire  w18_4;
  reg [0:0] result_253;
  wire  b_73;
  wire  \c$_INTERNAL_.w22_0 ;
  wire  w15_3;
  wire  c$w25_app_arg;
  reg [0:0] result_254;
  wire  b_74;
  wire  c$w15_app_arg;
  reg [0:0] result_255;
  wire  b_75;
  wire  w12_7;
  reg [0:0] result_256;
  wire  b_76;
  reg [0:0] result_257;
  wire  b_77;
  reg [0:0] result_258;
  reg [0:0] result_259;
  wire  b_78;
  reg  b_79;
  wire  b_80;
  wire  w11_8;
  wire  c$w11_app_arg_5;
  wire [11:0] result_260;
  wire [8:0] \c$_INTERNAL_.ds2_app_arg ;
  wire  \c$_INTERNAL_.ds2_app_arg_0 ;
  wire [64:0] result_261;
  reg [17:0] result_262;
  reg [16:0] result_263;
  reg [8:0] result_264;
  reg [17:0] result_265;
  reg [2:0] result_266;
  wire [17:0] c$o_output_case_alt;
  reg [17:0] c$o_output_case_alt_0;
  wire [16:0] c$o_spiWriteCtrl_case_alt;
  reg [16:0] c$o_spiWriteCtrl_case_alt_0;
  wire [8:0] c$o_spiReadCtrl_case_alt;
  reg [8:0] c$o_spiReadCtrl_case_alt_0;
  wire [17:0] \c$_INTERNAL_.o_lastCmd_case_alt ;
  wire [17:0] \c$_INTERNAL_.o_lastCmd_case_alt_0 ;
  wire [2:0] c$o_sensorOut_case_alt;
  reg [2:0] c$o_sensorOut_case_alt_0;
  wire [17:0] c$o_output_case_alt_1;
  reg [17:0] c$o_output_case_alt_2;
  wire [16:0] c$o_spiWriteCtrl_case_alt_1;
  wire [16:0] c$o_spiWriteCtrl_case_alt_2;
  wire [8:0] c$o_spiReadCtrl_case_alt_1;
  wire [8:0] c$o_spiReadCtrl_case_alt_2;
  wire [2:0] c$o_sensorOut_case_alt_1;
  reg [2:0] c$o_sensorOut_case_alt_2;
  wire [3:0] bs_92;
  wire [17:0] c$o_output_case_alt_3;
  wire [17:0] c$o_output_case_alt_4;
  wire [2:0] bs_93;
  wire [2:0] bs_94;
  wire [1:0] bs_95;
  wire [3:0] bs_96;
  wire [2:0] c$o_sensorOut_case_alt_3;
  wire [2:0] c$o_sensorOut_case_alt_4;
  wire [17:0] dt_142;
  wire [16:0] dt_143;
  wire [8:0] dt_144;
  wire [17:0] dt_145;
  wire [17:0] c_lastCmd;
  wire [2:0] dt_146;
  wire [5:0] dt_147;
  wire [15:0] result_267;
  reg [17:0] dt_148;
  reg [16:0] dt_149;
  reg [8:0] dt_150;
  reg [17:0] c$dt_case_alt_27;
  reg [17:0] dt_151;
  wire [15:0] ds1_2;
  wire [7:0] a_2;
  wire  w27_3;
  wire  c$cout_app_arg_61;
  reg [17:0] c$dt_case_alt_28;
  wire  w11_9;
  wire  w20_3;
  wire  w16_6;
  wire [7:0] x_6;
  wire  w15_4;
  wire  \c$_INTERNAL_.w7_2 ;
  wire  w39_1;
  wire  c$w11_app_arg_6;
  wire  c$w11_app_arg_7;
  wire [7:0] x_7;
  wire  w10_9;
  wire  w9_9;
  wire  \c$_INTERNAL_.w6_2 ;
  wire  \c$_INTERNAL_.w37_0 ;
  wire  \c$_INTERNAL_.w5_5 ;
  wire  \c$_INTERNAL_.w37_app_arg ;
  wire  c$w20_app_arg;
  wire  c$w20_app_arg_0;
  wire  c$w9_app_arg_7;
  wire  c$w9_app_arg_8;
  wire  c$w10_app_arg_0;
  wire  c$w10_app_arg_1;
  wire [3:0] cin_23;
  wire  w21_2;
  wire  w38_0;
  wire  w34_1;
  wire  \c$_INTERNAL_.w6_app_arg_1 ;
  reg [0:0] c$cin_app_arg_19;
  wire  w14_3;
  wire  c$w34_app_arg_0;
  wire  \c$_INTERNAL_.w7_app_arg_1 ;
  wire  \c$_INTERNAL_.w5_app_arg ;
  wire  \c$_INTERNAL_.w37_app_arg_0 ;
  reg [0:0] result_268;
  wire  w12_8;
  wire  w29_2;
  wire  w48_0;
  wire  w33_2;
  reg [0:0] result_269;
  reg [0:0] result_270;
  reg  b_81;
  wire  w31_0;
  wire  w28_0;
  reg  b_82;
  reg  b_83;
  wire  w44_0;
  wire  \c$_INTERNAL_.w7_app_arg_2 ;
  wire  w25_0;
  wire  w22_1;
  wire  c$w44_app_arg;
  wire  w18_5;
  wire  \c$_INTERNAL_.w5_app_arg_0 ;
  wire [17:0] c$app_arg_10;
  wire [20:0] result_271;
  wire  startGyr;
  wire  startMag;
  wire  startAcc;
  wire  startInit;
  wire [33:0] result_272;
  reg [17:0] result_273;
  reg [13:0] result_274;
  reg [1:0] result_275;
  wire [17:0] c$o_command_case_alt;
  reg [17:0] c$o_command_case_alt_0;
  wire [13:0] c$o_managerctrl_case_alt;
  reg [13:0] c$o_managerctrl_case_alt_0;
  wire [1:0] c$o_sensorType_case_alt_9;
  reg [1:0] c$o_sensorType_case_alt_10;
  wire [17:0] c$o_command_case_alt_1;
  reg [17:0] c$o_command_case_alt_2;
  wire [13:0] c$o_managerctrl_case_alt_1;
  reg [13:0] c$o_managerctrl_case_alt_2;
  wire [1:0] c$o_sensorType_case_alt_11;
  reg [1:0] c$o_sensorType_case_alt_12;
  wire [4:0] bs_97;
  wire [17:0] c$o_command_case_alt_3;
  reg [17:0] c$o_command_case_alt_4;
  wire [4:0] bs_98;
  wire [13:0] c$o_managerctrl_case_alt_3;
  reg [13:0] c$o_managerctrl_case_alt_4;
  wire [4:0] bs_99;
  wire [1:0] c$o_sensorType_case_alt_13;
  reg [1:0] c$o_sensorType_case_alt_14;
  wire [17:0] c$o_command_case_alt_5;
  wire [17:0] c$o_command_case_alt_6;
  wire [17:0] dt_152;
  wire [13:0] c$o_managerctrl_case_alt_5;
  wire [13:0] c$o_managerctrl_case_alt_6;
  wire [13:0] dt_153;
  wire [1:0] c$o_sensorType_case_alt_15;
  wire [1:0] c$o_sensorType_case_alt_16;
  wire [14:0] result_276;
  wire  w39_2;
  wire [0:0] c$cout_app_arg_62;
  wire [17:0] dt_154;
  wire [13:0] dt_155;
  wire  w41;
  wire [0:0] c$cout_app_arg_63;
  wire  c$w39_app_arg;
  wire  w30_2;
  wire  w42;
  wire [0:0] c$cout_app_arg_64;
  wire  c$w41_app_arg;
  wire  c$w41_app_arg_0;
  wire  result_277;
  wire [1:0] dt_156;
  wire  w25_1;
  wire  w17_6;
  wire  \c$_INTERNAL_.w28_0 ;
  wire [0:0] c$cout_app_arg_65;
  wire  c$w42_app_arg;
  wire  c$w30_app_arg;
  wire  w16_7;
  wire  \c$_INTERNAL_.w6_3 ;
  wire  \c$_INTERNAL_.w14_1 ;
  wire  \c$_INTERNAL_.w7_3 ;
  wire  w13_5;
  wire  w9_10;
  wire  w15_5;
  wire  w12_9;
  wire  \c$_INTERNAL_.w38_app_arg ;
  wire  \c$_INTERNAL_.w14_app_arg_1 ;
  wire  w8_7;
  wire  w23_2;
  wire  w32_3;
  wire  w22_2;
  wire  w5_0;
  wire  c$w9_app_arg_9;
  wire [3:0] cin_24;
  wire  c$w8_app_arg_0;
  wire  c$w8_app_arg_1;
  wire  c$w22_app_arg;
  reg [0:0] c$cin_app_arg_20;
  wire  \c$_INTERNAL_.w7_app_arg_3 ;
  wire  \c$_INTERNAL_.w7_app_arg_4 ;
  reg [0:0] c$cin_app_arg_21;
  wire  \c$_INTERNAL_.w7_app_arg_5 ;
  reg [0:0] c$cin_app_arg_22;
  reg [0:0] c$cin_app_arg_23;
  wire [3:0] c$case_alt_10;
  wire  a4_0;
  wire  a5;
  wire  a6;
  wire  a7;
  wire [3:0] ds_3;
  wire [9:0] result_278;
  reg  result_279;
  reg  result_280;
  reg  result_281;
  reg  result_282;
  reg  result_283;
  reg  result_284;
  reg  result_285;
  reg  result_286;
  reg  result_287;
  reg  result_288;
  wire  c$o_csAGOut_case_alt;
  wire  c$o_csAGOut_case_alt_0;
  wire  \c$_INTERNAL_.o_csAG_case_alt ;
  reg  \c$_INTERNAL_.o_csAG_case_alt_0 ;
  wire  c$o_csAltOut_case_alt;
  wire  c$o_csAltOut_case_alt_0;
  wire  \c$_INTERNAL_.o_csAlt_case_alt ;
  reg  \c$_INTERNAL_.o_csAlt_case_alt_0 ;
  wire  c$o_csMagOut_case_alt;
  wire  c$o_csMagOut_case_alt_0;
  wire  \c$_INTERNAL_.o_csMag_case_alt ;
  reg  \c$_INTERNAL_.o_csMag_case_alt_0 ;
  wire  c$o_sdiOut_case_alt;
  wire  c$o_sdiOut_case_alt_0;
  wire  \c$_INTERNAL_.o_sdi_case_alt ;
  reg  \c$_INTERNAL_.o_sdi_case_alt_0 ;
  wire  c$o_spcOut_case_alt;
  wire  c$o_spcOut_case_alt_0;
  wire  \c$_INTERNAL_.o_spc_case_alt ;
  reg  \c$_INTERNAL_.o_spc_case_alt_0 ;
  wire  \c$_INTERNAL_.o_csAG_case_alt_1 ;
  wire  \c$_INTERNAL_.o_csAG_case_alt_2 ;
  wire  \c$_INTERNAL_.o_csAlt_case_alt_1 ;
  wire  \c$_INTERNAL_.o_csAlt_case_alt_2 ;
  wire  \c$_INTERNAL_.o_csMag_case_alt_1 ;
  wire  \c$_INTERNAL_.o_csMag_case_alt_2 ;
  wire  \c$_INTERNAL_.o_sdi_case_alt_1 ;
  wire  \c$_INTERNAL_.o_sdi_case_alt_2 ;
  wire  \c$_INTERNAL_.o_spc_case_alt_1 ;
  wire  \c$_INTERNAL_.o_spc_case_alt_2 ;
  wire [1:0] bs_100;
  wire [2:0] bs_101;
  wire [1:0] bs_102;
  wire [2:0] bs_103;
  wire [1:0] bs_104;
  wire [2:0] bs_105;
  wire [1:0] bs_106;
  wire [2:0] bs_107;
  wire [1:0] bs_108;
  wire [2:0] bs_109;
  wire  c_spc;
  wire  c_sdi;
  wire  c_csMag;
  wire  c_csAlt;
  wire  c_csAG;
  wire [1:0] dt_157;
  wire [1:0] dt_158;
  wire [1:0] dt_159;
  wire [24:0] cout_4;
  wire  dt_160;
  wire  dt_161;
  wire  dt_162;
  wire  dt_163;
  wire [0:0] dt_164;
  wire  dt_165;
  wire [0:0] dt_166;
  wire  c$cout_app_arg_66;
  wire [3:0] cin_25;
  reg [0:0] result_289;
  wire [0:0] c$cout_app_arg_67;
  reg [0:0] result_290;
  reg  b_84;
  reg [0:0] result_291;
  reg [0:0] result_292;
  reg  b_85;
  wire [0:0] c$cout_app_arg_68;
  reg  b_86;
  reg  b_87;
  wire  c$cout_app_arg_69;
  wire  c$cout_app_arg_70;
  wire  c$cout_app_arg_71;
  wire [1:0] sensorType;
  wire [2:0] inPins;
  reg  b_88;
  reg [0:0] result_293;
  wire  c$cout_app_arg_72;
  wire [1:0] result_294;
  wire signed [15:0] dt_167;
  wire signed [15:0] c$o_regVal_case_alt;
  wire signed [15:0] c$o_regVal_case_alt_0;
  reg signed [15:0] result_295;
  reg  b_89;
  reg [0:0] result_296;
  wire  c$cout_app_arg_73;
  wire [1:0] result_297;
  wire signed [15:0] dt_168;
  wire signed [15:0] c$o_regVal_case_alt_1;
  wire signed [15:0] c$o_regVal_case_alt_2;
  reg signed [15:0] result_298;
  reg  b_90;
  reg [0:0] result_299;
  wire  c$cout_app_arg_74;
  wire [1:0] result_300;
  wire signed [15:0] dt_169;
  wire signed [15:0] c$o_regVal_case_alt_3;
  wire signed [15:0] c$o_regVal_case_alt_4;
  reg signed [15:0] result_301;
  reg  b_91;
  reg [0:0] result_302;
  wire  c$cout_app_arg_75;
  wire [1:0] result_303;
  wire signed [15:0] dt_170;
  wire signed [15:0] c$o_regVal_case_alt_5;
  wire signed [15:0] c$o_regVal_case_alt_6;
  reg signed [15:0] result_304;
  reg  b_92;
  reg [0:0] result_305;
  wire  c$cout_app_arg_76;
  wire [1:0] result_306;
  wire signed [15:0] dt_171;
  wire signed [15:0] c$o_regVal_case_alt_7;
  wire signed [15:0] c$o_regVal_case_alt_8;
  reg signed [15:0] result_307;
  reg  b_93;
  reg [0:0] result_308;
  wire  c$cout_app_arg_77;
  wire [1:0] result_309;
  wire signed [15:0] dt_172;
  wire signed [15:0] c$o_regVal_case_alt_9;
  wire signed [15:0] c$o_regVal_case_alt_10;
  reg signed [15:0] result_310;
  reg  b_94;
  reg [0:0] result_311;
  wire  c$cout_app_arg_78;
  wire [1:0] result_312;
  wire signed [15:0] dt_173;
  wire signed [15:0] c$o_regVal_case_alt_11;
  wire signed [15:0] c$o_regVal_case_alt_12;
  reg signed [15:0] result_313;
  wire [27:0] result_314;
  reg signed [15:0] result_315;
  reg [7:0] result_316;
  reg [3:0] result_317;
  wire signed [15:0] c$o_fullreg_case_alt;
  reg signed [15:0] c$o_fullreg_case_alt_0;
  wire [7:0] \c$_INTERNAL_.o_buffer_case_alt ;
  wire [7:0] \c$_INTERNAL_.o_buffer_case_alt_0 ;
  wire [3:0] c$o_regname_case_alt;
  reg [3:0] c$o_regname_case_alt_0;
  wire signed [15:0] c$o_fullreg_case_alt_1;
  wire signed [15:0] c$o_fullreg_case_alt_2;
  wire [3:0] c$o_regname_case_alt_1;
  wire [3:0] c$o_regname_case_alt_2;
  wire [2:0] bs_110;
  wire [1:0] bs_111;
  wire [2:0] bs_112;
  wire [7:0] c_buffer;
  wire signed [15:0] dt_174;
  wire [7:0] dt_175;
  wire [3:0] dt_176;
  reg [7:0] w6_4;
  wire [12:0] ds1_3;
  wire [7:0] result_318;
  wire signed [15:0] dt_177;
  reg [3:0] dt_178;
  wire  c$cout_app_arg_79;
  wire [1:0] cin_26;
  wire [0:0] c$cout_app_arg_80;
  reg [0:0] result_319;
  reg [0:0] result_320;
  wire [0:0] c$cout_app_arg_81;
  reg  b_95;
  reg  b_96;
  wire [0:0] ds3_1;
  wire  c$cout_app_arg_82;
  reg  b_97;
  reg [0:0] result_321;
  wire  c$cout_app_arg_83;
  wire [1:0] result_322;
  wire signed [15:0] dt_179;
  wire signed [15:0] c$o_regVal_case_alt_13;
  wire signed [15:0] c$o_regVal_case_alt_14;
  reg signed [15:0] result_323;
  wire [3:0] internRegister1;
  wire signed [15:0] internRegister;
  wire [1:0] \c$$d(%,%)1_0 ;
  reg  b_98;
  reg [0:0] result_324;
  wire  c$cout_app_arg_84;
  wire [1:0] result_325;
  wire signed [15:0] dt_180;
  wire signed [15:0] c$o_regVal_case_alt_15;
  wire signed [15:0] c$o_regVal_case_alt_16;
  reg signed [15:0] result_326;
  wire [143:0] result_327;
  wire [147:0] result_328;
  wire signed [15:0] c$ds1_app_arg_1;
  wire signed [15:0] gyroz;
  wire signed [15:0] gyrox;
  wire signed [15:0] gyroy;
  wire [63:0] scrut4;
  wire [79:0] scrut3_1;
  wire [95:0] scrut2_2;
  wire [111:0] scrut1_2;
  wire [127:0] scrut_1;
  wire [143:0] ds1_4;
  wire  result_329;
  reg  c$resetPin_case_alt;
  wire  h;
  reg  c$resetPin_case_alt_0;
  wire [1:0] ds_4;
  wire [0:0] i;
  wire [0:0] c$ds_app_arg_0;
  reg  result_330;
  reg  c$ds_app_arg_1;
  reg [65:0] wrM_0;
  reg [64:0] tup_0;
  wire signed [63:0] wild_6;
  wire signed [63:0] n;
  wire [64:0] x_8;
  wire [1:0] \$d(%,%) ;
  wire  c$initalCounter_app_arg_selection_res;
  wire [35:0] c$vec;
  wire  result_2_selection_res;
  wire  result_3_selection_res;
  wire  result_4_selection_res;
  wire [15:0] c$vecflat;
  wire [15:0] c$vecflat_0;
  wire [5:0] c$vecflat_1;
  wire [5:0] c$vecflat_2;
  wire [23:0] c$vecflat_3;
  wire  \c$_INTERNAL_.o_radius_case_alt_0_selection_res ;
  wire [23:0] c$vecflat_4;
  wire [23:0] c$vecflat_5;
  wire  result_8_selection_res;
  wire  result_9_selection_res;
  wire  result_10_selection_res;
  wire [15:0] c$vecflat_6;
  wire [15:0] c$vecflat_7;
  wire [5:0] c$vecflat_8;
  wire [5:0] c$vecflat_9;
  wire [23:0] c$vecflat_10;
  wire  \c$_INTERNAL_.o_radius_case_alt_4_selection_res ;
  wire [23:0] c$vecflat_11;
  wire [23:0] c$vecflat_12;
  wire  result_14_selection_res;
  wire  result_15_selection_res;
  wire  result_16_selection_res;
  wire [15:0] c$vecflat_13;
  wire [15:0] c$vecflat_14;
  wire [5:0] c$vecflat_15;
  wire [5:0] c$vecflat_16;
  wire [23:0] c$vecflat_17;
  wire  \c$_INTERNAL_.o_radius_case_alt_8_selection_res ;
  wire [23:0] c$vecflat_18;
  wire [23:0] c$vecflat_19;
  wire  result_19_selection_res;
  wire  result_20_selection_res;
  wire  result_21_selection_res;
  wire  result_22_selection_res;
  wire  result_23_selection_res;
  wire  result_24_selection_res;
  wire  result_25_selection_res;
  wire  result_26_selection_res;
  wire  result_27_selection_res;
  wire [143:0] c$vecflat_20;
  wire  c$o_resets_case_alt_0_selection_res;
  wire [15:0] c$vecflat_21;
  wire [15:0] c$vecflat_22;
  wire [5:0] c$vecflat_23;
  wire [5:0] c$vecflat_24;
  wire [11:0] c$vecflat_25;
  wire  c$o_moveticks_case_alt_0_selection_res;
  wire [47:0] c$vecflat_26;
  wire [47:0] c$vecflat_27;
  wire [29:0] c$vecflat_28;
  wire  \c$_INTERNAL_.o_score_case_alt_0_selection_res ;
  wire [2:0] c$vecflat_29;
  wire  c$o_gameover_case_alt_0_selection_res;
  wire [5:0] c$vecflat_30;
  wire [5:0] c$vecflat_31;
  wire [11:0] c$vecflat_32;
  wire  \c$_INTERNAL_.o_shotCounter_case_alt_0_selection_res ;
  wire [143:0] c$vecflat_33;
  wire  c$o_resets_case_alt_2_selection_res;
  wire [11:0] c$vecflat_34;
  wire [11:0] c$vecflat_35;
  wire [29:0] c$vecflat_36;
  wire [29:0] c$vecflat_37;
  wire [2:0] c$vecflat_38;
  wire [2:0] c$vecflat_39;
  wire [11:0] c$vecflat_40;
  wire  \c$_INTERNAL_.o_shotCounter_case_alt_2_selection_res ;
  wire [143:0] c$vecflat_41;
  wire [143:0] c$vecflat_42;
  wire [11:0] c$vecflat_43;
  wire [11:0] c$vecflat_44;
  wire  result_30_selection_res;
  wire  c$case_alt_selection_res;
  wire  c$case_alt_0_selection_res;
  wire  c$dt_app_arg_selection_res;
  wire  c$dt_case_alt_1_selection_res;
  wire  c$dt_case_alt_2_selection_res;
  wire [7:0] result_32_selection;
  wire  result_35_selection_res;
  wire [7:0] c$triggerresetall1_$jOut_app_arg_selection;
  wire [2:0] c$i_182;
  wire  result_38_selection_res;
  wire  result_39_selection_res;
  wire  result_40_selection_res;
  wire [15:0] c$vecflat_45;
  wire [15:0] c$vecflat_46;
  wire [5:0] c$vecflat_47;
  wire [5:0] c$vecflat_48;
  wire [23:0] c$vecflat_49;
  wire  \c$_INTERNAL_.o_radius_case_alt_12_selection_res ;
  wire [23:0] c$vecflat_50;
  wire [23:0] c$vecflat_51;
  wire  result_45_selection_res;
  wire  result_46_selection_res;
  wire  result_47_selection_res;
  wire  result_48_selection_res;
  wire  result_49_selection_res;
  wire  result_50_selection_res;
  wire  result_51_selection_res;
  wire  result_52_selection_res;
  wire [9:0] c$vecflat_52;
  wire [9:0] c$vecflat_53;
  wire [9:0] c$vecflat_54;
  wire [9:0] c$vecflat_55;
  wire [8:0] c$vecflat_56;
  wire  c$o_color_case_alt_8_selection_res;
  wire [8:0] c$vecflat_57;
  wire  \c$_INTERNAL_.o_tmpcolor_case_alt_0_selection_res ;
  wire [23:0] c$vecflat_58;
  wire  \c$_INTERNAL_.o_tmpdist_case_alt_0_selection_res ;
  wire [9:0] c$vecflat_59;
  wire [9:0] c$vecflat_60;
  wire [9:0] c$vecflat_61;
  wire [9:0] c$vecflat_62;
  wire [5:0] c$vecflat_63;
  wire [5:0] c$vecflat_64;
  wire [8:0] c$vecflat_65;
  wire [8:0] c$vecflat_66;
  wire [8:0] c$vecflat_67;
  wire [8:0] c$vecflat_68;
  wire [23:0] c$vecflat_69;
  wire [23:0] c$vecflat_70;
  wire  result_59_selection_res;
  wire  c$$j1_selection_res;
  wire [4:0] c$bv;
  wire [4:0] c$bv_0;
  wire  c$case_alt_1_selection_res;
  wire [2:0] c$i_260;
  wire  result_64_selection_res;
  wire  result_65_selection_res;
  wire  result_66_selection_res;
  wire  result_67_selection_res;
  wire  result_68_selection_res;
  wire  result_69_selection_res;
  wire  result_70_selection_res;
  wire  result_71_selection_res;
  wire  result_72_selection_res;
  wire  result_73_selection_res;
  wire  result_74_selection_res;
  wire [8:0] c$vecflat_71;
  wire  c$o_color_case_alt_12_selection_res;
  wire [8:0] c$vecflat_72;
  wire  \c$_INTERNAL_.o_tmpcolor_case_alt_4_selection_res ;
  wire [5:0] c$vecflat_73;
  wire [5:0] c$vecflat_74;
  wire [9:0] c$vecflat_75;
  wire [9:0] c$vecflat_76;
  wire [9:0] c$vecflat_77;
  wire [9:0] c$vecflat_78;
  wire [15:0] c$vecflat_79;
  wire [15:0] c$vecflat_80;
  wire [15:0] c$vecflat_81;
  wire [15:0] c$vecflat_82;
  wire [9:0] c$vecflat_83;
  wire [9:0] c$vecflat_84;
  wire [9:0] c$vecflat_85;
  wire [9:0] c$vecflat_86;
  wire [15:0] c$vecflat_87;
  wire [15:0] c$vecflat_88;
  wire [9:0] c$vecflat_89;
  wire [9:0] c$vecflat_90;
  wire [8:0] c$vecflat_91;
  wire [8:0] c$vecflat_92;
  wire [8:0] c$vecflat_93;
  wire [8:0] c$vecflat_94;
  wire [4:0] c$i_297;
  wire signed [14:0] c$s;
  wire [9:0] c$bv_1;
  wire signed [14:0] c$s_0;
  wire [9:0] c$bv_2;
  wire [15:0] \c$r'_projection ;
  wire  c$case_alt_2_selection_res;
  wire [14:0] c$bv_3;
  wire  result_82_selection_res;
  wire [15:0] \c$r'_0_projection ;
  wire  c$case_alt_3_selection_res;
  wire [14:0] c$bv_4;
  wire  result_83_selection_res;
  wire  result_84_selection_res;
  wire [19:0] c$bv_5;
  wire  c$case_alt_4_selection_res;
  wire  result_85_selection_res;
  wire [19:0] c$bv_6;
  wire  c$case_alt_5_selection_res;
  wire  c$case_alt_7_selection_res;
  wire  result_86_selection_res;
  wire signed [14:0] c$s_1;
  wire signed [63:0] bv_res;
  wire [7:0] c$i_328;
  wire [7:0] c$i_330;
  wire signed [63:0] bv_0_res;
  wire [7:0] c$i_331;
  wire [7:0] c$i_333;
  wire  result_91_selection_res;
  wire  result_92_selection_res;
  wire  result_93_selection_res;
  wire  result_94_selection_res;
  wire  result_95_selection_res;
  wire [11:0] c$vecflat_95;
  wire  c$o_actcolor_case_alt_0_selection_res;
  wire [9:0] c$vecflat_96;
  wire [9:0] c$vecflat_97;
  wire [9:0] c$vecflat_98;
  wire [9:0] c$vecflat_99;
  wire [9:0] c$vecflat_100;
  wire [9:0] c$vecflat_101;
  wire [9:0] c$vecflat_102;
  wire [9:0] c$vecflat_103;
  wire [11:0] c$vecflat_104;
  wire  c$o_actcolor_case_alt_2_selection_res;
  wire [11:0] c$vecflat_105;
  wire [11:0] c$vecflat_106;
  wire  result_101_selection_res;
  wire [51:0] c$vecflat_107;
  wire  c$o_outpoint_case_alt_0_selection_res;
  wire [51:0] c$vecflat_108;
  wire  c$o_outpoint_case_alt_2_selection_res;
  wire [51:0] c$vecflat_109;
  wire [51:0] c$vecflat_110;
  wire  result_107_selection_res;
  wire  result_110_selection_res;
  wire  result_111_selection_res;
  wire  result_112_selection_res;
  wire  result_113_selection_res;
  wire  result_114_selection_res;
  wire  result_115_selection_res;
  wire  result_116_selection_res;
  wire  result_117_selection_res;
  wire  result_118_selection_res;
  wire  result_119_selection_res;
  wire  result_120_selection_res;
  wire [2:0] c$vecflat_111;
  wire  c$o_bufferPin_case_alt_0_selection_res;
  wire [5:0] c$vecflat_112;
  wire [5:0] c$vecflat_113;
  wire [5:0] c$vecflat_114;
  wire [5:0] c$vecflat_115;
  wire [5:0] c$vecflat_116;
  wire [5:0] c$vecflat_117;
  wire [41:0] c$vecflat_118;
  wire  c$o_ramwrite_case_alt_0_selection_res;
  wire [39:0] c$vecflat_119;
  wire  c$o_rampos_case_alt_0_selection_res;
  wire [7:0] c$vecflat_120;
  wire [7:0] c$vecflat_121;
  wire [2:0] c$vecflat_122;
  wire  c$o_extclock_case_alt_0_selection_res;
  wire [1:0] c$vecflat_123;
  wire [1:0] c$vecflat_124;
  wire [9:0] c$vecflat_125;
  wire [9:0] c$vecflat_126;
  wire [13:0] c$vecflat_127;
  wire [13:0] c$vecflat_128;
  wire [2:0] c$vecflat_129;
  wire [2:0] c$vecflat_130;
  wire [41:0] c$vecflat_131;
  wire [41:0] c$vecflat_132;
  wire [39:0] c$vecflat_133;
  wire  c$o_rampos_case_alt_2_selection_res;
  wire [2:0] c$vecflat_134;
  wire [2:0] c$vecflat_135;
  wire [39:0] c$vecflat_136;
  wire [39:0] c$vecflat_137;
  wire [4:0] c$bv_7;
  wire [4:0] c$bv_8;
  wire [2:0] c$vecflat_138;
  wire [2:0] c$vecflat_139;
  wire [2:0] c$vecflat_140;
  wire [2:0] c$vecflat_141;
  wire  c$o_shot_case_alt_1_selection_res;
  wire [2:0] c$vecflat_142;
  wire  c$o_reset_case_alt_1_selection_res;
  wire [2:0] c$vecflat_143;
  wire  result_133_selection_res;
  wire  result_134_selection_res;
  wire [27:0] c$bv_9;
  wire [111:0] c$vecflat_144;
  wire [111:0] c$vecflat_145;
  wire  \c$_INTERNAL_.o_internalRotation_case_alt_1_selection_res ;
  wire [111:0] c$vecflat_146;
  wire [19:0] c$vecflat_147;
  wire [19:0] c$vecflat_148;
  wire  \c$_INTERNAL_.o_internalRotation_case_alt_3_selection_res ;
  wire [111:0] c$vecflat_149;
  wire [15:0] c$vecflat_150;
  wire [15:0] c$vecflat_151;
  wire  result_142_selection_res;
  wire  result_143_selection_res;
  wire  result_144_selection_res;
  wire  result_147_selection_res;
  wire  result_148_selection_res;
  wire  result_149_selection_res;
  wire  result_150_selection_res;
  wire [47:0] c$vecflat_152;
  wire [47:0] c$vecflat_153;
  wire [19:0] c$vecflat_154;
  wire [19:0] c$vecflat_155;
  wire  \c$_INTERNAL_.o_gamemode_case_alt_0_selection_res ;
  wire [83:0] c$vecflat_156;
  wire  \c$_INTERNAL_.o_rotation_case_alt_0_selection_res ;
  wire  \c$_INTERNAL_.o_gamemode_case_alt_2_selection_res ;
  wire [83:0] c$vecflat_157;
  wire [83:0] c$vecflat_158;
  wire  result_163_selection_res;
  wire  result_164_selection_res;
  wire  result_165_selection_res;
  wire  result_166_selection_res;
  wire [111:0] c$vecflat_159;
  wire  c$o_regmanage_case_alt_0_selection_res;
  wire [3:0] c$vecflat_160;
  wire [3:0] c$vecflat_161;
  wire [143:0] c$vecflat_162;
  wire  c$o_sensorcontrol_case_alt_0_selection_res;
  wire [2:0] c$vecflat_163;
  wire  c$o_status_case_alt_0_selection_res;
  wire [111:0] c$vecflat_164;
  wire  c$o_regmanage_case_alt_2_selection_res;
  wire [143:0] c$vecflat_165;
  wire  c$o_sensorcontrol_case_alt_2_selection_res;
  wire [2:0] c$vecflat_166;
  wire [2:0] c$vecflat_167;
  wire [111:0] c$vecflat_168;
  wire  c$o_regmanage_case_alt_4_selection_res;
  wire [143:0] c$vecflat_169;
  wire  c$o_sensorcontrol_case_alt_4_selection_res;
  wire [111:0] c$vecflat_170;
  wire  c$o_regmanage_case_alt_6_selection_res;
  wire [143:0] c$vecflat_171;
  wire  c$o_sensorcontrol_case_alt_6_selection_res;
  wire [111:0] c$vecflat_172;
  wire  c$o_regmanage_case_alt_8_selection_res;
  wire [143:0] c$vecflat_173;
  wire  c$o_sensorcontrol_case_alt_8_selection_res;
  wire [111:0] c$vecflat_174;
  wire  c$o_regmanage_case_alt_10_selection_res;
  wire [143:0] c$vecflat_175;
  wire  c$o_sensorcontrol_case_alt_10_selection_res;
  wire [111:0] c$vecflat_176;
  wire [111:0] c$vecflat_177;
  wire [143:0] c$vecflat_178;
  wire [143:0] c$vecflat_179;
  wire  result_170_selection_res;
  wire  result_171_selection_res;
  wire  result_172_selection_res;
  wire  result_173_selection_res;
  wire [27:0] c$vecflat_180;
  wire [27:0] c$vecflat_181;
  wire [5:0] c$vecflat_182;
  wire  c$o_sensorType_case_alt_2_selection_res;
  wire [161:0] c$vecflat_183;
  wire  c$o_sensorcontrol_case_alt_14_selection_res;
  wire [2:0] c$vecflat_184;
  wire  c$o_status_case_alt_4_selection_res;
  wire [5:0] c$vecflat_185;
  wire [5:0] c$vecflat_186;
  wire [161:0] c$vecflat_187;
  wire  c$o_sensorcontrol_case_alt_16_selection_res;
  wire [2:0] c$vecflat_188;
  wire [2:0] c$vecflat_189;
  wire [161:0] c$vecflat_190;
  wire  c$o_sensorcontrol_case_alt_18_selection_res;
  wire [161:0] c$vecflat_191;
  wire  c$o_sensorcontrol_case_alt_20_selection_res;
  wire [161:0] c$vecflat_192;
  wire  c$o_sensorcontrol_case_alt_22_selection_res;
  wire [161:0] c$vecflat_193;
  wire  c$o_sensorcontrol_case_alt_24_selection_res;
  wire [161:0] c$vecflat_194;
  wire  c$o_sensorcontrol_case_alt_26_selection_res;
  wire [161:0] c$vecflat_195;
  wire [161:0] c$vecflat_196;
  wire  result_177_selection_res;
  wire  result_178_selection_res;
  wire  result_179_selection_res;
  wire  result_180_selection_res;
  wire [111:0] c$vecflat_197;
  wire  c$o_regmanage_case_alt_16_selection_res;
  wire [3:0] c$vecflat_198;
  wire [3:0] c$vecflat_199;
  wire [143:0] c$vecflat_200;
  wire  c$o_sensorcontrol_case_alt_30_selection_res;
  wire [2:0] c$vecflat_201;
  wire  c$o_status_case_alt_8_selection_res;
  wire [111:0] c$vecflat_202;
  wire  c$o_regmanage_case_alt_18_selection_res;
  wire [143:0] c$vecflat_203;
  wire  c$o_sensorcontrol_case_alt_32_selection_res;
  wire [2:0] c$vecflat_204;
  wire [2:0] c$vecflat_205;
  wire [111:0] c$vecflat_206;
  wire  c$o_regmanage_case_alt_20_selection_res;
  wire [143:0] c$vecflat_207;
  wire  c$o_sensorcontrol_case_alt_34_selection_res;
  wire [111:0] c$vecflat_208;
  wire  c$o_regmanage_case_alt_22_selection_res;
  wire [143:0] c$vecflat_209;
  wire  c$o_sensorcontrol_case_alt_36_selection_res;
  wire [111:0] c$vecflat_210;
  wire  c$o_regmanage_case_alt_24_selection_res;
  wire [143:0] c$vecflat_211;
  wire  c$o_sensorcontrol_case_alt_38_selection_res;
  wire [111:0] c$vecflat_212;
  wire  c$o_regmanage_case_alt_26_selection_res;
  wire [143:0] c$vecflat_213;
  wire  c$o_sensorcontrol_case_alt_40_selection_res;
  wire [111:0] c$vecflat_214;
  wire [111:0] c$vecflat_215;
  wire [143:0] c$vecflat_216;
  wire [143:0] c$vecflat_217;
  wire  result_184_selection_res;
  wire  result_185_selection_res;
  wire  result_186_selection_res;
  wire  result_187_selection_res;
  wire [111:0] c$vecflat_218;
  wire  c$o_regmanage_case_alt_30_selection_res;
  wire [3:0] c$vecflat_219;
  wire [3:0] c$vecflat_220;
  wire [143:0] c$vecflat_221;
  wire  c$o_sensorcontrol_case_alt_44_selection_res;
  wire [2:0] c$vecflat_222;
  wire  c$o_status_case_alt_12_selection_res;
  wire [111:0] c$vecflat_223;
  wire  c$o_regmanage_case_alt_32_selection_res;
  wire [143:0] c$vecflat_224;
  wire  c$o_sensorcontrol_case_alt_46_selection_res;
  wire [2:0] c$vecflat_225;
  wire [2:0] c$vecflat_226;
  wire [111:0] c$vecflat_227;
  wire  c$o_regmanage_case_alt_34_selection_res;
  wire [143:0] c$vecflat_228;
  wire  c$o_sensorcontrol_case_alt_48_selection_res;
  wire [111:0] c$vecflat_229;
  wire  c$o_regmanage_case_alt_36_selection_res;
  wire [143:0] c$vecflat_230;
  wire  c$o_sensorcontrol_case_alt_50_selection_res;
  wire [111:0] c$vecflat_231;
  wire  c$o_regmanage_case_alt_38_selection_res;
  wire [143:0] c$vecflat_232;
  wire  c$o_sensorcontrol_case_alt_52_selection_res;
  wire [111:0] c$vecflat_233;
  wire  c$o_regmanage_case_alt_40_selection_res;
  wire [143:0] c$vecflat_234;
  wire  c$o_sensorcontrol_case_alt_54_selection_res;
  wire [111:0] c$vecflat_235;
  wire [111:0] c$vecflat_236;
  wire [143:0] c$vecflat_237;
  wire [143:0] c$vecflat_238;
  wire  result_190_selection_res;
  wire [23:0] c$vecflat_239;
  wire  c$o_partcontrol_case_alt_0_selection_res;
  wire [23:0] c$vecflat_240;
  wire  c$o_partcontrol_case_alt_2_selection_res;
  wire [23:0] c$vecflat_241;
  wire  c$o_partcontrol_case_alt_4_selection_res;
  wire [23:0] c$vecflat_242;
  wire  c$o_partcontrol_case_alt_6_selection_res;
  wire [23:0] c$vecflat_243;
  wire [23:0] c$vecflat_244;
  wire  c$dt_case_alt_3_selection_res;
  wire [7:0] c$bv_10;
  wire  c$dt_case_alt_4_selection_res;
  wire [7:0] c$bv_11;
  wire  c$dt_case_alt_5_selection_res;
  wire [7:0] c$bv_12;
  wire  c$dt_case_alt_6_selection_res;
  wire [7:0] c$bv_13;
  wire  c$dt_case_alt_7_selection_res;
  wire [7:0] c$bv_14;
  wire  c$dt_case_alt_8_selection_res;
  wire [7:0] c$bv_15;
  wire  c$dt_case_alt_9_selection_res;
  wire [7:0] c$bv_16;
  wire  c$dt_case_alt_10_selection_res;
  wire [7:0] c$bv_17;
  wire  c$dt_case_alt_11_selection_res;
  wire [7:0] c$bv_18;
  wire  c$dt_case_alt_12_selection_res;
  wire [7:0] c$bv_19;
  wire  c$dt_case_alt_13_selection_res;
  wire [7:0] c$bv_20;
  wire  c$dt_case_alt_14_selection_res;
  wire [7:0] c$bv_21;
  wire  c$dt_case_alt_15_selection_res;
  wire [7:0] c$bv_22;
  wire  c$dt_case_alt_16_selection_res;
  wire [7:0] c$bv_23;
  wire  c$dt_case_alt_17_selection_res;
  wire [7:0] c$bv_24;
  wire  c$dt_case_alt_18_selection_res;
  wire [7:0] c$bv_25;
  wire [3:0] c$vecflat_245;
  wire [3:0] c$vecflat_246;
  wire  c$o_sdi_case_alt_1_selection_res;
  wire [3:0] c$vecflat_247;
  wire  c$o_sdi_case_alt_3_selection_res;
  wire [3:0] c$vecflat_248;
  wire  result_202_selection_res;
  wire  result_203_selection_res;
  wire [2:0] c$vecflat_249;
  wire  c$o_spc_case_alt_0_selection_res;
  wire [2:0] c$vecflat_250;
  wire [2:0] c$vecflat_251;
  wire [16:0] b_57_selection;
  wire [16:0] dt_126_selection;
  wire [16:0] dt_127_selection;
  wire [23:0] c$vecflat_252;
  wire [23:0] c$vecflat_253;
  wire [2:0] c$vecflat_254;
  wire [2:0] c$vecflat_255;
  wire [2:0] c$vecflat_256;
  wire [2:0] c$vecflat_257;
  wire [15:0] c$vecflat_258;
  wire [15:0] c$vecflat_259;
  wire  \c$_INTERNAL_.o_counter_case_alt_7_selection_res ;
  wire [23:0] c$vecflat_260;
  wire  c$o_cs_case_alt_1_selection_res;
  wire [2:0] c$vecflat_261;
  wire  c$o_finished_case_alt_1_selection_res;
  wire [2:0] c$vecflat_262;
  wire [15:0] c$vecflat_263;
  wire [15:0] c$vecflat_264;
  wire [15:0] c$vecflat_265;
  wire [15:0] c$vecflat_266;
  wire  result_221_selection_res;
  wire  result_222_selection_res;
  wire  result_223_selection_res;
  wire  result_224_selection_res;
  wire  result_225_selection_res;
  wire  result_226_selection_res;
  wire  result_229_selection_res;
  wire [2:0] c$vecflat_267;
  wire  c$o_sdi_case_alt_6_selection_res;
  wire [2:0] c$vecflat_268;
  wire [2:0] c$vecflat_269;
  wire  c$dt_case_alt_19_selection_res;
  wire [7:0] c$bv_26;
  wire  c$dt_case_alt_20_selection_res;
  wire [7:0] c$bv_27;
  wire  c$dt_case_alt_21_selection_res;
  wire [7:0] c$bv_28;
  wire  c$dt_case_alt_22_selection_res;
  wire [7:0] c$bv_29;
  wire  c$dt_case_alt_23_selection_res;
  wire [7:0] c$bv_30;
  wire  c$dt_case_alt_24_selection_res;
  wire [7:0] c$bv_31;
  wire  c$dt_case_alt_25_selection_res;
  wire [7:0] c$bv_32;
  wire  c$dt_case_alt_26_selection_res;
  wire [7:0] c$bv_33;
  wire  result_238_selection_res;
  wire [2:0] c$vecflat_270;
  wire  c$o_spc_case_alt_4_selection_res;
  wire [2:0] c$vecflat_271;
  wire [2:0] c$vecflat_272;
  wire  result_245_selection_res;
  wire  result_246_selection_res;
  wire  result_247_selection_res;
  wire  result_248_selection_res;
  wire  result_249_selection_res;
  wire  result_250_selection_res;
  wire [26:0] c$vecflat_273;
  wire  c$o_readdata_case_alt_0_selection_res;
  wire [23:0] c$vecflat_274;
  wire  \c$_INTERNAL_.o_readdatatemp_case_alt_0_selection_res ;
  wire [15:0] c$vecflat_275;
  wire [15:0] c$vecflat_276;
  wire [2:0] c$vecflat_277;
  wire  c$o_cs_case_alt_4_selection_res;
  wire [23:0] c$vecflat_278;
  wire  \c$_INTERNAL_.o_counter_case_alt_10_selection_res ;
  wire [15:0] c$vecflat_279;
  wire [15:0] c$vecflat_280;
  wire [26:0] c$vecflat_281;
  wire [26:0] c$vecflat_282;
  wire [23:0] c$vecflat_283;
  wire [23:0] c$vecflat_284;
  wire [2:0] c$vecflat_285;
  wire [2:0] c$vecflat_286;
  wire [23:0] c$vecflat_287;
  wire [23:0] c$vecflat_288;
  wire [8:0] dt_137_selection;
  wire [8:0] b_79_selection;
  wire  result_262_selection_res;
  wire  result_263_selection_res;
  wire  result_264_selection_res;
  wire  result_265_selection_res;
  wire  result_266_selection_res;
  wire [71:0] c$vecflat_289;
  wire  c$o_output_case_alt_0_selection_res;
  wire [50:0] c$vecflat_290;
  wire  c$o_spiWriteCtrl_case_alt_0_selection_res;
  wire [26:0] c$vecflat_291;
  wire  c$o_spiReadCtrl_case_alt_0_selection_res;
  wire [35:0] c$vecflat_292;
  wire [35:0] c$vecflat_293;
  wire [11:0] c$vecflat_294;
  wire  c$o_sensorOut_case_alt_0_selection_res;
  wire [71:0] c$vecflat_295;
  wire  c$o_output_case_alt_2_selection_res;
  wire [50:0] c$vecflat_296;
  wire [50:0] c$vecflat_297;
  wire [26:0] c$vecflat_298;
  wire [26:0] c$vecflat_299;
  wire [11:0] c$vecflat_300;
  wire  c$o_sensorOut_case_alt_2_selection_res;
  wire [71:0] c$vecflat_301;
  wire [71:0] c$vecflat_302;
  wire [11:0] c$vecflat_303;
  wire [11:0] c$vecflat_304;
  wire  result_273_selection_res;
  wire  result_274_selection_res;
  wire  result_275_selection_res;
  wire [89:0] c$vecflat_305;
  wire  c$o_command_case_alt_0_selection_res;
  wire [69:0] c$vecflat_306;
  wire  c$o_managerctrl_case_alt_0_selection_res;
  wire [9:0] c$vecflat_307;
  wire  c$o_sensorType_case_alt_10_selection_res;
  wire [89:0] c$vecflat_308;
  wire  c$o_command_case_alt_2_selection_res;
  wire [69:0] c$vecflat_309;
  wire  c$o_managerctrl_case_alt_2_selection_res;
  wire [9:0] c$vecflat_310;
  wire  c$o_sensorType_case_alt_12_selection_res;
  wire [89:0] c$vecflat_311;
  wire  c$o_command_case_alt_4_selection_res;
  wire [69:0] c$vecflat_312;
  wire  c$o_managerctrl_case_alt_4_selection_res;
  wire [9:0] c$vecflat_313;
  wire  c$o_sensorType_case_alt_14_selection_res;
  wire [89:0] c$vecflat_314;
  wire [89:0] c$vecflat_315;
  wire [69:0] c$vecflat_316;
  wire [69:0] c$vecflat_317;
  wire [9:0] c$vecflat_318;
  wire [9:0] c$vecflat_319;
  wire  result_279_selection_res;
  wire  result_280_selection_res;
  wire  result_281_selection_res;
  wire  result_282_selection_res;
  wire  result_283_selection_res;
  wire  result_284_selection_res;
  wire  result_285_selection_res;
  wire  result_286_selection_res;
  wire  result_287_selection_res;
  wire  result_288_selection_res;
  wire [1:0] c$vecflat_320;
  wire [1:0] c$vecflat_321;
  wire [2:0] c$vecflat_322;
  wire  \c$_INTERNAL_.o_csAG_case_alt_0_selection_res ;
  wire [1:0] c$vecflat_323;
  wire [1:0] c$vecflat_324;
  wire [2:0] c$vecflat_325;
  wire  \c$_INTERNAL_.o_csAlt_case_alt_0_selection_res ;
  wire [1:0] c$vecflat_326;
  wire [1:0] c$vecflat_327;
  wire [2:0] c$vecflat_328;
  wire  \c$_INTERNAL_.o_csMag_case_alt_0_selection_res ;
  wire [1:0] c$vecflat_329;
  wire [1:0] c$vecflat_330;
  wire [2:0] c$vecflat_331;
  wire  \c$_INTERNAL_.o_sdi_case_alt_0_selection_res ;
  wire [1:0] c$vecflat_332;
  wire [1:0] c$vecflat_333;
  wire [2:0] c$vecflat_334;
  wire  \c$_INTERNAL_.o_spc_case_alt_0_selection_res ;
  wire [2:0] c$vecflat_335;
  wire [2:0] c$vecflat_336;
  wire [2:0] c$vecflat_337;
  wire [2:0] c$vecflat_338;
  wire [2:0] c$vecflat_339;
  wire [2:0] c$vecflat_340;
  wire [2:0] c$vecflat_341;
  wire [2:0] c$vecflat_342;
  wire [2:0] c$vecflat_343;
  wire [2:0] c$vecflat_344;
  wire [31:0] c$vecflat_345;
  wire [31:0] c$vecflat_346;
  wire  result_295_selection_res;
  wire [1:0] c$bv_34;
  wire [31:0] c$vecflat_347;
  wire [31:0] c$vecflat_348;
  wire  result_298_selection_res;
  wire [1:0] c$bv_35;
  wire [31:0] c$vecflat_349;
  wire [31:0] c$vecflat_350;
  wire  result_301_selection_res;
  wire [1:0] c$bv_36;
  wire [31:0] c$vecflat_351;
  wire [31:0] c$vecflat_352;
  wire  result_304_selection_res;
  wire [1:0] c$bv_37;
  wire [31:0] c$vecflat_353;
  wire [31:0] c$vecflat_354;
  wire  result_307_selection_res;
  wire [1:0] c$bv_38;
  wire [31:0] c$vecflat_355;
  wire [31:0] c$vecflat_356;
  wire  result_310_selection_res;
  wire [1:0] c$bv_39;
  wire [31:0] c$vecflat_357;
  wire [31:0] c$vecflat_358;
  wire  result_313_selection_res;
  wire [1:0] c$bv_40;
  wire  result_315_selection_res;
  wire  result_316_selection_res;
  wire  result_317_selection_res;
  wire [47:0] c$vecflat_359;
  wire  c$o_fullreg_case_alt_0_selection_res;
  wire [15:0] c$vecflat_360;
  wire [15:0] c$vecflat_361;
  wire [11:0] c$vecflat_362;
  wire  c$o_regname_case_alt_0_selection_res;
  wire [47:0] c$vecflat_363;
  wire [47:0] c$vecflat_364;
  wire [11:0] c$vecflat_365;
  wire [11:0] c$vecflat_366;
  wire [13:0] w6_4_selection;
  wire [13:0] dt_178_selection;
  wire [13:0] b_95_selection;
  wire [13:0] b_96_selection;
  wire [31:0] c$vecflat_367;
  wire [31:0] c$vecflat_368;
  wire  result_323_selection_res;
  wire [1:0] c$bv_41;
  wire [31:0] c$vecflat_369;
  wire [31:0] c$vecflat_370;
  wire  result_326_selection_res;
  wire [1:0] c$bv_42;
  wire  wrM_0_selection_res;
  wire [32:0] result;

  assign \$d(%,%)  = {CLOCK,RESET};

  // register begin
  reg  c$ds1_app_arg_reg = 1'b0;
  always @(posedge \$d(%,%) [1:1] or posedge \$d(%,%) [0:0]) begin : c$ds1_app_arg_register
    if (\$d(%,%) [0:0]) begin
      c$ds1_app_arg_reg <= 1'b0;
    end else begin
      c$ds1_app_arg_reg <= 1'b1;
    end
  end
  assign c$ds1_app_arg = c$ds1_app_arg_reg;
  // register end

  assign b = ds1[0:0];

  assign ds1 = {result_126[0:0],c$ds1_app_arg};

  assign a = ds1[1:1];

  assign c$initalCounter_app_arg_selection_res = initalCounter < 27'd67108864;

  always @(*) begin
    if(c$initalCounter_app_arg_selection_res)
      c$initalCounter_app_arg = initalCounter + 27'd1;
    else
      c$initalCounter_app_arg = initalCounter;
  end

  always @(*) begin
    if(a)
      c$tup_case_alt = 1'b1;
    else
      c$tup_case_alt = ~ b;
  end

  // register begin
  reg [26:0] initalCounter_reg = 27'd0;
  always @(posedge \$d(%,%) [1:1] or posedge \$d(%,%) [0:0]) begin : initalCounter_register
    if (\$d(%,%) [0:0]) begin
      initalCounter_reg <= 27'd0;
    end else begin
      initalCounter_reg <= c$initalCounter_app_arg;
    end
  end
  assign initalCounter = initalCounter_reg;
  // register end

  assign shot = result_126[1:1];

  assign enemies = result_42[78:3];

  assign rotation = result_126[9:2];

  assign x = result_18[63:60];

  assign scrut3 = scrut2[9-1 : 0];

  assign scrut2 = scrut1[18-1 : 0];

  assign scrut1 = scrut[27-1 : 0];

  assign c$vec = (result_18[51:16]);

  // map begin
  genvar i_0;
  generate
  for (i_0=0; i_0 < 4; i_0 = i_0 + 1) begin : map
    wire [8:0] map_in;
    assign map_in = c$vec[i_0*9+:9];
    wire [8:0] map_out;
      assign map_out = {map_in[8:8]
                       ,map_in[7:0]};
    assign scrut[i_0*9+:9] = map_out;
  end
  endgenerate
  // map end

  assign scrut3_0 = scrut2_0[1-1 : 0];

  assign scrut2_0 = scrut1_0[2-1 : 0];

  assign scrut1_0 = x[3-1 : 0];

  assign c$ds1_case_scrut = scrut3[9-1 -: 9];

  assign c$ds1_case_scrut_0 = scrut2[18-1 -: 9];

  assign c$ds1_case_scrut_1 = scrut1[27-1 -: 9];

  assign c$ds1_case_scrut_2 = scrut[36-1 -: 9];

  assign a4 = c$ds1_case_scrut[7:0];

  assign r4 = c$ds1_case_scrut[8:8];

  assign a3 = c$ds1_case_scrut_0[7:0];

  assign ramreqsine = c$ds1_case_scrut_0[8:8];

  assign a2 = c$ds1_case_scrut_1[7:0];

  assign r2 = c$ds1_case_scrut_1[8:8];

  assign a1 = c$ds1_case_scrut_2[7:0];

  assign r1 = c$ds1_case_scrut_2[8:8];

  assign result_0 = {c$app_arg_0
                    ,c$app_arg
                    ,result_1[10:8]};

  // register begin
  reg [7:0] c$app_arg_reg = 8'd255;
  always @(posedge \$d(%,%) [1:1] or posedge \$d(%,%) [0:0]) begin : c$app_arg_register
    if (\$d(%,%) [0:0]) begin
      c$app_arg_reg <= 8'd255;
    end else begin
      c$app_arg_reg <= result_1[7:0];
    end
  end
  assign c$app_arg = c$app_arg_reg;
  // register end

  // register begin
  reg [7:0] c$app_arg_0_reg = 8'd16;
  always @(posedge \$d(%,%) [1:1] or posedge \$d(%,%) [0:0]) begin : c$app_arg_0_register
    if (\$d(%,%) [0:0]) begin
      c$app_arg_0_reg <= 8'd16;
    end else begin
      c$app_arg_0_reg <= result_1[18:11];
    end
  end
  assign c$app_arg_0 = c$app_arg_0_reg;
  // register end

  assign result_1 = {result_2,result_3,result_4};

  assign result_2_selection_res = (bs[(64'sd0)]) == (1'b1);

  always @(*) begin
    if(result_2_selection_res)
      result_2 = c$o_angle_case_alt;
    else
      result_2 = c$o_angle_case_alt_0;
  end

  assign result_3_selection_res = (bs_0[(64'sd0)]) == (1'b1);

  always @(*) begin
    if(result_3_selection_res)
      result_3 = c$o_color_case_alt;
    else
      result_3 = c$o_color_case_alt_0;
  end

  assign result_4_selection_res = (bs_1[(64'sd0)]) == (1'b1);

  always @(*) begin
    if(result_4_selection_res)
      result_4 = \c$_INTERNAL_.o_radius_case_alt ;
    else
      result_4 = \c$_INTERNAL_.o_radius_case_alt_0 ;
  end

  assign c$vecflat = {dt,dt_0};

  // index begin
  wire [7:0] vec [0:2-1];

  genvar i_1;
  generate
  for (i_1=0; i_1 < 2; i_1=i_1+1) begin : mk_array
    assign vec[(2-1)-i_1] = c$vecflat[i_1*8+:8];
  end
  endgenerate

  assign c$o_angle_case_alt = vec[(64'sd1)];
  // index end

  assign c$vecflat_0 = {dt,dt_0};

  // index begin
  wire [7:0] vec_0 [0:2-1];

  genvar i_2;
  generate
  for (i_2=0; i_2 < 2; i_2=i_2+1) begin : mk_array_0
    assign vec_0[(2-1)-i_2] = c$vecflat_0[i_2*8+:8];
  end
  endgenerate

  assign c$o_angle_case_alt_0 = vec_0[(64'sd0)];
  // index end

  assign c$vecflat_1 = {dt_1,3'b001};

  // index begin
  wire [2:0] vec_1 [0:2-1];

  genvar i_3;
  generate
  for (i_3=0; i_3 < 2; i_3=i_3+1) begin : mk_array_1
    assign vec_1[(2-1)-i_3] = c$vecflat_1[i_3*3+:3];
  end
  endgenerate

  assign c$o_color_case_alt = vec_1[(64'sd1)];
  // index end

  assign c$vecflat_2 = {dt_1,3'b001};

  // index begin
  wire [2:0] vec_2 [0:2-1];

  genvar i_4;
  generate
  for (i_4=0; i_4 < 2; i_4=i_4+1) begin : mk_array_2
    assign vec_2[(2-1)-i_4] = c$vecflat_2[i_4*3+:3];
  end
  endgenerate

  assign c$o_color_case_alt_0 = vec_2[(64'sd0)];
  // index end

  assign c$vecflat_3 = {c_radius,8'd255,dt_2};

  // index begin
  wire [7:0] vec_3 [0:3-1];

  genvar i_5;
  generate
  for (i_5=0; i_5 < 3; i_5=i_5+1) begin : mk_array_3
    assign vec_3[(3-1)-i_5] = c$vecflat_3[i_5*8+:8];
  end
  endgenerate

  assign \c$_INTERNAL_.o_radius_case_alt  = vec_3[(64'sd2)];
  // index end

  assign \c$_INTERNAL_.o_radius_case_alt_0_selection_res  = (bs_1[(64'sd1)]) == (1'b1);

  always @(*) begin
    if(\c$_INTERNAL_.o_radius_case_alt_0_selection_res )
      \c$_INTERNAL_.o_radius_case_alt_0  = \c$_INTERNAL_.o_radius_case_alt_1 ;
    else
      \c$_INTERNAL_.o_radius_case_alt_0  = \c$_INTERNAL_.o_radius_case_alt_2 ;
  end

  assign c$vecflat_4 = {c_radius,8'd255,dt_2};

  // index begin
  wire [7:0] vec_4 [0:3-1];

  genvar i_6;
  generate
  for (i_6=0; i_6 < 3; i_6=i_6+1) begin : mk_array_4
    assign vec_4[(3-1)-i_6] = c$vecflat_4[i_6*8+:8];
  end
  endgenerate

  assign \c$_INTERNAL_.o_radius_case_alt_1  = vec_4[(64'sd1)];
  // index end

  assign c$vecflat_5 = {c_radius,8'd255,dt_2};

  // index begin
  wire [7:0] vec_5 [0:3-1];

  genvar i_7;
  generate
  for (i_7=0; i_7 < 3; i_7=i_7+1) begin : mk_array_5
    assign vec_5[(3-1)-i_7] = c$vecflat_5[i_7*8+:8];
  end
  endgenerate

  assign \c$_INTERNAL_.o_radius_case_alt_2  = vec_5[(64'sd0)];
  // index end

  assign bs = {((result_5[(64'sd0)])),((result_5[(64'sd1)]))};

  assign bs_0 = {((result_5[(64'sd2)])),((result_5[(64'sd3)]))};

  assign bs_1 = {((result_5[(64'sd4)])),({((result_5[(64'sd5)])),((result_5[(64'sd6)]))})};

  // register begin
  reg [7:0] c_radius_reg = 8'd255;
  always @(posedge \$d(%,%) [1:1] or posedge \$d(%,%) [0:0]) begin : c_radius_register
    if (\$d(%,%) [0:0]) begin
      c_radius_reg <= 8'd255;
    end else begin
      c_radius_reg <= result_4;
    end
  end
  assign c_radius = c_radius_reg;
  // register end

  // register begin
  reg [7:0] dt_reg = 8'd0;
  always @(posedge \$d(%,%) [1:1] or posedge \$d(%,%) [0:0]) begin : dt_register
    if (\$d(%,%) [0:0]) begin
      dt_reg <= 8'd0;
    end else begin
      dt_reg <= result_2;
    end
  end
  assign dt = dt_reg;
  // register end

  assign dt_0 = a4;

  // register begin
  reg [2:0] dt_1_reg = 3'b000;
  always @(posedge \$d(%,%) [1:1] or posedge \$d(%,%) [0:0]) begin : dt_1_register
    if (\$d(%,%) [0:0]) begin
      dt_1_reg <= 3'b000;
    end else begin
      dt_1_reg <= result_3;
    end
  end
  assign dt_1 = dt_1_reg;
  // register end

  assign result_5 = {((c$cout_app_arg_2 & c$cout_app_arg_0)),({c$cout_app_arg_1,({((c$cout_app_arg_2 & (~ c$cout_app_arg_0))),({1'b1,({1'b0,({c$cout_app_arg_1,(c$cout_app_arg_2)})})})})})};

  assign dt_2 = c_radius - 8'd1;

  assign c$cout_app_arg = cin[(64'sd1)];

  assign c$cout_app_arg_0 = cin[(64'sd0)];

  assign cin = {c$cin_app_arg_0,c$cin_app_arg};

  always @(*) begin
    if(clock)
      c$cin_app_arg = 1'b1;
    else
      c$cin_app_arg = 1'b0;
  end

  always @(*) begin
    if(r4)
      c$cin_app_arg_0 = 1'b1;
    else
      c$cin_app_arg_0 = 1'b0;
  end

  assign c$cout_app_arg_1 = c$cout_app_arg;

  assign c$cout_app_arg_2 = ~ c$cout_app_arg;

  assign clock = scrut3_0[1-1 -: 1];

  assign enemies4 = result_0;

  assign result_6 = {c$app_arg_2
                    ,c$app_arg_1
                    ,result_7[10:8]};

  // register begin
  reg [7:0] c$app_arg_1_reg = 8'd255;
  always @(posedge \$d(%,%) [1:1] or posedge \$d(%,%) [0:0]) begin : c$app_arg_1_register
    if (\$d(%,%) [0:0]) begin
      c$app_arg_1_reg <= 8'd255;
    end else begin
      c$app_arg_1_reg <= result_7[7:0];
    end
  end
  assign c$app_arg_1 = c$app_arg_1_reg;
  // register end

  // register begin
  reg [7:0] c$app_arg_2_reg = 8'd16;
  always @(posedge \$d(%,%) [1:1] or posedge \$d(%,%) [0:0]) begin : c$app_arg_2_register
    if (\$d(%,%) [0:0]) begin
      c$app_arg_2_reg <= 8'd16;
    end else begin
      c$app_arg_2_reg <= result_7[18:11];
    end
  end
  assign c$app_arg_2 = c$app_arg_2_reg;
  // register end

  assign result_7 = {result_8,result_9,result_10};

  assign result_8_selection_res = (bs_2[(64'sd0)]) == (1'b1);

  always @(*) begin
    if(result_8_selection_res)
      result_8 = c$o_angle_case_alt_1;
    else
      result_8 = c$o_angle_case_alt_2;
  end

  assign result_9_selection_res = (bs_3[(64'sd0)]) == (1'b1);

  always @(*) begin
    if(result_9_selection_res)
      result_9 = c$o_color_case_alt_1;
    else
      result_9 = c$o_color_case_alt_2;
  end

  assign result_10_selection_res = (bs_4[(64'sd0)]) == (1'b1);

  always @(*) begin
    if(result_10_selection_res)
      result_10 = \c$_INTERNAL_.o_radius_case_alt_3 ;
    else
      result_10 = \c$_INTERNAL_.o_radius_case_alt_4 ;
  end

  assign c$vecflat_6 = {dt_3,dt_4};

  // index begin
  wire [7:0] vec_6 [0:2-1];

  genvar i_8;
  generate
  for (i_8=0; i_8 < 2; i_8=i_8+1) begin : mk_array_6
    assign vec_6[(2-1)-i_8] = c$vecflat_6[i_8*8+:8];
  end
  endgenerate

  assign c$o_angle_case_alt_1 = vec_6[(64'sd1)];
  // index end

  assign c$vecflat_7 = {dt_3,dt_4};

  // index begin
  wire [7:0] vec_7 [0:2-1];

  genvar i_9;
  generate
  for (i_9=0; i_9 < 2; i_9=i_9+1) begin : mk_array_7
    assign vec_7[(2-1)-i_9] = c$vecflat_7[i_9*8+:8];
  end
  endgenerate

  assign c$o_angle_case_alt_2 = vec_7[(64'sd0)];
  // index end

  assign c$vecflat_8 = {dt_5,3'b110};

  // index begin
  wire [2:0] vec_8 [0:2-1];

  genvar i_10;
  generate
  for (i_10=0; i_10 < 2; i_10=i_10+1) begin : mk_array_8
    assign vec_8[(2-1)-i_10] = c$vecflat_8[i_10*3+:3];
  end
  endgenerate

  assign c$o_color_case_alt_1 = vec_8[(64'sd1)];
  // index end

  assign c$vecflat_9 = {dt_5,3'b110};

  // index begin
  wire [2:0] vec_9 [0:2-1];

  genvar i_11;
  generate
  for (i_11=0; i_11 < 2; i_11=i_11+1) begin : mk_array_9
    assign vec_9[(2-1)-i_11] = c$vecflat_9[i_11*3+:3];
  end
  endgenerate

  assign c$o_color_case_alt_2 = vec_9[(64'sd0)];
  // index end

  assign c$vecflat_10 = {c_radius_0,8'd255,dt_6};

  // index begin
  wire [7:0] vec_10 [0:3-1];

  genvar i_12;
  generate
  for (i_12=0; i_12 < 3; i_12=i_12+1) begin : mk_array_10
    assign vec_10[(3-1)-i_12] = c$vecflat_10[i_12*8+:8];
  end
  endgenerate

  assign \c$_INTERNAL_.o_radius_case_alt_3  = vec_10[(64'sd2)];
  // index end

  assign \c$_INTERNAL_.o_radius_case_alt_4_selection_res  = (bs_4[(64'sd1)]) == (1'b1);

  always @(*) begin
    if(\c$_INTERNAL_.o_radius_case_alt_4_selection_res )
      \c$_INTERNAL_.o_radius_case_alt_4  = \c$_INTERNAL_.o_radius_case_alt_5 ;
    else
      \c$_INTERNAL_.o_radius_case_alt_4  = \c$_INTERNAL_.o_radius_case_alt_6 ;
  end

  assign c$vecflat_11 = {c_radius_0,8'd255,dt_6};

  // index begin
  wire [7:0] vec_11 [0:3-1];

  genvar i_13;
  generate
  for (i_13=0; i_13 < 3; i_13=i_13+1) begin : mk_array_11
    assign vec_11[(3-1)-i_13] = c$vecflat_11[i_13*8+:8];
  end
  endgenerate

  assign \c$_INTERNAL_.o_radius_case_alt_5  = vec_11[(64'sd1)];
  // index end

  assign c$vecflat_12 = {c_radius_0,8'd255,dt_6};

  // index begin
  wire [7:0] vec_12 [0:3-1];

  genvar i_14;
  generate
  for (i_14=0; i_14 < 3; i_14=i_14+1) begin : mk_array_12
    assign vec_12[(3-1)-i_14] = c$vecflat_12[i_14*8+:8];
  end
  endgenerate

  assign \c$_INTERNAL_.o_radius_case_alt_6  = vec_12[(64'sd0)];
  // index end

  assign bs_2 = {((result_11[(64'sd0)])),((result_11[(64'sd1)]))};

  assign bs_3 = {((result_11[(64'sd2)])),((result_11[(64'sd3)]))};

  assign bs_4 = {((result_11[(64'sd4)])),({((result_11[(64'sd5)])),((result_11[(64'sd6)]))})};

  // register begin
  reg [7:0] c_radius_0_reg = 8'd255;
  always @(posedge \$d(%,%) [1:1] or posedge \$d(%,%) [0:0]) begin : c_radius_0_register
    if (\$d(%,%) [0:0]) begin
      c_radius_0_reg <= 8'd255;
    end else begin
      c_radius_0_reg <= result_10;
    end
  end
  assign c_radius_0 = c_radius_0_reg;
  // register end

  // register begin
  reg [7:0] dt_3_reg = 8'd0;
  always @(posedge \$d(%,%) [1:1] or posedge \$d(%,%) [0:0]) begin : dt_3_register
    if (\$d(%,%) [0:0]) begin
      dt_3_reg <= 8'd0;
    end else begin
      dt_3_reg <= result_8;
    end
  end
  assign dt_3 = dt_3_reg;
  // register end

  assign dt_4 = a3;

  // register begin
  reg [2:0] dt_5_reg = 3'b000;
  always @(posedge \$d(%,%) [1:1] or posedge \$d(%,%) [0:0]) begin : dt_5_register
    if (\$d(%,%) [0:0]) begin
      dt_5_reg <= 3'b000;
    end else begin
      dt_5_reg <= result_9;
    end
  end
  assign dt_5 = dt_5_reg;
  // register end

  assign result_11 = {((c$cout_app_arg_6 & c$cout_app_arg_4)),({c$cout_app_arg_5,({((c$cout_app_arg_6 & (~ c$cout_app_arg_4))),({1'b1,({1'b0,({c$cout_app_arg_5,(c$cout_app_arg_6)})})})})})};

  assign dt_6 = c_radius_0 - 8'd1;

  assign c$cout_app_arg_3 = cin_0[(64'sd1)];

  assign c$cout_app_arg_4 = cin_0[(64'sd0)];

  assign cin_0 = {c$cin_app_arg_2,c$cin_app_arg_1};

  always @(*) begin
    if(clock_0)
      c$cin_app_arg_1 = 1'b1;
    else
      c$cin_app_arg_1 = 1'b0;
  end

  always @(*) begin
    if(ramreqsine)
      c$cin_app_arg_2 = 1'b1;
    else
      c$cin_app_arg_2 = 1'b0;
  end

  assign c$cout_app_arg_5 = c$cout_app_arg_3;

  assign c$cout_app_arg_6 = ~ c$cout_app_arg_3;

  assign clock_0 = scrut2_0[2-1 -: 1];

  assign enemies5 = {result_6,enemies4};

  assign result_12 = {c$app_arg_4
                     ,c$app_arg_3
                     ,result_13[10:8]};

  // register begin
  reg [7:0] c$app_arg_3_reg = 8'd255;
  always @(posedge \$d(%,%) [1:1] or posedge \$d(%,%) [0:0]) begin : c$app_arg_3_register
    if (\$d(%,%) [0:0]) begin
      c$app_arg_3_reg <= 8'd255;
    end else begin
      c$app_arg_3_reg <= result_13[7:0];
    end
  end
  assign c$app_arg_3 = c$app_arg_3_reg;
  // register end

  // register begin
  reg [7:0] c$app_arg_4_reg = 8'd16;
  always @(posedge \$d(%,%) [1:1] or posedge \$d(%,%) [0:0]) begin : c$app_arg_4_register
    if (\$d(%,%) [0:0]) begin
      c$app_arg_4_reg <= 8'd16;
    end else begin
      c$app_arg_4_reg <= result_13[18:11];
    end
  end
  assign c$app_arg_4 = c$app_arg_4_reg;
  // register end

  assign result_13 = {result_14
                     ,result_15
                     ,result_16};

  assign result_14_selection_res = (bs_5[(64'sd0)]) == (1'b1);

  always @(*) begin
    if(result_14_selection_res)
      result_14 = c$o_angle_case_alt_3;
    else
      result_14 = c$o_angle_case_alt_4;
  end

  assign result_15_selection_res = (bs_6[(64'sd0)]) == (1'b1);

  always @(*) begin
    if(result_15_selection_res)
      result_15 = c$o_color_case_alt_3;
    else
      result_15 = c$o_color_case_alt_4;
  end

  assign result_16_selection_res = (bs_7[(64'sd0)]) == (1'b1);

  always @(*) begin
    if(result_16_selection_res)
      result_16 = \c$_INTERNAL_.o_radius_case_alt_7 ;
    else
      result_16 = \c$_INTERNAL_.o_radius_case_alt_8 ;
  end

  assign c$vecflat_13 = {dt_7,dt_8};

  // index begin
  wire [7:0] vec_13 [0:2-1];

  genvar i_15;
  generate
  for (i_15=0; i_15 < 2; i_15=i_15+1) begin : mk_array_13
    assign vec_13[(2-1)-i_15] = c$vecflat_13[i_15*8+:8];
  end
  endgenerate

  assign c$o_angle_case_alt_3 = vec_13[(64'sd1)];
  // index end

  assign c$vecflat_14 = {dt_7,dt_8};

  // index begin
  wire [7:0] vec_14 [0:2-1];

  genvar i_16;
  generate
  for (i_16=0; i_16 < 2; i_16=i_16+1) begin : mk_array_14
    assign vec_14[(2-1)-i_16] = c$vecflat_14[i_16*8+:8];
  end
  endgenerate

  assign c$o_angle_case_alt_4 = vec_14[(64'sd0)];
  // index end

  assign c$vecflat_15 = {dt_9,3'b010};

  // index begin
  wire [2:0] vec_15 [0:2-1];

  genvar i_17;
  generate
  for (i_17=0; i_17 < 2; i_17=i_17+1) begin : mk_array_15
    assign vec_15[(2-1)-i_17] = c$vecflat_15[i_17*3+:3];
  end
  endgenerate

  assign c$o_color_case_alt_3 = vec_15[(64'sd1)];
  // index end

  assign c$vecflat_16 = {dt_9,3'b010};

  // index begin
  wire [2:0] vec_16 [0:2-1];

  genvar i_18;
  generate
  for (i_18=0; i_18 < 2; i_18=i_18+1) begin : mk_array_16
    assign vec_16[(2-1)-i_18] = c$vecflat_16[i_18*3+:3];
  end
  endgenerate

  assign c$o_color_case_alt_4 = vec_16[(64'sd0)];
  // index end

  assign c$vecflat_17 = {c_radius_1,8'd255,dt_10};

  // index begin
  wire [7:0] vec_17 [0:3-1];

  genvar i_19;
  generate
  for (i_19=0; i_19 < 3; i_19=i_19+1) begin : mk_array_17
    assign vec_17[(3-1)-i_19] = c$vecflat_17[i_19*8+:8];
  end
  endgenerate

  assign \c$_INTERNAL_.o_radius_case_alt_7  = vec_17[(64'sd2)];
  // index end

  assign \c$_INTERNAL_.o_radius_case_alt_8_selection_res  = (bs_7[(64'sd1)]) == (1'b1);

  always @(*) begin
    if(\c$_INTERNAL_.o_radius_case_alt_8_selection_res )
      \c$_INTERNAL_.o_radius_case_alt_8  = \c$_INTERNAL_.o_radius_case_alt_9 ;
    else
      \c$_INTERNAL_.o_radius_case_alt_8  = \c$_INTERNAL_.o_radius_case_alt_10 ;
  end

  assign c$vecflat_18 = {c_radius_1,8'd255,dt_10};

  // index begin
  wire [7:0] vec_18 [0:3-1];

  genvar i_20;
  generate
  for (i_20=0; i_20 < 3; i_20=i_20+1) begin : mk_array_18
    assign vec_18[(3-1)-i_20] = c$vecflat_18[i_20*8+:8];
  end
  endgenerate

  assign \c$_INTERNAL_.o_radius_case_alt_9  = vec_18[(64'sd1)];
  // index end

  assign c$vecflat_19 = {c_radius_1,8'd255,dt_10};

  // index begin
  wire [7:0] vec_19 [0:3-1];

  genvar i_21;
  generate
  for (i_21=0; i_21 < 3; i_21=i_21+1) begin : mk_array_19
    assign vec_19[(3-1)-i_21] = c$vecflat_19[i_21*8+:8];
  end
  endgenerate

  assign \c$_INTERNAL_.o_radius_case_alt_10  = vec_19[(64'sd0)];
  // index end

  assign bs_5 = {((result_17[(64'sd0)])),((result_17[(64'sd1)]))};

  assign bs_6 = {((result_17[(64'sd2)])),((result_17[(64'sd3)]))};

  assign bs_7 = {((result_17[(64'sd4)])),({((result_17[(64'sd5)])),((result_17[(64'sd6)]))})};

  // register begin
  reg [7:0] c_radius_1_reg = 8'd255;
  always @(posedge \$d(%,%) [1:1] or posedge \$d(%,%) [0:0]) begin : c_radius_1_register
    if (\$d(%,%) [0:0]) begin
      c_radius_1_reg <= 8'd255;
    end else begin
      c_radius_1_reg <= result_16;
    end
  end
  assign c_radius_1 = c_radius_1_reg;
  // register end

  // register begin
  reg [7:0] dt_7_reg = 8'd0;
  always @(posedge \$d(%,%) [1:1] or posedge \$d(%,%) [0:0]) begin : dt_7_register
    if (\$d(%,%) [0:0]) begin
      dt_7_reg <= 8'd0;
    end else begin
      dt_7_reg <= result_14;
    end
  end
  assign dt_7 = dt_7_reg;
  // register end

  assign dt_8 = a2;

  // register begin
  reg [2:0] dt_9_reg = 3'b000;
  always @(posedge \$d(%,%) [1:1] or posedge \$d(%,%) [0:0]) begin : dt_9_register
    if (\$d(%,%) [0:0]) begin
      dt_9_reg <= 3'b000;
    end else begin
      dt_9_reg <= result_15;
    end
  end
  assign dt_9 = dt_9_reg;
  // register end

  assign result_17 = {((c$cout_app_arg_10 & c$cout_app_arg_8)),({c$cout_app_arg_9,({((c$cout_app_arg_10 & (~ c$cout_app_arg_8))),({1'b1,({1'b0,({c$cout_app_arg_9,(c$cout_app_arg_10)})})})})})};

  assign dt_10 = c_radius_1 - 8'd1;

  assign c$cout_app_arg_7 = cin_1[(64'sd1)];

  assign c$cout_app_arg_8 = cin_1[(64'sd0)];

  assign cin_1 = {c$cin_app_arg_4,c$cin_app_arg_3};

  always @(*) begin
    if(clock_1)
      c$cin_app_arg_3 = 1'b1;
    else
      c$cin_app_arg_3 = 1'b0;
  end

  always @(*) begin
    if(r2)
      c$cin_app_arg_4 = 1'b1;
    else
      c$cin_app_arg_4 = 1'b0;
  end

  assign c$cout_app_arg_9 = c$cout_app_arg_7;

  assign c$cout_app_arg_10 = ~ c$cout_app_arg_7;

  assign clock_1 = scrut1_0[3-1 -: 1];

  assign result_18 = {result_26
                     ,result_25
                     ,result_23
                     ,result_22
                     ,result_20
                     ,result_19
                     ,result_24
                     ,result_21
                     ,result_27};

  assign result_19_selection_res = (bs_8[(64'sd0)]) == (1'b1);

  always @(*) begin
    if(result_19_selection_res)
      result_19 = c$o_resets_case_alt;
    else
      result_19 = c$o_resets_case_alt_0;
  end

  assign result_20_selection_res = (bs_9[(64'sd0)]) == (1'b1);

  always @(*) begin
    if(result_20_selection_res)
      result_20 = \c$_INTERNAL_.o_newangle_case_alt ;
    else
      result_20 = \c$_INTERNAL_.o_newangle_case_alt_0 ;
  end

  assign result_21_selection_res = (bs_10[(64'sd0)]) == (1'b1);

  always @(*) begin
    if(result_21_selection_res)
      result_21 = c$o_scorecolor_case_alt;
    else
      result_21 = c$o_scorecolor_case_alt_0;
  end

  assign result_22_selection_res = (bs_11[(64'sd0)]) == (1'b1);

  always @(*) begin
    if(result_22_selection_res)
      result_22 = c$o_moveticks_case_alt;
    else
      result_22 = c$o_moveticks_case_alt_0;
  end

  assign result_23_selection_res = (bs_12[(64'sd0)]) == (1'b1);

  always @(*) begin
    if(result_23_selection_res)
      result_23 = \c$_INTERNAL_.o_movementclock_case_alt ;
    else
      result_23 = \c$_INTERNAL_.o_movementclock_case_alt_0 ;
  end

  assign result_24_selection_res = (bs_13[(64'sd0)]) == (1'b1);

  always @(*) begin
    if(result_24_selection_res)
      result_24 = \c$_INTERNAL_.o_score_case_alt ;
    else
      result_24 = \c$_INTERNAL_.o_score_case_alt_0 ;
  end

  assign result_25_selection_res = (bs_14[(64'sd0)]) == (1'b1);

  always @(*) begin
    if(result_25_selection_res)
      result_25 = c$o_gameover_case_alt;
    else
      result_25 = c$o_gameover_case_alt_0;
  end

  assign result_26_selection_res = (bs_15[(64'sd0)]) == (1'b1);

  always @(*) begin
    if(result_26_selection_res)
      result_26 = \c$_INTERNAL_.o_counter_case_alt ;
    else
      result_26 = \c$_INTERNAL_.o_counter_case_alt_0 ;
  end

  assign result_27_selection_res = (bs_16[(64'sd0)]) == (1'b1);

  always @(*) begin
    if(result_27_selection_res)
      result_27 = \c$_INTERNAL_.o_shotCounter_case_alt ;
    else
      result_27 = \c$_INTERNAL_.o_shotCounter_case_alt_0 ;
  end

  assign c$vecflat_20 = {dt_11
                        ,{{1'b0,8'd0}
                         ,{1'b0,8'd0}
                         ,{1'b0,8'd0}
                         ,{1'b0,8'd0}}
                        ,dt_17
                        ,dt_19};

  // index begin
  wire [35:0] vec_20 [0:4-1];

  genvar i_22;
  generate
  for (i_22=0; i_22 < 4; i_22=i_22+1) begin : mk_array_20
    assign vec_20[(4-1)-i_22] = c$vecflat_20[i_22*36+:36];
  end
  endgenerate

  assign c$o_resets_case_alt = vec_20[(64'sd3)];
  // index end

  assign c$o_resets_case_alt_0_selection_res = (bs_8[(64'sd1)]) == (1'b1);

  always @(*) begin
    if(c$o_resets_case_alt_0_selection_res)
      c$o_resets_case_alt_0 = c$o_resets_case_alt_1;
    else
      c$o_resets_case_alt_0 = c$o_resets_case_alt_2;
  end

  assign c$vecflat_21 = {c_newangle,dt_15};

  // index begin
  wire [7:0] vec_21 [0:2-1];

  genvar i_23;
  generate
  for (i_23=0; i_23 < 2; i_23=i_23+1) begin : mk_array_21
    assign vec_21[(2-1)-i_23] = c$vecflat_21[i_23*8+:8];
  end
  endgenerate

  assign \c$_INTERNAL_.o_newangle_case_alt  = vec_21[(64'sd1)];
  // index end

  assign c$vecflat_22 = {c_newangle,dt_15};

  // index begin
  wire [7:0] vec_22 [0:2-1];

  genvar i_24;
  generate
  for (i_24=0; i_24 < 2; i_24=i_24+1) begin : mk_array_22
    assign vec_22[(2-1)-i_24] = c$vecflat_22[i_24*8+:8];
  end
  endgenerate

  assign \c$_INTERNAL_.o_newangle_case_alt_0  = vec_22[(64'sd0)];
  // index end

  assign c$vecflat_23 = {dt_12,result_28};

  // index begin
  wire [2:0] vec_23 [0:2-1];

  genvar i_25;
  generate
  for (i_25=0; i_25 < 2; i_25=i_25+1) begin : mk_array_23
    assign vec_23[(2-1)-i_25] = c$vecflat_23[i_25*3+:3];
  end
  endgenerate

  assign c$o_scorecolor_case_alt = vec_23[(64'sd1)];
  // index end

  assign c$vecflat_24 = {dt_12,result_28};

  // index begin
  wire [2:0] vec_24 [0:2-1];

  genvar i_26;
  generate
  for (i_26=0; i_26 < 2; i_26=i_26+1) begin : mk_array_24
    assign vec_24[(2-1)-i_26] = c$vecflat_24[i_26*3+:3];
  end
  endgenerate

  assign c$o_scorecolor_case_alt_0 = vec_24[(64'sd0)];
  // index end

  assign c$vecflat_25 = {dt_13
                        ,{1'b0,1'b0,1'b0,1'b0}
                        ,c$dt_case_alt_0};

  // index begin
  wire [3:0] vec_25 [0:3-1];

  genvar i_27;
  generate
  for (i_27=0; i_27 < 3; i_27=i_27+1) begin : mk_array_25
    assign vec_25[(3-1)-i_27] = c$vecflat_25[i_27*4+:4];
  end
  endgenerate

  assign c$o_moveticks_case_alt = vec_25[(64'sd2)];
  // index end

  assign c$o_moveticks_case_alt_0_selection_res = (bs_11[(64'sd1)]) == (1'b1);

  always @(*) begin
    if(c$o_moveticks_case_alt_0_selection_res)
      c$o_moveticks_case_alt_0 = c$o_moveticks_case_alt_1;
    else
      c$o_moveticks_case_alt_0 = c$o_moveticks_case_alt_2;
  end

  assign c$vecflat_26 = {c_movementclock
                        ,c$dt_case_alt};

  // index begin
  wire [23:0] vec_26 [0:2-1];

  genvar i_28;
  generate
  for (i_28=0; i_28 < 2; i_28=i_28+1) begin : mk_array_26
    assign vec_26[(2-1)-i_28] = c$vecflat_26[i_28*24+:24];
  end
  endgenerate

  assign \c$_INTERNAL_.o_movementclock_case_alt  = vec_26[(64'sd1)];
  // index end

  assign c$vecflat_27 = {c_movementclock
                        ,c$dt_case_alt};

  // index begin
  wire [23:0] vec_27 [0:2-1];

  genvar i_29;
  generate
  for (i_29=0; i_29 < 2; i_29=i_29+1) begin : mk_array_27
    assign vec_27[(2-1)-i_29] = c$vecflat_27[i_29*24+:24];
  end
  endgenerate

  assign \c$_INTERNAL_.o_movementclock_case_alt_0  = vec_27[(64'sd0)];
  // index end

  assign c$vecflat_28 = {c_score,10'd0,dt_18};

  // index begin
  wire [9:0] vec_28 [0:3-1];

  genvar i_30;
  generate
  for (i_30=0; i_30 < 3; i_30=i_30+1) begin : mk_array_28
    assign vec_28[(3-1)-i_30] = c$vecflat_28[i_30*10+:10];
  end
  endgenerate

  assign \c$_INTERNAL_.o_score_case_alt  = vec_28[(64'sd2)];
  // index end

  assign \c$_INTERNAL_.o_score_case_alt_0_selection_res  = (bs_13[(64'sd1)]) == (1'b1);

  always @(*) begin
    if(\c$_INTERNAL_.o_score_case_alt_0_selection_res )
      \c$_INTERNAL_.o_score_case_alt_0  = \c$_INTERNAL_.o_score_case_alt_1 ;
    else
      \c$_INTERNAL_.o_score_case_alt_0  = \c$_INTERNAL_.o_score_case_alt_2 ;
  end

  assign c$vecflat_29 = {dt_14,1'b0,1'b1};

  // index begin
  wire  vec_29 [0:3-1];

  genvar i_31;
  generate
  for (i_31=0; i_31 < 3; i_31=i_31+1) begin : mk_array_29
    assign vec_29[(3-1)-i_31] = c$vecflat_29[i_31*1+:1];
  end
  endgenerate

  assign c$o_gameover_case_alt = vec_29[(64'sd2)];
  // index end

  assign c$o_gameover_case_alt_0_selection_res = (bs_14[(64'sd1)]) == (1'b1);

  always @(*) begin
    if(c$o_gameover_case_alt_0_selection_res)
      c$o_gameover_case_alt_0 = c$o_gameover_case_alt_1;
    else
      c$o_gameover_case_alt_0 = c$o_gameover_case_alt_2;
  end

  assign c$vecflat_30 = {c_counter,dt_16};

  // index begin
  wire [2:0] vec_30 [0:2-1];

  genvar i_32;
  generate
  for (i_32=0; i_32 < 2; i_32=i_32+1) begin : mk_array_30
    assign vec_30[(2-1)-i_32] = c$vecflat_30[i_32*3+:3];
  end
  endgenerate

  assign \c$_INTERNAL_.o_counter_case_alt  = vec_30[(64'sd1)];
  // index end

  assign c$vecflat_31 = {c_counter,dt_16};

  // index begin
  wire [2:0] vec_31 [0:2-1];

  genvar i_33;
  generate
  for (i_33=0; i_33 < 2; i_33=i_33+1) begin : mk_array_31
    assign vec_31[(2-1)-i_33] = c$vecflat_31[i_33*3+:3];
  end
  endgenerate

  assign \c$_INTERNAL_.o_counter_case_alt_0  = vec_31[(64'sd0)];
  // index end

  assign c$vecflat_32 = {c_shotCounter
                        ,3'd4
                        ,3'd0
                        ,dt_20};

  // index begin
  wire [2:0] vec_32 [0:4-1];

  genvar i_34;
  generate
  for (i_34=0; i_34 < 4; i_34=i_34+1) begin : mk_array_32
    assign vec_32[(4-1)-i_34] = c$vecflat_32[i_34*3+:3];
  end
  endgenerate

  assign \c$_INTERNAL_.o_shotCounter_case_alt  = vec_32[(64'sd3)];
  // index end

  assign \c$_INTERNAL_.o_shotCounter_case_alt_0_selection_res  = (bs_16[(64'sd1)]) == (1'b1);

  always @(*) begin
    if(\c$_INTERNAL_.o_shotCounter_case_alt_0_selection_res )
      \c$_INTERNAL_.o_shotCounter_case_alt_0  = \c$_INTERNAL_.o_shotCounter_case_alt_1 ;
    else
      \c$_INTERNAL_.o_shotCounter_case_alt_0  = \c$_INTERNAL_.o_shotCounter_case_alt_2 ;
  end

  assign c$vecflat_33 = {dt_11
                        ,{{1'b0,8'd0}
                         ,{1'b0,8'd0}
                         ,{1'b0,8'd0}
                         ,{1'b0,8'd0}}
                        ,dt_17
                        ,dt_19};

  // index begin
  wire [35:0] vec_33 [0:4-1];

  genvar i_35;
  generate
  for (i_35=0; i_35 < 4; i_35=i_35+1) begin : mk_array_33
    assign vec_33[(4-1)-i_35] = c$vecflat_33[i_35*36+:36];
  end
  endgenerate

  assign c$o_resets_case_alt_1 = vec_33[(64'sd2)];
  // index end

  assign c$o_resets_case_alt_2_selection_res = (bs_8[(64'sd2)]) == (1'b1);

  always @(*) begin
    if(c$o_resets_case_alt_2_selection_res)
      c$o_resets_case_alt_2 = c$o_resets_case_alt_3;
    else
      c$o_resets_case_alt_2 = c$o_resets_case_alt_4;
  end

  assign c$vecflat_34 = {dt_13
                        ,{1'b0,1'b0,1'b0,1'b0}
                        ,c$dt_case_alt_0};

  // index begin
  wire [3:0] vec_34 [0:3-1];

  genvar i_36;
  generate
  for (i_36=0; i_36 < 3; i_36=i_36+1) begin : mk_array_34
    assign vec_34[(3-1)-i_36] = c$vecflat_34[i_36*4+:4];
  end
  endgenerate

  assign c$o_moveticks_case_alt_1 = vec_34[(64'sd1)];
  // index end

  assign c$vecflat_35 = {dt_13
                        ,{1'b0,1'b0,1'b0,1'b0}
                        ,c$dt_case_alt_0};

  // index begin
  wire [3:0] vec_35 [0:3-1];

  genvar i_37;
  generate
  for (i_37=0; i_37 < 3; i_37=i_37+1) begin : mk_array_35
    assign vec_35[(3-1)-i_37] = c$vecflat_35[i_37*4+:4];
  end
  endgenerate

  assign c$o_moveticks_case_alt_2 = vec_35[(64'sd0)];
  // index end

  assign c$vecflat_36 = {c_score,10'd0,dt_18};

  // index begin
  wire [9:0] vec_36 [0:3-1];

  genvar i_38;
  generate
  for (i_38=0; i_38 < 3; i_38=i_38+1) begin : mk_array_36
    assign vec_36[(3-1)-i_38] = c$vecflat_36[i_38*10+:10];
  end
  endgenerate

  assign \c$_INTERNAL_.o_score_case_alt_1  = vec_36[(64'sd1)];
  // index end

  assign c$vecflat_37 = {c_score,10'd0,dt_18};

  // index begin
  wire [9:0] vec_37 [0:3-1];

  genvar i_39;
  generate
  for (i_39=0; i_39 < 3; i_39=i_39+1) begin : mk_array_37
    assign vec_37[(3-1)-i_39] = c$vecflat_37[i_39*10+:10];
  end
  endgenerate

  assign \c$_INTERNAL_.o_score_case_alt_2  = vec_37[(64'sd0)];
  // index end

  assign c$vecflat_38 = {dt_14,1'b0,1'b1};

  // index begin
  wire  vec_38 [0:3-1];

  genvar i_40;
  generate
  for (i_40=0; i_40 < 3; i_40=i_40+1) begin : mk_array_38
    assign vec_38[(3-1)-i_40] = c$vecflat_38[i_40*1+:1];
  end
  endgenerate

  assign c$o_gameover_case_alt_1 = vec_38[(64'sd1)];
  // index end

  assign c$vecflat_39 = {dt_14,1'b0,1'b1};

  // index begin
  wire  vec_39 [0:3-1];

  genvar i_41;
  generate
  for (i_41=0; i_41 < 3; i_41=i_41+1) begin : mk_array_39
    assign vec_39[(3-1)-i_41] = c$vecflat_39[i_41*1+:1];
  end
  endgenerate

  assign c$o_gameover_case_alt_2 = vec_39[(64'sd0)];
  // index end

  assign c$vecflat_40 = {c_shotCounter
                        ,3'd4
                        ,3'd0
                        ,dt_20};

  // index begin
  wire [2:0] vec_40 [0:4-1];

  genvar i_42;
  generate
  for (i_42=0; i_42 < 4; i_42=i_42+1) begin : mk_array_40
    assign vec_40[(4-1)-i_42] = c$vecflat_40[i_42*3+:3];
  end
  endgenerate

  assign \c$_INTERNAL_.o_shotCounter_case_alt_1  = vec_40[(64'sd2)];
  // index end

  assign \c$_INTERNAL_.o_shotCounter_case_alt_2_selection_res  = (bs_16[(64'sd2)]) == (1'b1);

  always @(*) begin
    if(\c$_INTERNAL_.o_shotCounter_case_alt_2_selection_res )
      \c$_INTERNAL_.o_shotCounter_case_alt_2  = \c$_INTERNAL_.o_shotCounter_case_alt_3 ;
    else
      \c$_INTERNAL_.o_shotCounter_case_alt_2  = \c$_INTERNAL_.o_shotCounter_case_alt_4 ;
  end

  assign bs_8 = {((result_29[(64'sd12)])),({((result_29[(64'sd13)])),({((result_29[(64'sd14)])),((result_29[(64'sd15)]))})})};

  assign c$vecflat_41 = {dt_11
                        ,{{1'b0,8'd0}
                         ,{1'b0,8'd0}
                         ,{1'b0,8'd0}
                         ,{1'b0,8'd0}}
                        ,dt_17
                        ,dt_19};

  // index begin
  wire [35:0] vec_41 [0:4-1];

  genvar i_43;
  generate
  for (i_43=0; i_43 < 4; i_43=i_43+1) begin : mk_array_41
    assign vec_41[(4-1)-i_43] = c$vecflat_41[i_43*36+:36];
  end
  endgenerate

  assign c$o_resets_case_alt_3 = vec_41[(64'sd1)];
  // index end

  assign c$vecflat_42 = {dt_11
                        ,{{1'b0,8'd0}
                         ,{1'b0,8'd0}
                         ,{1'b0,8'd0}
                         ,{1'b0,8'd0}}
                        ,dt_17
                        ,dt_19};

  // index begin
  wire [35:0] vec_42 [0:4-1];

  genvar i_44;
  generate
  for (i_44=0; i_44 < 4; i_44=i_44+1) begin : mk_array_42
    assign vec_42[(4-1)-i_44] = c$vecflat_42[i_44*36+:36];
  end
  endgenerate

  assign c$o_resets_case_alt_4 = vec_42[(64'sd0)];
  // index end

  assign bs_9 = {((result_29[(64'sd10)])),((result_29[(64'sd11)]))};

  assign bs_10 = {((result_29[(64'sd19)])),((result_29[(64'sd20)]))};

  assign bs_11 = {((result_29[(64'sd7)])),({((result_29[(64'sd8)])),((result_29[(64'sd9)]))})};

  assign bs_12 = {((result_29[(64'sd5)])),((result_29[(64'sd6)]))};

  assign bs_13 = {((result_29[(64'sd16)])),({((result_29[(64'sd17)])),((result_29[(64'sd18)]))})};

  assign bs_14 = {((result_29[(64'sd2)])),({((result_29[(64'sd3)])),((result_29[(64'sd4)]))})};

  assign bs_15 = {((result_29[(64'sd0)])),((result_29[(64'sd1)]))};

  assign bs_16 = {((result_29[(64'sd21)])),({((result_29[(64'sd22)])),({((result_29[(64'sd23)])),((result_29[(64'sd24)]))})})};

  assign c$vecflat_43 = {c_shotCounter
                        ,3'd4
                        ,3'd0
                        ,dt_20};

  // index begin
  wire [2:0] vec_43 [0:4-1];

  genvar i_45;
  generate
  for (i_45=0; i_45 < 4; i_45=i_45+1) begin : mk_array_43
    assign vec_43[(4-1)-i_45] = c$vecflat_43[i_45*3+:3];
  end
  endgenerate

  assign \c$_INTERNAL_.o_shotCounter_case_alt_3  = vec_43[(64'sd1)];
  // index end

  assign c$vecflat_44 = {c_shotCounter
                        ,3'd4
                        ,3'd0
                        ,dt_20};

  // index begin
  wire [2:0] vec_44 [0:4-1];

  genvar i_46;
  generate
  for (i_46=0; i_46 < 4; i_46=i_46+1) begin : mk_array_44
    assign vec_44[(4-1)-i_46] = c$vecflat_44[i_46*3+:3];
  end
  endgenerate

  assign \c$_INTERNAL_.o_shotCounter_case_alt_4  = vec_44[(64'sd0)];
  // index end

  // register begin
  reg [2:0] c_counter_reg = 3'd0;
  always @(posedge \$d(%,%) [1:1] or posedge \$d(%,%) [0:0]) begin : c_counter_register
    if (\$d(%,%) [0:0]) begin
      c_counter_reg <= 3'd0;
    end else begin
      c_counter_reg <= result_26;
    end
  end
  assign c_counter = c_counter_reg;
  // register end

  // register begin
  reg [2:0] c_shotCounter_reg = 3'd0;
  always @(posedge \$d(%,%) [1:1] or posedge \$d(%,%) [0:0]) begin : c_shotCounter_register
    if (\$d(%,%) [0:0]) begin
      c_shotCounter_reg <= 3'd0;
    end else begin
      c_shotCounter_reg <= result_27;
    end
  end
  assign c_shotCounter = c_shotCounter_reg;
  // register end

  // register begin
  reg [9:0] c_score_reg = 10'd0;
  always @(posedge \$d(%,%) [1:1] or posedge \$d(%,%) [0:0]) begin : c_score_register
    if (\$d(%,%) [0:0]) begin
      c_score_reg <= 10'd0;
    end else begin
      c_score_reg <= result_24;
    end
  end
  assign c_score = c_score_reg;
  // register end

  // register begin
  reg [23:0] c_movementclock_reg = {11'd0,13'd0};
  always @(posedge \$d(%,%) [1:1] or posedge \$d(%,%) [0:0]) begin : c_movementclock_register
    if (\$d(%,%) [0:0]) begin
      c_movementclock_reg <= {11'd0,13'd0};
    end else begin
      c_movementclock_reg <= result_23;
    end
  end
  assign c_movementclock = c_movementclock_reg;
  // register end

  // register begin
  reg [7:0] c_newangle_reg = 8'd42;
  always @(posedge \$d(%,%) [1:1] or posedge \$d(%,%) [0:0]) begin : c_newangle_register
    if (\$d(%,%) [0:0]) begin
      c_newangle_reg <= 8'd42;
    end else begin
      c_newangle_reg <= result_20;
    end
  end
  assign c_newangle = c_newangle_reg;
  // register end

  // register begin
  reg [35:0] dt_11_reg = {{1'b0,8'd0},{1'b0,8'd0},{1'b0,8'd0},{1'b0,8'd0}};
  always @(posedge \$d(%,%) [1:1] or posedge \$d(%,%) [0:0]) begin : dt_11_register
    if (\$d(%,%) [0:0]) begin
      dt_11_reg <= {{1'b0,8'd0},{1'b0,8'd0},{1'b0,8'd0},{1'b0,8'd0}};
    end else begin
      dt_11_reg <= result_19;
    end
  end
  assign dt_11 = dt_11_reg;
  // register end

  // register begin
  reg [2:0] dt_12_reg = 3'b000;
  always @(posedge \$d(%,%) [1:1] or posedge \$d(%,%) [0:0]) begin : dt_12_register
    if (\$d(%,%) [0:0]) begin
      dt_12_reg <= 3'b000;
    end else begin
      dt_12_reg <= result_21;
    end
  end
  assign dt_12 = dt_12_reg;
  // register end

  // register begin
  reg [3:0] dt_13_reg = {1'b0,1'b0,1'b0,1'b0};
  always @(posedge \$d(%,%) [1:1] or posedge \$d(%,%) [0:0]) begin : dt_13_register
    if (\$d(%,%) [0:0]) begin
      dt_13_reg <= {1'b0,1'b0,1'b0,1'b0};
    end else begin
      dt_13_reg <= result_22;
    end
  end
  assign dt_13 = dt_13_reg;
  // register end

  // register begin
  reg  dt_14_reg = 1'b0;
  always @(posedge \$d(%,%) [1:1] or posedge \$d(%,%) [0:0]) begin : dt_14_register
    if (\$d(%,%) [0:0]) begin
      dt_14_reg <= 1'b0;
    end else begin
      dt_14_reg <= result_25;
    end
  end
  assign dt_14 = dt_14_reg;
  // register end

  assign dt_15 = (c_newangle + 8'd128) - 8'd7;

  assign dt_16 = (c_counter + 3'd1) % 3'd4;

  always @(*) begin
    if(c$dt_case_scrut)
      result_28 = result_30;
    else
      result_28 = result_30;
  end

  always @(*) begin
    case(ds1_0)
      11'd0 : c$dt_case_alt = {11'd1,c + 13'd1};
      default : c$dt_case_alt = {c$dt_app_arg,c};
    endcase
  end

  assign result_29 = {((~ w26)),({(w30),({(w29),({1'b0,({1'b1,({1'b0,({((w20 & c$w1_app_arg)),({(c$w26_app_arg),({(c$cout_app_arg_11),({(w18),({((~ w1)),({(w19),({1'b0,({1'b1,({1'b0,({c$cout_app_arg_12,({c$cout_app_arg_13,({1'b0,({((~ w33)),({(w33),({c$cout_app_arg_13,({c$cout_app_arg_12,3'b010})})})})})})})})})})})})})})})})})})})})})};

  assign dt_17 = {{1'b1,c_newangle + 8'd0}
                 ,{1'b1,c_newangle + 8'd50}
                 ,{1'b1,c_newangle + 8'd126}
                 ,{1'b1,c_newangle + 8'd189}};

  assign c$dt_case_scrut = r1_0 < \r2' ;

  assign ds1_0 = c_movementclock[23:13];

  assign dt_18 = c_score + 10'd1;

  assign r1_0 = c$dt_case_scrut_0[10:3];

  assign \r2'  = r2_0 >> (64'sd1);

  assign \r4'  = r4_0 >> (64'sd2);

  assign result_30_selection_res = \r3'  < \r4' ;

  always @(*) begin
    if(result_30_selection_res)
      result_30 = c$case_alt;
    else
      result_30 = c$case_alt_0;
  end

  assign \r3'  = r3 >> (64'sd1);

  assign c$case_alt_selection_res = c$tupIn[7:0] < \r3' ;

  always @(*) begin
    if(c$case_alt_selection_res)
      c$case_alt = c$tupIn[10:8];
    else
      c$case_alt = c3;
  end

  assign c$case_alt_0_selection_res = c$tupIn[7:0] < \r4' ;

  always @(*) begin
    if(c$case_alt_0_selection_res)
      c$case_alt_0 = c$tupIn[10:8];
    else
      c$case_alt_0 = c4;
  end

  always @(*) begin
    case(ds1_0)
      11'd0 : c$dt_case_alt_0 = {c == 13'd0
                                ,c$dt_app_arg_0
                                ,c$dt_app_arg_1
                                ,c$dt_app_arg_2};
      default : c$dt_case_alt_0 = {1'b0
                                  ,1'b0
                                  ,1'b0
                                  ,1'b0};
    endcase
  end

  assign c = c_movementclock[12:0];

  assign c$dt_app_arg_selection_res = ds1_0 > 11'd1024;

  always @(*) begin
    if(c$dt_app_arg_selection_res)
      c$dt_app_arg = 11'd0;
    else
      c$dt_app_arg = (ds1_0 + 11'd1) + (({{(11-10) {1'b0}},c_score}) >> (64'sd3));
  end

  always @(*) begin
    case(c_counter)
      3'd0 : dt_19 = {{1'b1,c_newangle}
                     ,{1'b0,8'd0}
                     ,{1'b0,8'd0}
                     ,{1'b0,8'd0}};
      3'd1 : dt_19 = {{1'b0,8'd0}
                     ,{1'b1,c_newangle + 8'd50}
                     ,{1'b0,8'd0}
                     ,{1'b0,8'd0}};
      3'd2 : dt_19 = {{1'b0,8'd0}
                     ,{1'b0,8'd0}
                     ,{1'b1,c_newangle + 8'd126}
                     ,{1'b0,8'd0}};
      3'd3 : dt_19 = {{1'b0,8'd0}
                     ,{1'b0,8'd0}
                     ,{1'b0,8'd0}
                     ,{1'b1,c_newangle + 8'd189}};
      default : dt_19 = {{1'b0,8'd0}
                        ,{1'b0,8'd0}
                        ,{1'b0,8'd0}
                        ,{1'b0,8'd0}};
    endcase
  end

  assign c$dt_case_scrut_0 = enemies7[76-1 -: 19];

  assign r2_0 = c$dt_case_scrut_1[10:3];

  assign r3 = c$dt_case_scrut_2[10:3];

  assign c3 = c$dt_case_scrut_2[2:0];

  assign r4_0 = c$dt_case_scrut_3[10:3];

  assign c4 = c$dt_case_scrut_3[2:0];

  assign dt_20 = c_shotCounter - 3'd1;

  assign w26 = (~ ((~ ((~ w15) & c$w26_app_arg_0)) & w16)) & (~ ((~ w22) & c$w26_app_arg));

  assign w30 = (~ w29) & w26;

  assign c$dt_case_scrut_1 = scrut_0[57-1 -: 19];

  assign c$dt_case_scrut_2 = scrut1_1[38-1 -: 19];

  assign c$dt_case_scrut_3 = scrut2_1[19-1 -: 19];

  always @(*) begin
    if(c$dt_case_scrut)
      c$tupIn = {c1,r1_0};
    else
      c$tupIn = {c2,\r2' };
  end

  assign w29 = ((~ (w13 & c$w29_app_arg)) & w22) & w11;

  assign scrut_0 = enemies7[57-1 : 0];

  assign scrut1_1 = scrut_0[38-1 : 0];

  assign scrut2_1 = scrut1_1[19-1 : 0];

  always @(*) begin
    case(c)
      13'd0 : c$dt_app_arg_0 = 1'b1;
      default : c$dt_app_arg_0 = c == 13'd4096;
    endcase
  end

  assign w11 = c$w11_app_arg & (~ w9);

  assign c1 = c$dt_case_scrut_0[2:0];

  assign c2 = c$dt_case_scrut_1[2:0];

  always @(*) begin
    case(c)
      13'd0 : c$dt_app_arg_1 = 1'b1;
      default : c$dt_app_arg_1 = c == 13'd4096;
    endcase
  end

  assign w22 = (cin_2[(64'sd3)]) & (~ c$w16_app_arg);

  assign w16 = \_INTERNAL_.w6  & c$w16_app_arg;

  assign c$w26_app_arg = cin_2[(64'sd2)];

  assign c$w11_app_arg = ~ w10;

  always @(*) begin
    case(c)
      13'd0 : c$dt_app_arg_2 = 1'b1;
      default : c$dt_app_arg_2 = c$dt_case_alt_1;
    endcase
  end

  assign cin_2 = {result_31,({c$cin_app_arg_5,({c$cin_app_arg_6,({result_34,result_33})})})};

  assign w10 = c$w1_app_arg & c$w29_app_arg;

  assign w9 = w8 & \c$_INTERNAL_.w7_app_arg ;

  // register begin
  reg  _INTERNAL_w6_reg = (1'b0);
  always @(posedge \$d(%,%) [1:1] or posedge \$d(%,%) [0:0]) begin : _INTERNAL_w6_register
    if (\$d(%,%) [0:0]) begin
      _INTERNAL_w6_reg <= (1'b0);
    end else begin
      _INTERNAL_w6_reg <= (\c$_INTERNAL_.w6_app_arg  & c$w11_app_arg);
    end
  end
  assign \_INTERNAL_.w6  = _INTERNAL_w6_reg;
  // register end

  assign c$w16_app_arg = cin_2[(64'sd0)];

  assign c$dt_case_alt_1_selection_res = c == 13'd2048;

  always @(*) begin
    if(c$dt_case_alt_1_selection_res)
      c$dt_case_alt_1 = 1'b1;
    else
      c$dt_case_alt_1 = c$dt_case_alt_2;
  end

  assign w8 = \_INTERNAL_.w7  & c$w1_app_arg;

  assign w13 = (~ \_INTERNAL_.w7 ) & c$w13_app_arg;

  assign c$w29_app_arg = cin_2[(64'sd1)];

  assign c$w26_app_arg_0 = ~ w11;

  always @(*) begin
    if(result_32)
      result_31 = 1'b1;
    else
      result_31 = 1'b0;
  end

  assign c$dt_case_alt_2_selection_res = c == 13'd4096;

  always @(*) begin
    if(c$dt_case_alt_2_selection_res)
      c$dt_case_alt_2 = 1'b1;
    else
      c$dt_case_alt_2 = c == 13'd6144;
  end

  assign w15 = (cin_2[(64'sd4)]) & \c$_INTERNAL_.w7_app_arg ;

  // register begin
  reg  _INTERNAL_w7_reg = (1'b0);
  always @(posedge \$d(%,%) [1:1] or posedge \$d(%,%) [0:0]) begin : _INTERNAL_w7_register
    if (\$d(%,%) [0:0]) begin
      _INTERNAL_w7_reg <= (1'b0);
    end else begin
      _INTERNAL_w7_reg <= (~ ((~ w8) & \c$_INTERNAL_.w7_app_arg ));
    end
  end
  assign \_INTERNAL_.w7  = _INTERNAL_w7_reg;
  // register end

  assign w20 = (~ w19) & \c$_INTERNAL_.w6_app_arg ;

  assign c$w13_app_arg = ~ \_INTERNAL_.w6 ;

  assign \c$_INTERNAL_.w6_app_arg  = ~ w12;

  always @(*) begin
    if(shot)
      c$cin_app_arg_5 = 1'b1;
    else
      c$cin_app_arg_5 = 1'b0;
  end

  assign w12 = c$w26_app_arg_0 & c$w13_app_arg;

  assign c$cout_app_arg_11 = ~ w20;

  always @(*) begin
    if(c$tup_case_alt)
      c$cin_app_arg_6 = 1'b1;
    else
      c$cin_app_arg_6 = 1'b0;
  end

  assign result_32_selection = c$angle_case_scrut[10:3];

  always @(*) begin
    case(result_32_selection)
      8'd0 : result_32 = result_35;
      default : result_32 = result_35;
    endcase
  end

  assign w18 = (w15 & c$w1_app_arg) & w16;

  assign w19 = (~ w18) & w1;

  always @(*) begin
    if(b_0)
      result_33 = 1'b1;
    else
      result_33 = 1'b0;
  end

  always @(*) begin
    if(b_1)
      result_34 = 1'b1;
    else
      result_34 = 1'b0;
  end

  assign result_35_selection_res = c$app_arg_5 < c$triggerresetall1_$jOut_app_arg;

  always @(*) begin
    if(result_35_selection_res)
      result_35 = 1'b1;
    else
      result_35 = c$app_arg_5 > (8'd255 - c$triggerresetall1_$jOut_app_arg);
  end

  assign c$app_arg_5 = c$angle_case_scrut[18:11] - rotation;

  assign w1 = (~ w13) & c$w1_app_arg;

  assign \c$_INTERNAL_.w7_app_arg  = ~ c$w29_app_arg;

  assign b_0 = c_shotCounter > 3'd0;

  assign b_1 = c$angle_case_scrut[10:3] <= 8'd8;

  assign c$triggerresetall1_$jOut_app_arg_selection = c$angle_case_scrut[10:3];

  always @(*) begin
    case(c$triggerresetall1_$jOut_app_arg_selection)
      8'd0 : c$triggerresetall1_$jOut_app_arg = 8'd255;
      default : c$triggerresetall1_$jOut_app_arg = 8'd255 / c$angle_case_scrut[10:3];
    endcase
  end

  assign c$w1_app_arg = ~ c$w26_app_arg;

  // index begin
  wire [18:0] vec_45 [0:4-1];

  genvar i_47;
  generate
  for (i_47=0; i_47 < 4; i_47=i_47+1) begin : mk_array_45
    assign vec_45[(4-1)-i_47] = enemies7[i_47*19+:19];
  end
  endgenerate

  assign c$angle_case_scrut = vec_45[(wild)];
  // index end

  assign c$cout_app_arg_12 = w32;

  assign c$i_182 = (c_counter % 3'd4);

  assign wild = $signed(($signed({{(64-3) {1'b0}},c$i_182})));

  assign w32 = (~ (w30 & c$w29_app_arg)) & (~ w21);

  assign w21 = c$cout_app_arg_11 & w9;

  assign w33 = w21 & w16;

  assign c$cout_app_arg_13 = (~ w32);

  assign enemies6 = {result_12,enemies5};

  assign result_36 = {c$app_arg_7
                     ,c$app_arg_6
                     ,result_37[10:8]};

  // register begin
  reg [7:0] c$app_arg_6_reg = 8'd255;
  always @(posedge \$d(%,%) [1:1] or posedge \$d(%,%) [0:0]) begin : c$app_arg_6_register
    if (\$d(%,%) [0:0]) begin
      c$app_arg_6_reg <= 8'd255;
    end else begin
      c$app_arg_6_reg <= result_37[7:0];
    end
  end
  assign c$app_arg_6 = c$app_arg_6_reg;
  // register end

  // register begin
  reg [7:0] c$app_arg_7_reg = 8'd16;
  always @(posedge \$d(%,%) [1:1] or posedge \$d(%,%) [0:0]) begin : c$app_arg_7_register
    if (\$d(%,%) [0:0]) begin
      c$app_arg_7_reg <= 8'd16;
    end else begin
      c$app_arg_7_reg <= result_37[18:11];
    end
  end
  assign c$app_arg_7 = c$app_arg_7_reg;
  // register end

  assign result_37 = {result_38
                     ,result_39
                     ,result_40};

  assign result_38_selection_res = (bs_17[(64'sd0)]) == (1'b1);

  always @(*) begin
    if(result_38_selection_res)
      result_38 = c$o_angle_case_alt_5;
    else
      result_38 = c$o_angle_case_alt_6;
  end

  assign result_39_selection_res = (bs_18[(64'sd0)]) == (1'b1);

  always @(*) begin
    if(result_39_selection_res)
      result_39 = c$o_color_case_alt_5;
    else
      result_39 = c$o_color_case_alt_6;
  end

  assign result_40_selection_res = (bs_19[(64'sd0)]) == (1'b1);

  always @(*) begin
    if(result_40_selection_res)
      result_40 = \c$_INTERNAL_.o_radius_case_alt_11 ;
    else
      result_40 = \c$_INTERNAL_.o_radius_case_alt_12 ;
  end

  assign c$vecflat_45 = {dt_21,dt_22};

  // index begin
  wire [7:0] vec_46 [0:2-1];

  genvar i_48;
  generate
  for (i_48=0; i_48 < 2; i_48=i_48+1) begin : mk_array_46
    assign vec_46[(2-1)-i_48] = c$vecflat_45[i_48*8+:8];
  end
  endgenerate

  assign c$o_angle_case_alt_5 = vec_46[(64'sd1)];
  // index end

  assign c$vecflat_46 = {dt_21,dt_22};

  // index begin
  wire [7:0] vec_47 [0:2-1];

  genvar i_49;
  generate
  for (i_49=0; i_49 < 2; i_49=i_49+1) begin : mk_array_47
    assign vec_47[(2-1)-i_49] = c$vecflat_46[i_49*8+:8];
  end
  endgenerate

  assign c$o_angle_case_alt_6 = vec_47[(64'sd0)];
  // index end

  assign c$vecflat_47 = {dt_23,3'b101};

  // index begin
  wire [2:0] vec_48 [0:2-1];

  genvar i_50;
  generate
  for (i_50=0; i_50 < 2; i_50=i_50+1) begin : mk_array_48
    assign vec_48[(2-1)-i_50] = c$vecflat_47[i_50*3+:3];
  end
  endgenerate

  assign c$o_color_case_alt_5 = vec_48[(64'sd1)];
  // index end

  assign c$vecflat_48 = {dt_23,3'b101};

  // index begin
  wire [2:0] vec_49 [0:2-1];

  genvar i_51;
  generate
  for (i_51=0; i_51 < 2; i_51=i_51+1) begin : mk_array_49
    assign vec_49[(2-1)-i_51] = c$vecflat_48[i_51*3+:3];
  end
  endgenerate

  assign c$o_color_case_alt_6 = vec_49[(64'sd0)];
  // index end

  assign c$vecflat_49 = {c_radius_2,8'd255,dt_24};

  // index begin
  wire [7:0] vec_50 [0:3-1];

  genvar i_52;
  generate
  for (i_52=0; i_52 < 3; i_52=i_52+1) begin : mk_array_50
    assign vec_50[(3-1)-i_52] = c$vecflat_49[i_52*8+:8];
  end
  endgenerate

  assign \c$_INTERNAL_.o_radius_case_alt_11  = vec_50[(64'sd2)];
  // index end

  assign \c$_INTERNAL_.o_radius_case_alt_12_selection_res  = (bs_19[(64'sd1)]) == (1'b1);

  always @(*) begin
    if(\c$_INTERNAL_.o_radius_case_alt_12_selection_res )
      \c$_INTERNAL_.o_radius_case_alt_12  = \c$_INTERNAL_.o_radius_case_alt_13 ;
    else
      \c$_INTERNAL_.o_radius_case_alt_12  = \c$_INTERNAL_.o_radius_case_alt_14 ;
  end

  assign c$vecflat_50 = {c_radius_2,8'd255,dt_24};

  // index begin
  wire [7:0] vec_51 [0:3-1];

  genvar i_53;
  generate
  for (i_53=0; i_53 < 3; i_53=i_53+1) begin : mk_array_51
    assign vec_51[(3-1)-i_53] = c$vecflat_50[i_53*8+:8];
  end
  endgenerate

  assign \c$_INTERNAL_.o_radius_case_alt_13  = vec_51[(64'sd1)];
  // index end

  assign c$vecflat_51 = {c_radius_2,8'd255,dt_24};

  // index begin
  wire [7:0] vec_52 [0:3-1];

  genvar i_54;
  generate
  for (i_54=0; i_54 < 3; i_54=i_54+1) begin : mk_array_52
    assign vec_52[(3-1)-i_54] = c$vecflat_51[i_54*8+:8];
  end
  endgenerate

  assign \c$_INTERNAL_.o_radius_case_alt_14  = vec_52[(64'sd0)];
  // index end

  assign bs_17 = {((result_41[(64'sd0)])),((result_41[(64'sd1)]))};

  assign bs_18 = {((result_41[(64'sd2)])),((result_41[(64'sd3)]))};

  assign bs_19 = {((result_41[(64'sd4)])),({((result_41[(64'sd5)])),((result_41[(64'sd6)]))})};

  // register begin
  reg [7:0] c_radius_2_reg = 8'd255;
  always @(posedge \$d(%,%) [1:1] or posedge \$d(%,%) [0:0]) begin : c_radius_2_register
    if (\$d(%,%) [0:0]) begin
      c_radius_2_reg <= 8'd255;
    end else begin
      c_radius_2_reg <= result_40;
    end
  end
  assign c_radius_2 = c_radius_2_reg;
  // register end

  // register begin
  reg [7:0] dt_21_reg = 8'd0;
  always @(posedge \$d(%,%) [1:1] or posedge \$d(%,%) [0:0]) begin : dt_21_register
    if (\$d(%,%) [0:0]) begin
      dt_21_reg <= 8'd0;
    end else begin
      dt_21_reg <= result_38;
    end
  end
  assign dt_21 = dt_21_reg;
  // register end

  assign dt_22 = a1;

  // register begin
  reg [2:0] dt_23_reg = 3'b000;
  always @(posedge \$d(%,%) [1:1] or posedge \$d(%,%) [0:0]) begin : dt_23_register
    if (\$d(%,%) [0:0]) begin
      dt_23_reg <= 3'b000;
    end else begin
      dt_23_reg <= result_39;
    end
  end
  assign dt_23 = dt_23_reg;
  // register end

  assign result_41 = {((c$cout_app_arg_17 & c$cout_app_arg_15)),({c$cout_app_arg_16,({((c$cout_app_arg_17 & (~ c$cout_app_arg_15))),({1'b1,({1'b0,({c$cout_app_arg_16,(c$cout_app_arg_17)})})})})})};

  assign dt_24 = c_radius_2 - 8'd1;

  assign c$cout_app_arg_14 = cin_3[(64'sd1)];

  assign c$cout_app_arg_15 = cin_3[(64'sd0)];

  assign cin_3 = {c$cin_app_arg_8,c$cin_app_arg_7};

  always @(*) begin
    if(clock_2)
      c$cin_app_arg_7 = 1'b1;
    else
      c$cin_app_arg_7 = 1'b0;
  end

  always @(*) begin
    if(r1)
      c$cin_app_arg_8 = 1'b1;
    else
      c$cin_app_arg_8 = 1'b0;
  end

  assign c$cout_app_arg_16 = c$cout_app_arg_14;

  assign c$cout_app_arg_17 = ~ c$cout_app_arg_14;

  assign clock_2 = x[4-1 -: 1];

  assign enemies7 = {result_36,enemies6};

  assign result_42 = {result_18[15:6]
                     ,result_18[88:88]
                     ,enemies7
                     ,result_18[5:3]};

  assign result_43 = {result_44[36:32]
                     ,result_44[31:27]
                     ,result_44[26:24]};

  assign result_44 = {result_45
                     ,result_46
                     ,result_47
                     ,result_52
                     ,result_48
                     ,result_49
                     ,result_50
                     ,result_51};

  assign result_45_selection_res = (bs_20[(64'sd0)]) == (1'b1);

  always @(*) begin
    if(result_45_selection_res)
      result_45 = c$o_bxcoord_case_alt;
    else
      result_45 = c$o_bxcoord_case_alt_0;
  end

  assign result_46_selection_res = (bs_21[(64'sd0)]) == (1'b1);

  always @(*) begin
    if(result_46_selection_res)
      result_46 = c$o_bycoord_case_alt;
    else
      result_46 = c$o_bycoord_case_alt_0;
  end

  assign result_47_selection_res = (bs_22[(64'sd0)]) == (1'b1);

  always @(*) begin
    if(result_47_selection_res)
      result_47 = c$o_color_case_alt_7;
    else
      result_47 = c$o_color_case_alt_8;
  end

  assign result_48_selection_res = (bs_23[(64'sd0)]) == (1'b1);

  always @(*) begin
    if(result_48_selection_res)
      result_48 = \c$_INTERNAL_.o_tmpcolor_case_alt ;
    else
      result_48 = \c$_INTERNAL_.o_tmpcolor_case_alt_0 ;
  end

  assign result_49_selection_res = (bs_24[(64'sd0)]) == (1'b1);

  always @(*) begin
    if(result_49_selection_res)
      result_49 = \c$_INTERNAL_.o_tmpdist_case_alt ;
    else
      result_49 = \c$_INTERNAL_.o_tmpdist_case_alt_0 ;
  end

  assign result_50_selection_res = (bs_25[(64'sd0)]) == (1'b1);

  always @(*) begin
    if(result_50_selection_res)
      result_50 = \c$_INTERNAL_.o_xcoord_case_alt ;
    else
      result_50 = \c$_INTERNAL_.o_xcoord_case_alt_0 ;
  end

  assign result_51_selection_res = (bs_26[(64'sd0)]) == (1'b1);

  always @(*) begin
    if(result_51_selection_res)
      result_51 = \c$_INTERNAL_.o_ycoord_case_alt ;
    else
      result_51 = \c$_INTERNAL_.o_ycoord_case_alt_0 ;
  end

  assign result_52_selection_res = (bs_27[(64'sd0)]) == (1'b1);

  always @(*) begin
    if(result_52_selection_res)
      result_52 = \c$_INTERNAL_.o_counter_case_alt_1 ;
    else
      result_52 = \c$_INTERNAL_.o_counter_case_alt_2 ;
  end

  assign c$vecflat_52 = {dt_25,dt_26};

  // index begin
  wire [4:0] vec_53 [0:2-1];

  genvar i_55;
  generate
  for (i_55=0; i_55 < 2; i_55=i_55+1) begin : mk_array_53
    assign vec_53[(2-1)-i_55] = c$vecflat_52[i_55*5+:5];
  end
  endgenerate

  assign c$o_bxcoord_case_alt = vec_53[(64'sd1)];
  // index end

  assign c$vecflat_53 = {dt_25,dt_26};

  // index begin
  wire [4:0] vec_54 [0:2-1];

  genvar i_56;
  generate
  for (i_56=0; i_56 < 2; i_56=i_56+1) begin : mk_array_54
    assign vec_54[(2-1)-i_56] = c$vecflat_53[i_56*5+:5];
  end
  endgenerate

  assign c$o_bxcoord_case_alt_0 = vec_54[(64'sd0)];
  // index end

  assign c$vecflat_54 = {dt_27,dt_28};

  // index begin
  wire [4:0] vec_55 [0:2-1];

  genvar i_57;
  generate
  for (i_57=0; i_57 < 2; i_57=i_57+1) begin : mk_array_55
    assign vec_55[(2-1)-i_57] = c$vecflat_54[i_57*5+:5];
  end
  endgenerate

  assign c$o_bycoord_case_alt = vec_55[(64'sd1)];
  // index end

  assign c$vecflat_55 = {dt_27,dt_28};

  // index begin
  wire [4:0] vec_56 [0:2-1];

  genvar i_58;
  generate
  for (i_58=0; i_58 < 2; i_58=i_58+1) begin : mk_array_56
    assign vec_56[(2-1)-i_58] = c$vecflat_55[i_58*5+:5];
  end
  endgenerate

  assign c$o_bycoord_case_alt_0 = vec_56[(64'sd0)];
  // index end

  assign c$vecflat_56 = {dt_29,dt_30};

  // index begin
  wire [2:0] vec_57 [0:3-1];

  genvar i_59;
  generate
  for (i_59=0; i_59 < 3; i_59=i_59+1) begin : mk_array_57
    assign vec_57[(3-1)-i_59] = c$vecflat_56[i_59*3+:3];
  end
  endgenerate

  assign c$o_color_case_alt_7 = vec_57[(64'sd2)];
  // index end

  assign c$o_color_case_alt_8_selection_res = (bs_22[(64'sd1)]) == (1'b1);

  always @(*) begin
    if(c$o_color_case_alt_8_selection_res)
      c$o_color_case_alt_8 = c$o_color_case_alt_9;
    else
      c$o_color_case_alt_8 = c$o_color_case_alt_10;
  end

  assign c$vecflat_57 = {c_tmpcolor
                        ,3'b000
                        ,c$eta14_case_scrut[2:0]};

  // index begin
  wire [2:0] vec_58 [0:3-1];

  genvar i_60;
  generate
  for (i_60=0; i_60 < 3; i_60=i_60+1) begin : mk_array_58
    assign vec_58[(3-1)-i_60] = c$vecflat_57[i_60*3+:3];
  end
  endgenerate

  assign \c$_INTERNAL_.o_tmpcolor_case_alt  = vec_58[(64'sd2)];
  // index end

  assign \c$_INTERNAL_.o_tmpcolor_case_alt_0_selection_res  = (bs_23[(64'sd1)]) == (1'b1);

  always @(*) begin
    if(\c$_INTERNAL_.o_tmpcolor_case_alt_0_selection_res )
      \c$_INTERNAL_.o_tmpcolor_case_alt_0  = \c$_INTERNAL_.o_tmpcolor_case_alt_1 ;
    else
      \c$_INTERNAL_.o_tmpcolor_case_alt_0  = \c$_INTERNAL_.o_tmpcolor_case_alt_2 ;
  end

  assign c$vecflat_58 = {c_tmpdist
                        ,{8'd255,dt_31}};

  // index begin
  wire [7:0] vec_59 [0:3-1];

  genvar i_61;
  generate
  for (i_61=0; i_61 < 3; i_61=i_61+1) begin : mk_array_59
    assign vec_59[(3-1)-i_61] = c$vecflat_58[i_61*8+:8];
  end
  endgenerate

  assign \c$_INTERNAL_.o_tmpdist_case_alt  = vec_59[(64'sd2)];
  // index end

  assign \c$_INTERNAL_.o_tmpdist_case_alt_0_selection_res  = (bs_24[(64'sd1)]) == (1'b1);

  always @(*) begin
    if(\c$_INTERNAL_.o_tmpdist_case_alt_0_selection_res )
      \c$_INTERNAL_.o_tmpdist_case_alt_0  = \c$_INTERNAL_.o_tmpdist_case_alt_1 ;
    else
      \c$_INTERNAL_.o_tmpdist_case_alt_0  = \c$_INTERNAL_.o_tmpdist_case_alt_2 ;
  end

  assign c$vecflat_59 = {c_xcoord,dt_32};

  // index begin
  wire [4:0] vec_60 [0:2-1];

  genvar i_62;
  generate
  for (i_62=0; i_62 < 2; i_62=i_62+1) begin : mk_array_60
    assign vec_60[(2-1)-i_62] = c$vecflat_59[i_62*5+:5];
  end
  endgenerate

  assign \c$_INTERNAL_.o_xcoord_case_alt  = vec_60[(64'sd1)];
  // index end

  assign c$vecflat_60 = {c_xcoord,dt_32};

  // index begin
  wire [4:0] vec_61 [0:2-1];

  genvar i_63;
  generate
  for (i_63=0; i_63 < 2; i_63=i_63+1) begin : mk_array_61
    assign vec_61[(2-1)-i_63] = c$vecflat_60[i_63*5+:5];
  end
  endgenerate

  assign \c$_INTERNAL_.o_xcoord_case_alt_0  = vec_61[(64'sd0)];
  // index end

  assign c$vecflat_61 = {c_ycoord,dt_33};

  // index begin
  wire [4:0] vec_62 [0:2-1];

  genvar i_64;
  generate
  for (i_64=0; i_64 < 2; i_64=i_64+1) begin : mk_array_62
    assign vec_62[(2-1)-i_64] = c$vecflat_61[i_64*5+:5];
  end
  endgenerate

  assign \c$_INTERNAL_.o_ycoord_case_alt  = vec_62[(64'sd1)];
  // index end

  assign c$vecflat_62 = {c_ycoord,dt_33};

  // index begin
  wire [4:0] vec_63 [0:2-1];

  genvar i_65;
  generate
  for (i_65=0; i_65 < 2; i_65=i_65+1) begin : mk_array_63
    assign vec_63[(2-1)-i_65] = c$vecflat_62[i_65*5+:5];
  end
  endgenerate

  assign \c$_INTERNAL_.o_ycoord_case_alt_0  = vec_63[(64'sd0)];
  // index end

  assign c$vecflat_63 = {c_counter_0,dt_34};

  // index begin
  wire [2:0] vec_64 [0:2-1];

  genvar i_66;
  generate
  for (i_66=0; i_66 < 2; i_66=i_66+1) begin : mk_array_64
    assign vec_64[(2-1)-i_66] = c$vecflat_63[i_66*3+:3];
  end
  endgenerate

  assign \c$_INTERNAL_.o_counter_case_alt_1  = vec_64[(64'sd1)];
  // index end

  assign c$vecflat_64 = {c_counter_0,dt_34};

  // index begin
  wire [2:0] vec_65 [0:2-1];

  genvar i_67;
  generate
  for (i_67=0; i_67 < 2; i_67=i_67+1) begin : mk_array_65
    assign vec_65[(2-1)-i_67] = c$vecflat_64[i_67*3+:3];
  end
  endgenerate

  assign \c$_INTERNAL_.o_counter_case_alt_2  = vec_65[(64'sd0)];
  // index end

  assign c$vecflat_65 = {dt_29,dt_30};

  // index begin
  wire [2:0] vec_66 [0:3-1];

  genvar i_68;
  generate
  for (i_68=0; i_68 < 3; i_68=i_68+1) begin : mk_array_66
    assign vec_66[(3-1)-i_68] = c$vecflat_65[i_68*3+:3];
  end
  endgenerate

  assign c$o_color_case_alt_9 = vec_66[(64'sd1)];
  // index end

  assign c$vecflat_66 = {dt_29,dt_30};

  // index begin
  wire [2:0] vec_67 [0:3-1];

  genvar i_69;
  generate
  for (i_69=0; i_69 < 3; i_69=i_69+1) begin : mk_array_67
    assign vec_67[(3-1)-i_69] = c$vecflat_66[i_69*3+:3];
  end
  endgenerate

  assign c$o_color_case_alt_10 = vec_67[(64'sd0)];
  // index end

  assign c$vecflat_67 = {c_tmpcolor
                        ,3'b000
                        ,c$eta14_case_scrut[2:0]};

  // index begin
  wire [2:0] vec_68 [0:3-1];

  genvar i_70;
  generate
  for (i_70=0; i_70 < 3; i_70=i_70+1) begin : mk_array_68
    assign vec_68[(3-1)-i_70] = c$vecflat_67[i_70*3+:3];
  end
  endgenerate

  assign \c$_INTERNAL_.o_tmpcolor_case_alt_1  = vec_68[(64'sd1)];
  // index end

  assign c$vecflat_68 = {c_tmpcolor
                        ,3'b000
                        ,c$eta14_case_scrut[2:0]};

  // index begin
  wire [2:0] vec_69 [0:3-1];

  genvar i_71;
  generate
  for (i_71=0; i_71 < 3; i_71=i_71+1) begin : mk_array_69
    assign vec_69[(3-1)-i_71] = c$vecflat_68[i_71*3+:3];
  end
  endgenerate

  assign \c$_INTERNAL_.o_tmpcolor_case_alt_2  = vec_69[(64'sd0)];
  // index end

  assign c$vecflat_69 = {c_tmpdist
                        ,{8'd255,dt_31}};

  // index begin
  wire [7:0] vec_70 [0:3-1];

  genvar i_72;
  generate
  for (i_72=0; i_72 < 3; i_72=i_72+1) begin : mk_array_70
    assign vec_70[(3-1)-i_72] = c$vecflat_69[i_72*8+:8];
  end
  endgenerate

  assign \c$_INTERNAL_.o_tmpdist_case_alt_1  = vec_70[(64'sd1)];
  // index end

  assign c$vecflat_70 = {c_tmpdist
                        ,{8'd255,dt_31}};

  // index begin
  wire [7:0] vec_71 [0:3-1];

  genvar i_73;
  generate
  for (i_73=0; i_73 < 3; i_73=i_73+1) begin : mk_array_71
    assign vec_71[(3-1)-i_73] = c$vecflat_70[i_73*8+:8];
  end
  endgenerate

  assign \c$_INTERNAL_.o_tmpdist_case_alt_2  = vec_71[(64'sd0)];
  // index end

  assign bs_20 = {((result_53[(64'sd0)])),((result_53[(64'sd1)]))};

  assign bs_21 = {((result_53[(64'sd2)])),((result_53[(64'sd3)]))};

  assign bs_22 = {((result_53[(64'sd4)])),({((result_53[(64'sd5)])),((result_53[(64'sd6)]))})};

  assign bs_23 = {((result_53[(64'sd9)])),({((result_53[(64'sd10)])),((result_53[(64'sd11)]))})};

  assign bs_24 = {((result_53[(64'sd12)])),({((result_53[(64'sd13)])),((result_53[(64'sd14)]))})};

  assign bs_25 = {((result_53[(64'sd15)])),((result_53[(64'sd16)]))};

  assign bs_26 = {((result_53[(64'sd17)])),((result_53[(64'sd18)]))};

  assign bs_27 = {((result_53[(64'sd7)])),((result_53[(64'sd8)]))};

  // register begin
  reg [7:0] c_tmpdist_reg = 8'd255;
  always @(posedge \$d(%,%) [1:1] or posedge \$d(%,%) [0:0]) begin : c_tmpdist_register
    if (\$d(%,%) [0:0]) begin
      c_tmpdist_reg <= 8'd255;
    end else begin
      c_tmpdist_reg <= result_49;
    end
  end
  assign c_tmpdist = c_tmpdist_reg;
  // register end

  // register begin
  reg [4:0] c_xcoord_reg = 5'd0;
  always @(posedge \$d(%,%) [1:1] or posedge \$d(%,%) [0:0]) begin : c_xcoord_register
    if (\$d(%,%) [0:0]) begin
      c_xcoord_reg <= 5'd0;
    end else begin
      c_xcoord_reg <= result_50;
    end
  end
  assign c_xcoord = c_xcoord_reg;
  // register end

  // register begin
  reg [4:0] c_ycoord_reg = 5'd0;
  always @(posedge \$d(%,%) [1:1] or posedge \$d(%,%) [0:0]) begin : c_ycoord_register
    if (\$d(%,%) [0:0]) begin
      c_ycoord_reg <= 5'd0;
    end else begin
      c_ycoord_reg <= result_51;
    end
  end
  assign c_ycoord = c_ycoord_reg;
  // register end

  // register begin
  reg [2:0] c_counter_0_reg = 3'd0;
  always @(posedge \$d(%,%) [1:1] or posedge \$d(%,%) [0:0]) begin : c_counter_0_register
    if (\$d(%,%) [0:0]) begin
      c_counter_0_reg <= 3'd0;
    end else begin
      c_counter_0_reg <= result_52;
    end
  end
  assign c_counter_0 = c_counter_0_reg;
  // register end

  // register begin
  reg [2:0] c_tmpcolor_reg = 3'b000;
  always @(posedge \$d(%,%) [1:1] or posedge \$d(%,%) [0:0]) begin : c_tmpcolor_register
    if (\$d(%,%) [0:0]) begin
      c_tmpcolor_reg <= 3'b000;
    end else begin
      c_tmpcolor_reg <= result_48;
    end
  end
  assign c_tmpcolor = c_tmpcolor_reg;
  // register end

  // register begin
  reg [4:0] dt_25_reg = 5'd0;
  always @(posedge \$d(%,%) [1:1] or posedge \$d(%,%) [0:0]) begin : dt_25_register
    if (\$d(%,%) [0:0]) begin
      dt_25_reg <= 5'd0;
    end else begin
      dt_25_reg <= result_45;
    end
  end
  assign dt_25 = dt_25_reg;
  // register end

  assign dt_26 = c_xcoord;

  // register begin
  reg [4:0] dt_27_reg = 5'd0;
  always @(posedge \$d(%,%) [1:1] or posedge \$d(%,%) [0:0]) begin : dt_27_register
    if (\$d(%,%) [0:0]) begin
      dt_27_reg <= 5'd0;
    end else begin
      dt_27_reg <= result_46;
    end
  end
  assign dt_27 = dt_27_reg;
  // register end

  assign dt_28 = c_ycoord;

  // register begin
  reg [2:0] dt_29_reg = 3'b000;
  always @(posedge \$d(%,%) [1:1] or posedge \$d(%,%) [0:0]) begin : dt_29_register
    if (\$d(%,%) [0:0]) begin
      dt_29_reg <= 3'b000;
    end else begin
      dt_29_reg <= result_47;
    end
  end
  assign dt_29 = dt_29_reg;
  // register end

  assign dt_30 = {c_tmpcolor,3'b111};

  assign dt_31 = c$eta14_case_scrut[10:3];

  assign dt_32 = c_xcoord + 5'd1;

  assign dt_33 = c_ycoord + 5'd1;

  assign dt_34 = (c_counter_0 + 3'd1) % 3'd5;

  assign result_53 = {(w13_0),({((~ w13_0)),({\c$_INTERNAL_.cout_app_arg_2 ,({\c$_INTERNAL_.cout_app_arg_1 ,({\c$_INTERNAL_.cout_app_arg ,({\c$_INTERNAL_.cout_app_arg_2 ,({\c$_INTERNAL_.cout_app_arg_0 ,({\c$_INTERNAL_.cout_app_arg ,({\c$_INTERNAL_.cout_app_arg_2 ,({\c$_INTERNAL_.cout_app_arg_0 ,({1'b1,({1'b0,({((w7 & c$w13_app_arg_0)),({(((~ w7) & c$w13_app_arg_0)),({\c$_INTERNAL_.cout_app_arg_1 ,({\c$_INTERNAL_.cout_app_arg_2 ,({\c$_INTERNAL_.cout_app_arg_1 ,({\c$_INTERNAL_.cout_app_arg_2 ,\c$_INTERNAL_.cout_app_arg_1 })})})})})})})})})})})})})})})})})};

  assign w13_0 = (cin_4[(64'sd1)]) & c$w13_app_arg_0;

  assign c$w13_app_arg_0 = cin_4[(64'sd0)];

  assign cin_4 = {result_54,({result_55,({result_56,({result_58,({result_61,result_60})})})})};

  assign \c$_INTERNAL_.cout_app_arg  = w11_0;

  always @(*) begin
    if(result_57)
      result_54 = 1'b1;
    else
      result_54 = 1'b0;
  end

  assign w11_0 = ((cin_4[(64'sd4)]) & \c$_INTERNAL_.cout_app_arg_3 ) & (cin_4[(64'sd5)]);

  always @(*) begin
    if(b_2)
      result_55 = 1'b1;
    else
      result_55 = 1'b0;
  end

  assign w17 = c_counter_0 - 3'd1;

  assign \c$_INTERNAL_.cout_app_arg_0  = w12_0;

  always @(*) begin
    if(b_3)
      result_56 = 1'b1;
    else
      result_56 = 1'b0;
  end

  assign b_2 = c$eta14_case_scrut[10:3] < c_tmpdist;

  always @(*) begin
    if(c$b_case_scrut)
      result_57 = result_59;
    else
      result_57 = result_59;
  end

  assign w12_0 = (~ w11_0) & \c$_INTERNAL_.cout_app_arg_3 ;

  always @(*) begin
    if(b_4)
      result_58 = 1'b1;
    else
      result_58 = 1'b0;
  end

  assign b_3 = c_ycoord == 5'd16;

  assign relativ_angle = ((c$eta14_case_scrut[18:11] - rotation) + ({{(8-5) {1'b0}},c_xcoord})) - 8'd16;

  assign result_59_selection_res = relativ_angle < c$$sincmod3_$jOut_app_arg;

  always @(*) begin
    if(result_59_selection_res)
      result_59 = \$j1 ;
    else
      result_59 = c$case_alt_1;
  end

  assign c$$j1_selection_res = c_ycoord > 5'd16;

  assign c$bv = (5'd16 - c_ycoord);

  assign c$bv_0 = (c_ycoord - 5'd16);

  always @(*) begin
    if(c$$j1_selection_res)
      \$j1  = ({{(8-5) {1'b0}},(c_ycoord - 5'd16)}) < c$$sincmod3_$jOut_app_arg;
    else
      \$j1  = ({{(8-5) {1'b0}},(5'd16 - c_ycoord)}) < c$$sincmod3_$jOut_app_arg;
  end

  assign c$case_alt_1_selection_res = relativ_angle > (8'd255 - c$$sincmod3_$jOut_app_arg);

  always @(*) begin
    if(c$case_alt_1_selection_res)
      c$case_alt_1 = \$j1 ;
    else
      c$case_alt_1 = 1'b0;
  end

  assign c$b_case_scrut = c$eta14_case_scrut[10:3] > 8'd0;

  always @(*) begin
    if(b_5)
      result_60 = 1'b1;
    else
      result_60 = 1'b0;
  end

  always @(*) begin
    if(b_6)
      result_61 = 1'b1;
    else
      result_61 = 1'b0;
  end

  assign b_4 = c_xcoord == 5'd16;

  always @(*) begin
    if(c$b_case_scrut)
      c$$sincmod3_$jOut_app_arg = 8'd255 / c$eta14_case_scrut[10:3];
    else
      c$$sincmod3_$jOut_app_arg = 8'd255;
  end

  assign b_5 = c_counter_0 == 3'd0;

  assign b_6 = c_xcoord == 5'd31;

  // index begin
  wire [18:0] vec_72 [0:4-1];

  genvar i_74;
  generate
  for (i_74=0; i_74 < 4; i_74=i_74+1) begin : mk_array_72
    assign vec_72[(4-1)-i_74] = enemies[i_74*19+:19];
  end
  endgenerate

  assign c$eta14_case_scrut = vec_72[(wild_0)];
  // index end

  assign c$i_260 = (w17 % 3'd4);

  assign wild_0 = $signed(($signed({{(64-3) {1'b0}},c$i_260})));

  assign w7 = (cin_4[(64'sd3)]) & (cin_4[(64'sd2)]);

  assign \c$_INTERNAL_.cout_app_arg_1  = \c$_INTERNAL_.cout_app_arg_3 ;

  assign \c$_INTERNAL_.cout_app_arg_2  = c$w13_app_arg_0;

  assign \c$_INTERNAL_.cout_app_arg_3  = ~ c$w13_app_arg_0;

  assign result_62 = {result_63[38:34]
                     ,result_63[33:29]
                     ,result_63[46:44]};

  assign result_63 = {result_66
                     ,result_73
                     ,result_64
                     ,result_74
                     ,result_68
                     ,result_67
                     ,result_70
                     ,result_69
                     ,result_65
                     ,result_72
                     ,result_71};

  assign result_64_selection_res = (bs_28[(64'sd0)]) == (1'b1);

  always @(*) begin
    if(result_64_selection_res)
      result_64 = c$o_color_case_alt_11;
    else
      result_64 = c$o_color_case_alt_12;
  end

  assign result_65_selection_res = (bs_29[(64'sd0)]) == (1'b1);

  always @(*) begin
    if(result_65_selection_res)
      result_65 = \c$_INTERNAL_.o_tmpcolor_case_alt_3 ;
    else
      result_65 = \c$_INTERNAL_.o_tmpcolor_case_alt_4 ;
  end

  assign result_66_selection_res = (bs_30[(64'sd0)]) == (1'b1);

  always @(*) begin
    if(result_66_selection_res)
      result_66 = \c$_INTERNAL_.o_buffercolor_case_alt ;
    else
      result_66 = \c$_INTERNAL_.o_buffercolor_case_alt_0 ;
  end

  assign result_67_selection_res = (bs_31[(64'sd0)]) == (1'b1);

  always @(*) begin
    if(result_67_selection_res)
      result_67 = c$o_outy_case_alt;
    else
      result_67 = c$o_outy_case_alt_0;
  end

  assign result_68_selection_res = (bs_32[(64'sd0)]) == (1'b1);

  always @(*) begin
    if(result_68_selection_res)
      result_68 = c$o_outx_case_alt;
    else
      result_68 = c$o_outx_case_alt_0;
  end

  assign result_69_selection_res = (bs_33[(64'sd0)]) == (1'b1);

  always @(*) begin
    if(result_69_selection_res)
      result_69 = c$o_ramreqsine_case_alt;
    else
      result_69 = c$o_ramreqsine_case_alt_0;
  end

  assign result_70_selection_res = (bs_34[(64'sd0)]) == (1'b1);

  always @(*) begin
    if(result_70_selection_res)
      result_70 = c$o_ramreqcosine_case_alt;
    else
      result_70 = c$o_ramreqcosine_case_alt_0;
  end

  assign result_71_selection_res = (bs_35[(64'sd0)]) == (1'b1);

  always @(*) begin
    if(result_71_selection_res)
      result_71 = \c$_INTERNAL_.o_ycoord_case_alt_1 ;
    else
      result_71 = \c$_INTERNAL_.o_ycoord_case_alt_2 ;
  end

  assign result_72_selection_res = (bs_36[(64'sd0)]) == (1'b1);

  always @(*) begin
    if(result_72_selection_res)
      result_72 = \c$_INTERNAL_.o_xcoord_case_alt_1 ;
    else
      result_72 = \c$_INTERNAL_.o_xcoord_case_alt_2 ;
  end

  assign result_73_selection_res = (bs_37[(64'sd0)]) == (1'b1);

  always @(*) begin
    if(result_73_selection_res)
      result_73 = \c$_INTERNAL_.o_bufferdradius_case_alt ;
    else
      result_73 = \c$_INTERNAL_.o_bufferdradius_case_alt_0 ;
  end

  assign result_74_selection_res = (bs_38[(64'sd0)]) == (1'b1);

  always @(*) begin
    if(result_74_selection_res)
      result_74 = \c$_INTERNAL_.o_counter_case_alt_3 ;
    else
      result_74 = \c$_INTERNAL_.o_counter_case_alt_4 ;
  end

  assign c$vecflat_71 = {dt_35,dt_36};

  // index begin
  wire [2:0] vec_73 [0:3-1];

  genvar i_75;
  generate
  for (i_75=0; i_75 < 3; i_75=i_75+1) begin : mk_array_73
    assign vec_73[(3-1)-i_75] = c$vecflat_71[i_75*3+:3];
  end
  endgenerate

  assign c$o_color_case_alt_11 = vec_73[(64'sd2)];
  // index end

  assign c$o_color_case_alt_12_selection_res = (bs_28[(64'sd1)]) == (1'b1);

  always @(*) begin
    if(c$o_color_case_alt_12_selection_res)
      c$o_color_case_alt_12 = c$o_color_case_alt_13;
    else
      c$o_color_case_alt_12 = c$o_color_case_alt_14;
  end

  assign c$vecflat_72 = {c_buffercolor,dt_37};

  // index begin
  wire [2:0] vec_74 [0:3-1];

  genvar i_76;
  generate
  for (i_76=0; i_76 < 3; i_76=i_76+1) begin : mk_array_74
    assign vec_74[(3-1)-i_76] = c$vecflat_72[i_76*3+:3];
  end
  endgenerate

  assign \c$_INTERNAL_.o_tmpcolor_case_alt_3  = vec_74[(64'sd2)];
  // index end

  assign \c$_INTERNAL_.o_tmpcolor_case_alt_4_selection_res  = (bs_29[(64'sd1)]) == (1'b1);

  always @(*) begin
    if(\c$_INTERNAL_.o_tmpcolor_case_alt_4_selection_res )
      \c$_INTERNAL_.o_tmpcolor_case_alt_4  = \c$_INTERNAL_.o_tmpcolor_case_alt_5 ;
    else
      \c$_INTERNAL_.o_tmpcolor_case_alt_4  = \c$_INTERNAL_.o_tmpcolor_case_alt_6 ;
  end

  assign c$vecflat_73 = {c_buffercolor
                        ,c$dt_case_scrut_4[2:0]};

  // index begin
  wire [2:0] vec_75 [0:2-1];

  genvar i_77;
  generate
  for (i_77=0; i_77 < 2; i_77=i_77+1) begin : mk_array_75
    assign vec_75[(2-1)-i_77] = c$vecflat_73[i_77*3+:3];
  end
  endgenerate

  assign \c$_INTERNAL_.o_buffercolor_case_alt  = vec_75[(64'sd1)];
  // index end

  assign c$vecflat_74 = {c_buffercolor
                        ,c$dt_case_scrut_4[2:0]};

  // index begin
  wire [2:0] vec_76 [0:2-1];

  genvar i_78;
  generate
  for (i_78=0; i_78 < 2; i_78=i_78+1) begin : mk_array_76
    assign vec_76[(2-1)-i_78] = c$vecflat_74[i_78*3+:3];
  end
  endgenerate

  assign \c$_INTERNAL_.o_buffercolor_case_alt_0  = vec_76[(64'sd0)];
  // index end

  assign c$vecflat_75 = {dt_38,dt_39};

  // index begin
  wire [4:0] vec_77 [0:2-1];

  genvar i_79;
  generate
  for (i_79=0; i_79 < 2; i_79=i_79+1) begin : mk_array_77
    assign vec_77[(2-1)-i_79] = c$vecflat_75[i_79*5+:5];
  end
  endgenerate

  assign c$o_outy_case_alt = vec_77[(64'sd1)];
  // index end

  assign c$vecflat_76 = {dt_38,dt_39};

  // index begin
  wire [4:0] vec_78 [0:2-1];

  genvar i_80;
  generate
  for (i_80=0; i_80 < 2; i_80=i_80+1) begin : mk_array_78
    assign vec_78[(2-1)-i_80] = c$vecflat_76[i_80*5+:5];
  end
  endgenerate

  assign c$o_outy_case_alt_0 = vec_78[(64'sd0)];
  // index end

  assign c$vecflat_77 = {dt_40,dt_41};

  // index begin
  wire [4:0] vec_79 [0:2-1];

  genvar i_81;
  generate
  for (i_81=0; i_81 < 2; i_81=i_81+1) begin : mk_array_79
    assign vec_79[(2-1)-i_81] = c$vecflat_77[i_81*5+:5];
  end
  endgenerate

  assign c$o_outx_case_alt = vec_79[(64'sd1)];
  // index end

  assign c$vecflat_78 = {dt_40,dt_41};

  // index begin
  wire [4:0] vec_80 [0:2-1];

  genvar i_82;
  generate
  for (i_82=0; i_82 < 2; i_82=i_82+1) begin : mk_array_80
    assign vec_80[(2-1)-i_82] = c$vecflat_78[i_82*5+:5];
  end
  endgenerate

  assign c$o_outx_case_alt_0 = vec_80[(64'sd0)];
  // index end

  assign c$vecflat_79 = {dt_42,dt_43};

  // index begin
  wire [7:0] vec_81 [0:2-1];

  genvar i_83;
  generate
  for (i_83=0; i_83 < 2; i_83=i_83+1) begin : mk_array_81
    assign vec_81[(2-1)-i_83] = c$vecflat_79[i_83*8+:8];
  end
  endgenerate

  assign c$o_ramreqsine_case_alt = vec_81[(64'sd1)];
  // index end

  assign c$vecflat_80 = {dt_42,dt_43};

  // index begin
  wire [7:0] vec_82 [0:2-1];

  genvar i_84;
  generate
  for (i_84=0; i_84 < 2; i_84=i_84+1) begin : mk_array_82
    assign vec_82[(2-1)-i_84] = c$vecflat_80[i_84*8+:8];
  end
  endgenerate

  assign c$o_ramreqsine_case_alt_0 = vec_82[(64'sd0)];
  // index end

  assign c$vecflat_81 = {dt_44,dt_43};

  // index begin
  wire [7:0] vec_83 [0:2-1];

  genvar i_85;
  generate
  for (i_85=0; i_85 < 2; i_85=i_85+1) begin : mk_array_83
    assign vec_83[(2-1)-i_85] = c$vecflat_81[i_85*8+:8];
  end
  endgenerate

  assign c$o_ramreqcosine_case_alt = vec_83[(64'sd1)];
  // index end

  assign c$vecflat_82 = {dt_44,dt_43};

  // index begin
  wire [7:0] vec_84 [0:2-1];

  genvar i_86;
  generate
  for (i_86=0; i_86 < 2; i_86=i_86+1) begin : mk_array_84
    assign vec_84[(2-1)-i_86] = c$vecflat_82[i_86*8+:8];
  end
  endgenerate

  assign c$o_ramreqcosine_case_alt_0 = vec_84[(64'sd0)];
  // index end

  assign c$vecflat_83 = {c_ycoord_0,dt_45};

  // index begin
  wire [4:0] vec_85 [0:2-1];

  genvar i_87;
  generate
  for (i_87=0; i_87 < 2; i_87=i_87+1) begin : mk_array_85
    assign vec_85[(2-1)-i_87] = c$vecflat_83[i_87*5+:5];
  end
  endgenerate

  assign \c$_INTERNAL_.o_ycoord_case_alt_1  = vec_85[(64'sd1)];
  // index end

  assign c$vecflat_84 = {c_ycoord_0,dt_45};

  // index begin
  wire [4:0] vec_86 [0:2-1];

  genvar i_88;
  generate
  for (i_88=0; i_88 < 2; i_88=i_88+1) begin : mk_array_86
    assign vec_86[(2-1)-i_88] = c$vecflat_84[i_88*5+:5];
  end
  endgenerate

  assign \c$_INTERNAL_.o_ycoord_case_alt_2  = vec_86[(64'sd0)];
  // index end

  assign c$vecflat_85 = {c_xcoord_0,dt_46};

  // index begin
  wire [4:0] vec_87 [0:2-1];

  genvar i_89;
  generate
  for (i_89=0; i_89 < 2; i_89=i_89+1) begin : mk_array_87
    assign vec_87[(2-1)-i_89] = c$vecflat_85[i_89*5+:5];
  end
  endgenerate

  assign \c$_INTERNAL_.o_xcoord_case_alt_1  = vec_87[(64'sd1)];
  // index end

  assign c$vecflat_86 = {c_xcoord_0,dt_46};

  // index begin
  wire [4:0] vec_88 [0:2-1];

  genvar i_90;
  generate
  for (i_90=0; i_90 < 2; i_90=i_90+1) begin : mk_array_88
    assign vec_88[(2-1)-i_90] = c$vecflat_86[i_90*5+:5];
  end
  endgenerate

  assign \c$_INTERNAL_.o_xcoord_case_alt_2  = vec_88[(64'sd0)];
  // index end

  assign c$vecflat_87 = {c_bufferdradius
                        ,c$dt_case_scrut_4[10:3]};

  // index begin
  wire [7:0] vec_89 [0:2-1];

  genvar i_91;
  generate
  for (i_91=0; i_91 < 2; i_91=i_91+1) begin : mk_array_89
    assign vec_89[(2-1)-i_91] = c$vecflat_87[i_91*8+:8];
  end
  endgenerate

  assign \c$_INTERNAL_.o_bufferdradius_case_alt  = vec_89[(64'sd1)];
  // index end

  assign c$vecflat_88 = {c_bufferdradius
                        ,c$dt_case_scrut_4[10:3]};

  // index begin
  wire [7:0] vec_90 [0:2-1];

  genvar i_92;
  generate
  for (i_92=0; i_92 < 2; i_92=i_92+1) begin : mk_array_90
    assign vec_90[(2-1)-i_92] = c$vecflat_88[i_92*8+:8];
  end
  endgenerate

  assign \c$_INTERNAL_.o_bufferdradius_case_alt_0  = vec_90[(64'sd0)];
  // index end

  assign c$vecflat_89 = {c_counter_1,dt_47};

  // index begin
  wire [4:0] vec_91 [0:2-1];

  genvar i_93;
  generate
  for (i_93=0; i_93 < 2; i_93=i_93+1) begin : mk_array_91
    assign vec_91[(2-1)-i_93] = c$vecflat_89[i_93*5+:5];
  end
  endgenerate

  assign \c$_INTERNAL_.o_counter_case_alt_3  = vec_91[(64'sd1)];
  // index end

  assign c$vecflat_90 = {c_counter_1,dt_47};

  // index begin
  wire [4:0] vec_92 [0:2-1];

  genvar i_94;
  generate
  for (i_94=0; i_94 < 2; i_94=i_94+1) begin : mk_array_92
    assign vec_92[(2-1)-i_94] = c$vecflat_90[i_94*5+:5];
  end
  endgenerate

  assign \c$_INTERNAL_.o_counter_case_alt_4  = vec_92[(64'sd0)];
  // index end

  assign c$vecflat_91 = {dt_35,dt_36};

  // index begin
  wire [2:0] vec_93 [0:3-1];

  genvar i_95;
  generate
  for (i_95=0; i_95 < 3; i_95=i_95+1) begin : mk_array_93
    assign vec_93[(3-1)-i_95] = c$vecflat_91[i_95*3+:3];
  end
  endgenerate

  assign c$o_color_case_alt_13 = vec_93[(64'sd1)];
  // index end

  assign c$vecflat_92 = {dt_35,dt_36};

  // index begin
  wire [2:0] vec_94 [0:3-1];

  genvar i_96;
  generate
  for (i_96=0; i_96 < 3; i_96=i_96+1) begin : mk_array_94
    assign vec_94[(3-1)-i_96] = c$vecflat_92[i_96*3+:3];
  end
  endgenerate

  assign c$o_color_case_alt_14 = vec_94[(64'sd0)];
  // index end

  assign c$vecflat_93 = {c_buffercolor,dt_37};

  // index begin
  wire [2:0] vec_95 [0:3-1];

  genvar i_97;
  generate
  for (i_97=0; i_97 < 3; i_97=i_97+1) begin : mk_array_95
    assign vec_95[(3-1)-i_97] = c$vecflat_93[i_97*3+:3];
  end
  endgenerate

  assign \c$_INTERNAL_.o_tmpcolor_case_alt_5  = vec_95[(64'sd1)];
  // index end

  assign c$vecflat_94 = {c_buffercolor,dt_37};

  // index begin
  wire [2:0] vec_96 [0:3-1];

  genvar i_98;
  generate
  for (i_98=0; i_98 < 3; i_98=i_98+1) begin : mk_array_96
    assign vec_96[(3-1)-i_98] = c$vecflat_94[i_98*3+:3];
  end
  endgenerate

  assign \c$_INTERNAL_.o_tmpcolor_case_alt_6  = vec_96[(64'sd0)];
  // index end

  assign bs_28 = {((result_75[(64'sd4)])),({((result_75[(64'sd5)])),((result_75[(64'sd6)]))})};

  assign bs_29 = {((result_75[(64'sd17)])),({((result_75[(64'sd18)])),((result_75[(64'sd19)]))})};

  assign bs_30 = {((result_75[(64'sd0)])),((result_75[(64'sd1)]))};

  assign bs_31 = {((result_75[(64'sd11)])),((result_75[(64'sd12)]))};

  assign bs_32 = {((result_75[(64'sd9)])),((result_75[(64'sd10)]))};

  assign bs_33 = {((result_75[(64'sd15)])),((result_75[(64'sd16)]))};

  assign bs_34 = {((result_75[(64'sd13)])),((result_75[(64'sd14)]))};

  assign bs_35 = {((result_75[(64'sd22)])),((result_75[(64'sd23)]))};

  assign bs_36 = {((result_75[(64'sd20)])),((result_75[(64'sd21)]))};

  assign bs_37 = {((result_75[(64'sd2)])),((result_75[(64'sd3)]))};

  assign bs_38 = {((result_75[(64'sd7)])),((result_75[(64'sd8)]))};

  // register begin
  reg [4:0] c_ycoord_0_reg = 5'd0;
  always @(posedge \$d(%,%) [1:1] or posedge \$d(%,%) [0:0]) begin : c_ycoord_0_register
    if (\$d(%,%) [0:0]) begin
      c_ycoord_0_reg <= 5'd0;
    end else begin
      c_ycoord_0_reg <= result_71;
    end
  end
  assign c_ycoord_0 = c_ycoord_0_reg;
  // register end

  // register begin
  reg [4:0] c_xcoord_0_reg = 5'd0;
  always @(posedge \$d(%,%) [1:1] or posedge \$d(%,%) [0:0]) begin : c_xcoord_0_register
    if (\$d(%,%) [0:0]) begin
      c_xcoord_0_reg <= 5'd0;
    end else begin
      c_xcoord_0_reg <= result_72;
    end
  end
  assign c_xcoord_0 = c_xcoord_0_reg;
  // register end

  // register begin
  reg [7:0] c_bufferdradius_reg = 8'd255;
  always @(posedge \$d(%,%) [1:1] or posedge \$d(%,%) [0:0]) begin : c_bufferdradius_register
    if (\$d(%,%) [0:0]) begin
      c_bufferdradius_reg <= 8'd255;
    end else begin
      c_bufferdradius_reg <= result_73;
    end
  end
  assign c_bufferdradius = c_bufferdradius_reg;
  // register end

  // register begin
  reg [4:0] c_counter_1_reg = 5'd0;
  always @(posedge \$d(%,%) [1:1] or posedge \$d(%,%) [0:0]) begin : c_counter_1_register
    if (\$d(%,%) [0:0]) begin
      c_counter_1_reg <= 5'd0;
    end else begin
      c_counter_1_reg <= result_74;
    end
  end
  assign c_counter_1 = c_counter_1_reg;
  // register end

  // register begin
  reg [2:0] c_buffercolor_reg = 3'b000;
  always @(posedge \$d(%,%) [1:1] or posedge \$d(%,%) [0:0]) begin : c_buffercolor_register
    if (\$d(%,%) [0:0]) begin
      c_buffercolor_reg <= 3'b000;
    end else begin
      c_buffercolor_reg <= result_66;
    end
  end
  assign c_buffercolor = c_buffercolor_reg;
  // register end

  // register begin
  reg [2:0] dt_35_reg = 3'b000;
  always @(posedge \$d(%,%) [1:1] or posedge \$d(%,%) [0:0]) begin : dt_35_register
    if (\$d(%,%) [0:0]) begin
      dt_35_reg <= 3'b000;
    end else begin
      dt_35_reg <= result_64;
    end
  end
  assign dt_35 = dt_35_reg;
  // register end

  assign dt_36 = {c_tmpcolor_0,3'b111};

  assign dt_37 = {c_tmpcolor_0,3'b000};

  // register begin
  reg [4:0] dt_38_reg = 5'd0;
  always @(posedge \$d(%,%) [1:1] or posedge \$d(%,%) [0:0]) begin : dt_38_register
    if (\$d(%,%) [0:0]) begin
      dt_38_reg <= 5'd0;
    end else begin
      dt_38_reg <= result_67;
    end
  end
  assign dt_38 = dt_38_reg;
  // register end

  assign dt_39 = c_ycoord_0;

  // register begin
  reg [4:0] dt_40_reg = 5'd0;
  always @(posedge \$d(%,%) [1:1] or posedge \$d(%,%) [0:0]) begin : dt_40_register
    if (\$d(%,%) [0:0]) begin
      dt_40_reg <= 5'd0;
    end else begin
      dt_40_reg <= result_68;
    end
  end
  assign dt_40 = dt_40_reg;
  // register end

  assign dt_41 = c_xcoord_0;

  // register begin
  reg [7:0] dt_42_reg = 8'd0;
  always @(posedge \$d(%,%) [1:1] or posedge \$d(%,%) [0:0]) begin : dt_42_register
    if (\$d(%,%) [0:0]) begin
      dt_42_reg <= 8'd0;
    end else begin
      dt_42_reg <= result_69;
    end
  end
  assign dt_42 = dt_42_reg;
  // register end

  assign dt_43 = w30_0;

  // register begin
  reg [7:0] dt_44_reg = 8'd0;
  always @(posedge \$d(%,%) [1:1] or posedge \$d(%,%) [0:0]) begin : dt_44_register
    if (\$d(%,%) [0:0]) begin
      dt_44_reg <= 8'd0;
    end else begin
      dt_44_reg <= result_70;
    end
  end
  assign dt_44 = dt_44_reg;
  // register end

  assign w30_0 = c$dt_case_scrut_4[18:11] - rotation;

  // register begin
  reg [2:0] c_tmpcolor_0_reg = 3'b000;
  always @(posedge \$d(%,%) [1:1] or posedge \$d(%,%) [0:0]) begin : c_tmpcolor_0_register
    if (\$d(%,%) [0:0]) begin
      c_tmpcolor_0_reg <= 3'b000;
    end else begin
      c_tmpcolor_0_reg <= result_65;
    end
  end
  assign c_tmpcolor_0 = c_tmpcolor_0_reg;
  // register end

  assign dt_45 = c_ycoord_0 + 5'd1;

  assign dt_46 = c_xcoord_0 + 5'd1;

  assign dt_47 = (c_counter_1 + 5'd1) % 5'd6;

  assign result_75 = {(w11_1),({((~ w11_1)),({\c$_INTERNAL_.cout_app_arg_4 ,({\c$_INTERNAL_.cout_app_arg_5 ,({\c$_INTERNAL_.cout_app_arg_4 ,({(((~ w8_0) & \c$_INTERNAL_.cout_app_arg_7 )),({((w8_0 & \c$_INTERNAL_.cout_app_arg_7 )),({1'b1,({1'b0,({1'b1,({1'b0,({\c$_INTERNAL_.cout_app_arg_4 ,({\c$_INTERNAL_.cout_app_arg_5 ,({\c$_INTERNAL_.cout_app_arg_4 ,({\c$_INTERNAL_.cout_app_arg_5 ,({1'b1,({1'b0,({((\c$_INTERNAL_.cout_app_arg_6  & c$w11_app_arg_0)),({(((~ \c$_INTERNAL_.cout_app_arg_6 ) & c$w11_app_arg_0)),({\c$_INTERNAL_.cout_app_arg_5 ,4'b1010})})})})})})})})})})})})})})})})})})})};

  // index begin
  wire [18:0] vec_97 [0:4-1];

  genvar i_99;
  generate
  for (i_99=0; i_99 < 4; i_99=i_99+1) begin : mk_array_97
    assign vec_97[(4-1)-i_99] = enemies[i_99*19+:19];
  end
  endgenerate

  assign c$dt_case_scrut_4 = vec_97[(wild_1)];
  // index end

  assign w11_1 = (cin_5[(64'sd1)]) & c$w11_app_arg_0;

  assign c$i_297 = (c_counter_1 % 5'd4);

  assign wild_1 = $signed(($signed({{(64-5) {1'b0}},c$i_297})));

  assign c$w11_app_arg_0 = cin_5[(64'sd0)];

  assign cin_5 = {result_76,({result_77,({result_78,({result_81,result_80})})})};

  always @(*) begin
    if(result_79)
      result_76 = 1'b1;
    else
      result_76 = 1'b0;
  end

  always @(*) begin
    if(b_7)
      result_77 = 1'b1;
    else
      result_77 = 1'b0;
  end

  always @(*) begin
    if(b_8)
      result_78 = 1'b1;
    else
      result_78 = 1'b0;
  end

  assign b_7 = c_ycoord_0 == c$b_app_arg;

  always @(*) begin
    case(c_xcoord_0)
      5'd15 : result_79 = \$j ;
      5'd16 : result_79 = \$j ;
      default : result_79 = 1'b0;
    endcase
  end

  always @(*) begin
    if(b_9)
      result_80 = 1'b1;
    else
      result_80 = 1'b0;
  end

  always @(*) begin
    if(b_10)
      result_81 = 1'b1;
    else
      result_81 = 1'b0;
  end

  assign b_8 = c_xcoord_0 == c$b_app_arg_0;

  assign c$s = (result_82 >>> (64'sd5));

  assign c$bv_1 = (($unsigned(($signed({c$s[15-1],c$s[0+:(10-1)]})))));

  assign c$b_app_arg = c$bv_1[0+:5];

  always @(*) begin
    case(c_ycoord_0)
      5'd15 : \$j  = 1'b1;
      default : \$j  = c_ycoord_0 == 5'd16;
    endcase
  end

  assign w8_0 = (cin_5[(64'sd3)]) & (cin_5[(64'sd2)]);

  assign b_9 = c_counter_1 == 5'd5;

  assign b_10 = c_xcoord_0 == 5'd31;

  assign c$s_0 = (result_83 >>> (64'sd5));

  assign c$bv_2 = (($unsigned(($signed({c$s_0[15-1],c$s_0[0+:(10-1)]})))));

  assign c$b_app_arg_0 = c$bv_2[0+:5];

  assign r = result_84 + 15'sd512;

  assign c$app_arg_8 = $unsigned(r);

  assign \c$r'_projection  = c$app_arg_8;

  assign \r'  = \c$r'_projection [14:0];

  assign c$bv_3 = ($unsigned(result_84));

  assign c$case_alt_2_selection_res = (( c$bv_3[15-1] ) & 1'b0) == 1'b0;

  always @(*) begin
    if(c$case_alt_2_selection_res)
      c$case_alt_2 = 15'sd16383;
    else
      c$case_alt_2 = -15'sd16384;
  end

  assign result_82_selection_res = (( c$app_arg_8[16-1] ) ^ ( \r' [15-1] )) == 1'b0;

  always @(*) begin
    if(result_82_selection_res)
      result_82 = $signed(\r' );
    else
      result_82 = c$case_alt_2;
  end

  assign r_0 = result_85 + 15'sd512;

  assign c$app_arg_9 = $unsigned(r_0);

  assign \c$r'_0_projection  = c$app_arg_9;

  assign \c$r'_0  = \c$r'_0_projection [14:0];

  assign c$bv_4 = ($unsigned(result_85));

  assign c$case_alt_3_selection_res = (( c$bv_4[15-1] ) & 1'b0) == 1'b0;

  always @(*) begin
    if(c$case_alt_3_selection_res)
      c$case_alt_3 = 15'sd16383;
    else
      c$case_alt_3 = -15'sd16384;
  end

  assign result_83_selection_res = (( c$app_arg_9[16-1] ) ^ ( \c$r'_0 [15-1] )) == 1'b0;

  always @(*) begin
    if(result_83_selection_res)
      result_83 = $signed(\c$r'_0 );
    else
      result_83 = c$case_alt_3;
  end

  assign result_84_selection_res = ((~ (| (x_0))) | (& (x_0))) == 1'b1;

  assign c$bv_5 = (rR >> (64'sd5));

  always @(*) begin
    if(result_84_selection_res)
      result_84 = $signed((c$bv_5[0+:15]));
    else
      result_84 = c$case_alt_4;
  end

  assign c$case_alt_4_selection_res = ( rL[10-1] ) == 1'b0;

  always @(*) begin
    if(c$case_alt_4_selection_res)
      c$case_alt_4 = 15'sd16383;
    else
      c$case_alt_4 = -15'sd16384;
  end

  assign rL = ds3[29:20];

  assign rR = ds3[19:0];

  assign ds3 = ($unsigned(c$ds3_app_arg));

  assign x_0 = {(( rR[20-1] )),rL};

  assign c$ds3_app_arg = result_87 * result_86;

  assign result_85_selection_res = ((~ (| (x_1))) | (& (x_1))) == 1'b1;

  assign c$bv_6 = (rR_0 >> (64'sd5));

  always @(*) begin
    if(result_85_selection_res)
      result_85 = $signed((c$bv_6[0+:15]));
    else
      result_85 = c$case_alt_5;
  end

  assign c$case_alt_5_selection_res = ( rL_0[10-1] ) == 1'b0;

  always @(*) begin
    if(c$case_alt_5_selection_res)
      c$case_alt_5 = 15'sd16383;
    else
      c$case_alt_5 = -15'sd16384;
  end

  assign rL_0 = ds3_0[29:20];

  assign rR_0 = ds3_0[19:0];

  assign ds3_0 = ($unsigned(c$ds3_app_arg_0));

  assign x_1 = {(( rR_0[20-1] )),rL_0};

  assign c$ds3_app_arg_0 = result_88 * result_86;

  assign c$case_scrut = shiftedR & -31'sd16384;

  assign c$case_alt_6 = $signed({shiftedR[31-1],shiftedR[0+:(15-1)]});

  assign c$case_alt_7_selection_res = c$case_scrut == -31'sd16384;

  always @(*) begin
    if(c$case_alt_7_selection_res)
      c$case_alt_7 = c$case_alt_6;
    else
      c$case_alt_7 = -15'sd16384;
  end

  always @(*) begin
    case(c$case_scrut)
      31'sd0 : c$case_alt_8 = c$case_alt_6;
      default : c$case_alt_8 = 15'sd16383;
    endcase
  end

  assign shiftedR = ds >>> (64'sd10);

  assign result_86_selection_res = ds >= 31'sd0;

  always @(*) begin
    if(result_86_selection_res)
      result_86 = c$case_alt_8;
    else
      result_86 = c$case_alt_7;
  end

  assign c$s_1 = ($signed(({(({{(10-8) {1'b0}},c_bufferdradius})),5'b00000})));

  assign ds = (($signed({{(31-15) {c$s_1[15-1]}},c$s_1})) <<< (64'sd15)) / 31'sd512;

  assign \c$_INTERNAL_.cout_app_arg_4  = c$w11_app_arg_0;

  assign \c$_INTERNAL_.cout_app_arg_5  = \c$_INTERNAL_.cout_app_arg_7 ;

  assign \c$_INTERNAL_.cout_app_arg_6  = cin_5[(64'sd4)];

  assign \c$_INTERNAL_.cout_app_arg_7  = ~ c$w11_app_arg_0;

  assign result_87 = $signed(bv);

  assign c$i_328 = ({8 {1'bx}});

  assign bv_res = $signed(($signed({{(64-8) {1'b0}},c$i_328})));

  // blockRamFile begin
  reg [14:0] RAM [0:256-1];

  initial begin
    $readmemb("../SinusTableInit.txt",RAM);
  end

  always @(posedge \$d(%,%) [1:1]) begin : TopEntity_blockRamFile
    if (1'b0) begin
      RAM[(bv_res)] <= ({15 {1'bx}});
    end
    bv <= RAM[(wild_2)];
  end
  // blockRamFile end

  assign c$i_330 = (a_0 + 8'd64);

  assign wild_2 = $signed(($signed({{(64-8) {1'b0}},c$i_330})));

  assign result_88 = $signed(bv_0);

  assign c$i_331 = ({8 {1'bx}});

  assign bv_0_res = $signed(($signed({{(64-8) {1'b0}},c$i_331})));

  // blockRamFile begin
  reg [14:0] RAM_0 [0:256-1];

  initial begin
    $readmemb("../SinusTableInit_.txt",RAM_0);
  end

  always @(posedge \$d(%,%) [1:1]) begin : TopEntity_blockRamFile_0
    if (1'b0) begin
      RAM_0[(bv_0_res)] <= ({15 {1'bx}});
    end
    bv_0 <= RAM_0[(wild_3)];
  end
  // blockRamFile end

  assign c$i_333 = (a_1 + 8'd128);

  assign wild_3 = $signed(($signed({{(64-8) {1'b0}},c$i_333})));

  assign a_0 = result_63[20:13];

  assign a_1 = result_63[28:21];

  assign result_89 = {result_90[19:15]
                     ,result_90[14:10]
                     ,result_90[22:20]};

  assign result_90 = {result_91
                     ,result_92
                     ,result_93
                     ,result_94
                     ,result_95};

  assign result_91_selection_res = (bs_39[(64'sd0)]) == (1'b1);

  always @(*) begin
    if(result_91_selection_res)
      result_91 = c$o_actcolor_case_alt;
    else
      result_91 = c$o_actcolor_case_alt_0;
  end

  assign result_92_selection_res = (bs_40[(64'sd0)]) == (1'b1);

  always @(*) begin
    if(result_92_selection_res)
      result_92 = c$o_bxcoord_case_alt_1;
    else
      result_92 = c$o_bxcoord_case_alt_2;
  end

  assign result_93_selection_res = (bs_41[(64'sd0)]) == (1'b1);

  always @(*) begin
    if(result_93_selection_res)
      result_93 = c$o_bycoord_case_alt_1;
    else
      result_93 = c$o_bycoord_case_alt_2;
  end

  assign result_94_selection_res = (bs_42[(64'sd0)]) == (1'b1);

  always @(*) begin
    if(result_94_selection_res)
      result_94 = \c$_INTERNAL_.o_xcoord_case_alt_3 ;
    else
      result_94 = \c$_INTERNAL_.o_xcoord_case_alt_4 ;
  end

  assign result_95_selection_res = (bs_43[(64'sd0)]) == (1'b1);

  always @(*) begin
    if(result_95_selection_res)
      result_95 = \c$_INTERNAL_.o_ycoord_case_alt_3 ;
    else
      result_95 = \c$_INTERNAL_.o_ycoord_case_alt_4 ;
  end

  assign c$vecflat_95 = {dt_48
                        ,{3'b000,{3'b100,dt_55}}};

  // index begin
  wire [2:0] vec_98 [0:4-1];

  genvar i_100;
  generate
  for (i_100=0; i_100 < 4; i_100=i_100+1) begin : mk_array_98
    assign vec_98[(4-1)-i_100] = c$vecflat_95[i_100*3+:3];
  end
  endgenerate

  assign c$o_actcolor_case_alt = vec_98[(64'sd3)];
  // index end

  assign c$o_actcolor_case_alt_0_selection_res = (bs_39[(64'sd1)]) == (1'b1);

  always @(*) begin
    if(c$o_actcolor_case_alt_0_selection_res)
      c$o_actcolor_case_alt_0 = c$o_actcolor_case_alt_1;
    else
      c$o_actcolor_case_alt_0 = c$o_actcolor_case_alt_2;
  end

  assign c$vecflat_96 = {dt_49,dt_50};

  // index begin
  wire [4:0] vec_99 [0:2-1];

  genvar i_101;
  generate
  for (i_101=0; i_101 < 2; i_101=i_101+1) begin : mk_array_99
    assign vec_99[(2-1)-i_101] = c$vecflat_96[i_101*5+:5];
  end
  endgenerate

  assign c$o_bxcoord_case_alt_1 = vec_99[(64'sd1)];
  // index end

  assign c$vecflat_97 = {dt_49,dt_50};

  // index begin
  wire [4:0] vec_100 [0:2-1];

  genvar i_102;
  generate
  for (i_102=0; i_102 < 2; i_102=i_102+1) begin : mk_array_100
    assign vec_100[(2-1)-i_102] = c$vecflat_97[i_102*5+:5];
  end
  endgenerate

  assign c$o_bxcoord_case_alt_2 = vec_100[(64'sd0)];
  // index end

  assign c$vecflat_98 = {dt_51,dt_52};

  // index begin
  wire [4:0] vec_101 [0:2-1];

  genvar i_103;
  generate
  for (i_103=0; i_103 < 2; i_103=i_103+1) begin : mk_array_101
    assign vec_101[(2-1)-i_103] = c$vecflat_98[i_103*5+:5];
  end
  endgenerate

  assign c$o_bycoord_case_alt_1 = vec_101[(64'sd1)];
  // index end

  assign c$vecflat_99 = {dt_51,dt_52};

  // index begin
  wire [4:0] vec_102 [0:2-1];

  genvar i_104;
  generate
  for (i_104=0; i_104 < 2; i_104=i_104+1) begin : mk_array_102
    assign vec_102[(2-1)-i_104] = c$vecflat_99[i_104*5+:5];
  end
  endgenerate

  assign c$o_bycoord_case_alt_2 = vec_102[(64'sd0)];
  // index end

  assign c$vecflat_100 = {dt_53,dt_50};

  // index begin
  wire [4:0] vec_103 [0:2-1];

  genvar i_105;
  generate
  for (i_105=0; i_105 < 2; i_105=i_105+1) begin : mk_array_103
    assign vec_103[(2-1)-i_105] = c$vecflat_100[i_105*5+:5];
  end
  endgenerate

  assign \c$_INTERNAL_.o_xcoord_case_alt_3  = vec_103[(64'sd1)];
  // index end

  assign c$vecflat_101 = {dt_53,dt_50};

  // index begin
  wire [4:0] vec_104 [0:2-1];

  genvar i_106;
  generate
  for (i_106=0; i_106 < 2; i_106=i_106+1) begin : mk_array_104
    assign vec_104[(2-1)-i_106] = c$vecflat_101[i_106*5+:5];
  end
  endgenerate

  assign \c$_INTERNAL_.o_xcoord_case_alt_4  = vec_104[(64'sd0)];
  // index end

  assign c$vecflat_102 = {dt_54,dt_52};

  // index begin
  wire [4:0] vec_105 [0:2-1];

  genvar i_107;
  generate
  for (i_107=0; i_107 < 2; i_107=i_107+1) begin : mk_array_105
    assign vec_105[(2-1)-i_107] = c$vecflat_102[i_107*5+:5];
  end
  endgenerate

  assign \c$_INTERNAL_.o_ycoord_case_alt_3  = vec_105[(64'sd1)];
  // index end

  assign c$vecflat_103 = {dt_54,dt_52};

  // index begin
  wire [4:0] vec_106 [0:2-1];

  genvar i_108;
  generate
  for (i_108=0; i_108 < 2; i_108=i_108+1) begin : mk_array_106
    assign vec_106[(2-1)-i_108] = c$vecflat_103[i_108*5+:5];
  end
  endgenerate

  assign \c$_INTERNAL_.o_ycoord_case_alt_4  = vec_106[(64'sd0)];
  // index end

  assign c$vecflat_104 = {dt_48
                         ,{3'b000,{3'b100,dt_55}}};

  // index begin
  wire [2:0] vec_107 [0:4-1];

  genvar i_109;
  generate
  for (i_109=0; i_109 < 4; i_109=i_109+1) begin : mk_array_107
    assign vec_107[(4-1)-i_109] = c$vecflat_104[i_109*3+:3];
  end
  endgenerate

  assign c$o_actcolor_case_alt_1 = vec_107[(64'sd2)];
  // index end

  assign c$o_actcolor_case_alt_2_selection_res = (bs_39[(64'sd2)]) == (1'b1);

  always @(*) begin
    if(c$o_actcolor_case_alt_2_selection_res)
      c$o_actcolor_case_alt_2 = c$o_actcolor_case_alt_3;
    else
      c$o_actcolor_case_alt_2 = c$o_actcolor_case_alt_4;
  end

  assign bs_39 = {((result_96[(64'sd0)])),({((result_96[(64'sd1)])),({((result_96[(64'sd2)])),((result_96[(64'sd3)]))})})};

  assign c$vecflat_105 = {dt_48
                         ,{3'b000,{3'b100,dt_55}}};

  // index begin
  wire [2:0] vec_108 [0:4-1];

  genvar i_110;
  generate
  for (i_110=0; i_110 < 4; i_110=i_110+1) begin : mk_array_108
    assign vec_108[(4-1)-i_110] = c$vecflat_105[i_110*3+:3];
  end
  endgenerate

  assign c$o_actcolor_case_alt_3 = vec_108[(64'sd1)];
  // index end

  assign c$vecflat_106 = {dt_48
                         ,{3'b000,{3'b100,dt_55}}};

  // index begin
  wire [2:0] vec_109 [0:4-1];

  genvar i_111;
  generate
  for (i_111=0; i_111 < 4; i_111=i_111+1) begin : mk_array_109
    assign vec_109[(4-1)-i_111] = c$vecflat_106[i_111*3+:3];
  end
  endgenerate

  assign c$o_actcolor_case_alt_4 = vec_109[(64'sd0)];
  // index end

  assign bs_40 = {((result_96[(64'sd4)])),((result_96[(64'sd5)]))};

  assign bs_41 = {((result_96[(64'sd6)])),((result_96[(64'sd7)]))};

  assign bs_42 = {((result_96[(64'sd8)])),((result_96[(64'sd9)]))};

  assign bs_43 = {((result_96[(64'sd10)])),((result_96[(64'sd11)]))};

  // register begin
  reg [2:0] dt_48_reg = 3'b000;
  always @(posedge \$d(%,%) [1:1] or posedge \$d(%,%) [0:0]) begin : dt_48_register
    if (\$d(%,%) [0:0]) begin
      dt_48_reg <= 3'b000;
    end else begin
      dt_48_reg <= result_91;
    end
  end
  assign dt_48 = dt_48_reg;
  // register end

  // register begin
  reg [4:0] dt_49_reg = 5'd0;
  always @(posedge \$d(%,%) [1:1] or posedge \$d(%,%) [0:0]) begin : dt_49_register
    if (\$d(%,%) [0:0]) begin
      dt_49_reg <= 5'd0;
    end else begin
      dt_49_reg <= result_92;
    end
  end
  assign dt_49 = dt_49_reg;
  // register end

  assign dt_50 = c_xcoord_1;

  // register begin
  reg [4:0] dt_51_reg = 5'd0;
  always @(posedge \$d(%,%) [1:1] or posedge \$d(%,%) [0:0]) begin : dt_51_register
    if (\$d(%,%) [0:0]) begin
      dt_51_reg <= 5'd0;
    end else begin
      dt_51_reg <= result_93;
    end
  end
  assign dt_51 = dt_51_reg;
  // register end

  assign dt_52 = c_ycoord_1;

  assign dt_53 = c_xcoord_1 + 5'd1;

  assign dt_54 = c_ycoord_1 + 5'd1;

  // register begin
  reg [4:0] c_xcoord_1_reg = 5'd0;
  always @(posedge \$d(%,%) [1:1] or posedge \$d(%,%) [0:0]) begin : c_xcoord_1_register
    if (\$d(%,%) [0:0]) begin
      c_xcoord_1_reg <= 5'd0;
    end else begin
      c_xcoord_1_reg <= result_94;
    end
  end
  assign c_xcoord_1 = c_xcoord_1_reg;
  // register end

  // register begin
  reg [4:0] c_ycoord_1_reg = 5'd0;
  always @(posedge \$d(%,%) [1:1] or posedge \$d(%,%) [0:0]) begin : c_ycoord_1_register
    if (\$d(%,%) [0:0]) begin
      c_ycoord_1_reg <= 5'd0;
    end else begin
      c_ycoord_1_reg <= result_95;
    end
  end
  assign c_ycoord_1 = c_ycoord_1_reg;
  // register end

  assign result_96 = {((~ c$cout_app_arg_18)),({(c$cout_app_arg_18),({1'b0,({1'b1,({1'b1,({1'b0,({1'b1,({1'b0,({(c$cout_app_arg_19),({(w9_0),({((c$w9_app_arg & (~ w9_0))),1'b0})})})})})})})})})})};

  assign dt_55 = score_color;

  assign c$cout_app_arg_18 = cin_6[(64'sd1)];

  assign cin_6 = {c$cin_app_arg_9,({result_97,({result_98,({result_100,result_99})})})};

  always @(*) begin
    if(gameover)
      c$cin_app_arg_9 = 1'b1;
    else
      c$cin_app_arg_9 = 1'b0;
  end

  always @(*) begin
    if(b_11)
      result_97 = 1'b1;
    else
      result_97 = 1'b0;
  end

  always @(*) begin
    if(b_12)
      result_98 = 1'b1;
    else
      result_98 = 1'b0;
  end

  assign b_11 = (({{(10-5) {1'b0}},c_xcoord_1}) + (10'd32 * ({{(10-5) {1'b0}},c_ycoord_1}))) < score;

  always @(*) begin
    if(b_13)
      result_99 = 1'b1;
    else
      result_99 = 1'b0;
  end

  always @(*) begin
    if(b_14)
      result_100 = 1'b1;
    else
      result_100 = 1'b0;
  end

  assign b_12 = c_xcoord_1 == c_ycoord_1;

  assign b_13 = (c_xcoord_1 + c_ycoord_1) == 5'd31;

  assign b_14 = c_xcoord_1 == 5'd31;

  assign c$cout_app_arg_19 = cin_6[(64'sd3)];

  assign w9_0 = ((~ ((~ (cin_6[(64'sd0)])) & (~ (cin_6[(64'sd2)])))) & c$w9_app_arg) & (cin_6[(64'sd4)]);

  assign c$w9_app_arg = ~ c$cout_app_arg_19;

  assign score_color = result_42[2:0];

  assign score = result_42[89:80];

  assign gameover = result_42[79:79];

  assign gamemode = result_126[11:10];

  assign result_101_selection_res = (result_102[(64'sd0)]) == (1'b1);

  always @(*) begin
    if(result_101_selection_res)
      result_101 = c$o_outpoint_case_alt;
    else
      result_101 = c$o_outpoint_case_alt_0;
  end

  assign c$vecflat_107 = {result_43
                         ,{dt_56,{result_62,dt_57}}};

  // index begin
  wire [12:0] vec_110 [0:4-1];

  genvar i_112;
  generate
  for (i_112=0; i_112 < 4; i_112=i_112+1) begin : mk_array_110
    assign vec_110[(4-1)-i_112] = c$vecflat_107[i_112*13+:13];
  end
  endgenerate

  assign c$o_outpoint_case_alt = vec_110[(64'sd3)];
  // index end

  assign c$o_outpoint_case_alt_0_selection_res = (result_102[(64'sd1)]) == (1'b1);

  always @(*) begin
    if(c$o_outpoint_case_alt_0_selection_res)
      c$o_outpoint_case_alt_0 = c$o_outpoint_case_alt_1;
    else
      c$o_outpoint_case_alt_0 = c$o_outpoint_case_alt_2;
  end

  assign c$vecflat_108 = {result_43
                         ,{dt_56,{result_62,dt_57}}};

  // index begin
  wire [12:0] vec_111 [0:4-1];

  genvar i_113;
  generate
  for (i_113=0; i_113 < 4; i_113=i_113+1) begin : mk_array_111
    assign vec_111[(4-1)-i_113] = c$vecflat_108[i_113*13+:13];
  end
  endgenerate

  assign c$o_outpoint_case_alt_1 = vec_111[(64'sd2)];
  // index end

  assign c$o_outpoint_case_alt_2_selection_res = (result_102[(64'sd2)]) == (1'b1);

  always @(*) begin
    if(c$o_outpoint_case_alt_2_selection_res)
      c$o_outpoint_case_alt_2 = c$o_outpoint_case_alt_3;
    else
      c$o_outpoint_case_alt_2 = c$o_outpoint_case_alt_4;
  end

  assign c$vecflat_109 = {result_43
                         ,{dt_56,{result_62,dt_57}}};

  // index begin
  wire [12:0] vec_112 [0:4-1];

  genvar i_114;
  generate
  for (i_114=0; i_114 < 4; i_114=i_114+1) begin : mk_array_112
    assign vec_112[(4-1)-i_114] = c$vecflat_109[i_114*13+:13];
  end
  endgenerate

  assign c$o_outpoint_case_alt_3 = vec_112[(64'sd1)];
  // index end

  assign c$vecflat_110 = {result_43
                         ,{dt_56,{result_62,dt_57}}};

  // index begin
  wire [12:0] vec_113 [0:4-1];

  genvar i_115;
  generate
  for (i_115=0; i_115 < 4; i_115=i_115+1) begin : mk_array_113
    assign vec_113[(4-1)-i_115] = c$vecflat_110[i_115*13+:13];
  end
  endgenerate

  assign c$o_outpoint_case_alt_4 = vec_113[(64'sd0)];
  // index end

  assign result_102 = {((result_103[(64'sd0)])),({((result_103[(64'sd1)])),({((result_103[(64'sd2)])),((result_103[(64'sd3)]))})})};

  // register begin
  reg [12:0] dt_56_reg = {5'd0,5'd0,3'b000};
  always @(posedge \$d(%,%) [1:1] or posedge \$d(%,%) [0:0]) begin : dt_56_register
    if (\$d(%,%) [0:0]) begin
      dt_56_reg <= {5'd0,5'd0,3'b000};
    end else begin
      dt_56_reg <= result_101;
    end
  end
  assign dt_56 = dt_56_reg;
  // register end

  assign dt_57 = result_89;

  assign result_103 = {((~ w5)),({(w6),({1'b0,((w5 & (~ w6)))})})};

  assign w5 = (~ (cin_7[(64'sd3)])) & (~ (cin_7[(64'sd2)]));

  assign w6 = w5 & (cin_7[(64'sd1)]);

  assign cin_7 = {c$cin_app_arg_10,({result_104,({result_106,result_105})})};

  always @(*) begin
    if(gameover)
      c$cin_app_arg_10 = 1'b1;
    else
      c$cin_app_arg_10 = 1'b0;
  end

  always @(*) begin
    if(b_15)
      result_104 = 1'b1;
    else
      result_104 = 1'b0;
  end

  always @(*) begin
    if(b_16)
      result_105 = 1'b1;
    else
      result_105 = 1'b0;
  end

  always @(*) begin
    if(b_17)
      result_106 = 1'b1;
    else
      result_106 = 1'b0;
  end

  always @(*) begin
    case(gamemode)
      2'b00 : b_15 = 1'b1;
      default : b_15 = 1'b0;
    endcase
  end

  always @(*) begin
    case(gamemode)
      2'b10 : b_16 = 1'b1;
      default : b_16 = 1'b0;
    endcase
  end

  always @(*) begin
    case(gamemode)
      2'b01 : b_17 = 1'b1;
      default : b_17 = 1'b0;
    endcase
  end

  assign result_107_selection_res = initalCounter == 27'd67108864;

  always @(*) begin
    if(result_107_selection_res)
      result_107 = 1'b1;
    else
      result_107 = 1'b0;
  end

  assign result_108 = {result_109[50:48]
                      ,result_109[31:31]
                      ,result_109[47:45]
                      ,result_109[44:42]
                      ,result_109[36:33]
                      ,result_109[51:51]
                      ,result_109[32:32]};

  assign result_109 = {result_110
                      ,result_111
                      ,result_112
                      ,result_113
                      ,result_119
                      ,result_116
                      ,result_118
                      ,result_117
                      ,result_115
                      ,result_114
                      ,result_120};

  assign result_110_selection_res = (bs_44[(64'sd0)]) == (1'b1);

  always @(*) begin
    if(result_110_selection_res)
      result_110 = c$o_bufferPin_case_alt;
    else
      result_110 = c$o_bufferPin_case_alt_0;
  end

  assign result_111_selection_res = (bs_45[(64'sd0)]) == (1'b1);

  always @(*) begin
    if(result_111_selection_res)
      result_111 = c$o_color_case_alt_15;
    else
      result_111 = c$o_color_case_alt_16;
  end

  assign result_112_selection_res = (bs_46[(64'sd0)]) == (1'b1);

  always @(*) begin
    if(result_112_selection_res)
      result_112 = c$o_color1_case_alt;
    else
      result_112 = c$o_color1_case_alt_0;
  end

  assign result_113_selection_res = (bs_47[(64'sd0)]) == (1'b1);

  always @(*) begin
    if(result_113_selection_res)
      result_113 = c$o_color2_case_alt;
    else
      result_113 = c$o_color2_case_alt_0;
  end

  assign result_114_selection_res = (bs_48[(64'sd0)]) == (1'b1);

  always @(*) begin
    if(result_114_selection_res)
      result_114 = c$o_ramwrite_case_alt;
    else
      result_114 = c$o_ramwrite_case_alt_0;
  end

  assign result_115_selection_res = (bs_49[(64'sd0)]) == (1'b1);

  always @(*) begin
    if(result_115_selection_res)
      result_115 = c$o_rampos_case_alt;
    else
      result_115 = c$o_rampos_case_alt_0;
  end

  assign result_116_selection_res = (bs_50[(64'sd0)]) == (1'b1);

  always @(*) begin
    if(result_116_selection_res)
      result_116 = \c$_INTERNAL_.o_coordy_case_alt ;
    else
      result_116 = \c$_INTERNAL_.o_coordy_case_alt_0 ;
  end

  assign result_117_selection_res = (bs_51[(64'sd0)]) == (1'b1);

  always @(*) begin
    if(result_117_selection_res)
      result_117 = c$o_extclock_case_alt;
    else
      result_117 = c$o_extclock_case_alt_0;
  end

  assign result_118_selection_res = (bs_52[(64'sd0)]) == (1'b1);

  always @(*) begin
    if(result_118_selection_res)
      result_118 = c$o_driverPin_case_alt;
    else
      result_118 = c$o_driverPin_case_alt_0;
  end

  assign result_119_selection_res = (bs_53[(64'sd0)]) == (1'b1);

  always @(*) begin
    if(result_119_selection_res)
      result_119 = \c$_INTERNAL_.o_coordx_case_alt ;
    else
      result_119 = \c$_INTERNAL_.o_coordx_case_alt_0 ;
  end

  assign result_120_selection_res = (bs_54[(64'sd0)]) == (1'b1);

  always @(*) begin
    if(result_120_selection_res)
      result_120 = \c$_INTERNAL_.o_waitcounter_case_alt ;
    else
      result_120 = \c$_INTERNAL_.o_waitcounter_case_alt_0 ;
  end

  assign c$vecflat_111 = {dt_58,1'b1,1'b0};

  // index begin
  wire  vec_114 [0:3-1];

  genvar i_116;
  generate
  for (i_116=0; i_116 < 3; i_116=i_116+1) begin : mk_array_114
    assign vec_114[(3-1)-i_116] = c$vecflat_111[i_116*1+:1];
  end
  endgenerate

  assign c$o_bufferPin_case_alt = vec_114[(64'sd2)];
  // index end

  assign c$o_bufferPin_case_alt_0_selection_res = (bs_44[(64'sd1)]) == (1'b1);

  always @(*) begin
    if(c$o_bufferPin_case_alt_0_selection_res)
      c$o_bufferPin_case_alt_0 = c$o_bufferPin_case_alt_1;
    else
      c$o_bufferPin_case_alt_0 = c$o_bufferPin_case_alt_2;
  end

  assign c$vecflat_112 = {dt_59,dt_60};

  // index begin
  wire [2:0] vec_115 [0:2-1];

  genvar i_117;
  generate
  for (i_117=0; i_117 < 2; i_117=i_117+1) begin : mk_array_115
    assign vec_115[(2-1)-i_117] = c$vecflat_112[i_117*3+:3];
  end
  endgenerate

  assign c$o_color_case_alt_15 = vec_115[(64'sd1)];
  // index end

  assign c$vecflat_113 = {dt_59,dt_60};

  // index begin
  wire [2:0] vec_116 [0:2-1];

  genvar i_118;
  generate
  for (i_118=0; i_118 < 2; i_118=i_118+1) begin : mk_array_116
    assign vec_116[(2-1)-i_118] = c$vecflat_113[i_118*3+:3];
  end
  endgenerate

  assign c$o_color_case_alt_16 = vec_116[(64'sd0)];
  // index end

  assign c$vecflat_114 = {dt_61,dt_60};

  // index begin
  wire [2:0] vec_117 [0:2-1];

  genvar i_119;
  generate
  for (i_119=0; i_119 < 2; i_119=i_119+1) begin : mk_array_117
    assign vec_117[(2-1)-i_119] = c$vecflat_114[i_119*3+:3];
  end
  endgenerate

  assign c$o_color1_case_alt = vec_117[(64'sd1)];
  // index end

  assign c$vecflat_115 = {dt_61,dt_60};

  // index begin
  wire [2:0] vec_118 [0:2-1];

  genvar i_120;
  generate
  for (i_120=0; i_120 < 2; i_120=i_120+1) begin : mk_array_118
    assign vec_118[(2-1)-i_120] = c$vecflat_115[i_120*3+:3];
  end
  endgenerate

  assign c$o_color1_case_alt_0 = vec_118[(64'sd0)];
  // index end

  assign c$vecflat_116 = {dt_62,dt_60};

  // index begin
  wire [2:0] vec_119 [0:2-1];

  genvar i_121;
  generate
  for (i_121=0; i_121 < 2; i_121=i_121+1) begin : mk_array_119
    assign vec_119[(2-1)-i_121] = c$vecflat_116[i_121*3+:3];
  end
  endgenerate

  assign c$o_color2_case_alt = vec_119[(64'sd1)];
  // index end

  assign c$vecflat_117 = {dt_62,dt_60};

  // index begin
  wire [2:0] vec_120 [0:2-1];

  genvar i_122;
  generate
  for (i_122=0; i_122 < 2; i_122=i_122+1) begin : mk_array_120
    assign vec_120[(2-1)-i_122] = c$vecflat_117[i_122*3+:3];
  end
  endgenerate

  assign c$o_color2_case_alt_0 = vec_120[(64'sd0)];
  // index end

  assign c$vecflat_118 = {dt_63
                         ,{1'b0,13'bxxxxxxxxxxxxx}
                         ,dt_71};

  // index begin
  wire [13:0] vec_121 [0:3-1];

  genvar i_123;
  generate
  for (i_123=0; i_123 < 3; i_123=i_123+1) begin : mk_array_121
    assign vec_121[(3-1)-i_123] = c$vecflat_118[i_123*14+:14];
  end
  endgenerate

  assign c$o_ramwrite_case_alt = vec_121[(64'sd2)];
  // index end

  assign c$o_ramwrite_case_alt_0_selection_res = (bs_48[(64'sd1)]) == (1'b1);

  always @(*) begin
    if(c$o_ramwrite_case_alt_0_selection_res)
      c$o_ramwrite_case_alt_0 = c$o_ramwrite_case_alt_1;
    else
      c$o_ramwrite_case_alt_0 = c$o_ramwrite_case_alt_2;
  end

  assign c$vecflat_119 = {dt_64
                         ,dt_68
                         ,dt_72
                         ,dt_73};

  // index begin
  wire [9:0] vec_122 [0:4-1];

  genvar i_124;
  generate
  for (i_124=0; i_124 < 4; i_124=i_124+1) begin : mk_array_122
    assign vec_122[(4-1)-i_124] = c$vecflat_119[i_124*10+:10];
  end
  endgenerate

  assign c$o_rampos_case_alt = vec_122[(64'sd3)];
  // index end

  assign c$o_rampos_case_alt_0_selection_res = (bs_49[(64'sd1)]) == (1'b1);

  always @(*) begin
    if(c$o_rampos_case_alt_0_selection_res)
      c$o_rampos_case_alt_0 = c$o_rampos_case_alt_1;
    else
      c$o_rampos_case_alt_0 = c$o_rampos_case_alt_2;
  end

  assign c$vecflat_120 = {c_coordy,dt_65};

  // index begin
  wire [3:0] vec_123 [0:2-1];

  genvar i_125;
  generate
  for (i_125=0; i_125 < 2; i_125=i_125+1) begin : mk_array_123
    assign vec_123[(2-1)-i_125] = c$vecflat_120[i_125*4+:4];
  end
  endgenerate

  assign \c$_INTERNAL_.o_coordy_case_alt  = vec_123[(64'sd1)];
  // index end

  assign c$vecflat_121 = {c_coordy,dt_65};

  // index begin
  wire [3:0] vec_124 [0:2-1];

  genvar i_126;
  generate
  for (i_126=0; i_126 < 2; i_126=i_126+1) begin : mk_array_124
    assign vec_124[(2-1)-i_126] = c$vecflat_121[i_126*4+:4];
  end
  endgenerate

  assign \c$_INTERNAL_.o_coordy_case_alt_0  = vec_124[(64'sd0)];
  // index end

  assign c$vecflat_122 = {dt_66,1'b1,1'b0};

  // index begin
  wire  vec_125 [0:3-1];

  genvar i_127;
  generate
  for (i_127=0; i_127 < 3; i_127=i_127+1) begin : mk_array_125
    assign vec_125[(3-1)-i_127] = c$vecflat_122[i_127*1+:1];
  end
  endgenerate

  assign c$o_extclock_case_alt = vec_125[(64'sd2)];
  // index end

  assign c$o_extclock_case_alt_0_selection_res = (bs_51[(64'sd1)]) == (1'b1);

  always @(*) begin
    if(c$o_extclock_case_alt_0_selection_res)
      c$o_extclock_case_alt_0 = c$o_extclock_case_alt_1;
    else
      c$o_extclock_case_alt_0 = c$o_extclock_case_alt_2;
  end

  assign c$vecflat_123 = {dt_67,1'b0};

  // index begin
  wire  vec_126 [0:2-1];

  genvar i_128;
  generate
  for (i_128=0; i_128 < 2; i_128=i_128+1) begin : mk_array_126
    assign vec_126[(2-1)-i_128] = c$vecflat_123[i_128*1+:1];
  end
  endgenerate

  assign c$o_driverPin_case_alt = vec_126[(64'sd1)];
  // index end

  assign c$vecflat_124 = {dt_67,1'b0};

  // index begin
  wire  vec_127 [0:2-1];

  genvar i_129;
  generate
  for (i_129=0; i_129 < 2; i_129=i_129+1) begin : mk_array_127
    assign vec_127[(2-1)-i_129] = c$vecflat_124[i_129*1+:1];
  end
  endgenerate

  assign c$o_driverPin_case_alt_0 = vec_127[(64'sd0)];
  // index end

  assign c$vecflat_125 = {c_coordx,dt_69};

  // index begin
  wire [4:0] vec_128 [0:2-1];

  genvar i_130;
  generate
  for (i_130=0; i_130 < 2; i_130=i_130+1) begin : mk_array_128
    assign vec_128[(2-1)-i_130] = c$vecflat_125[i_130*5+:5];
  end
  endgenerate

  assign \c$_INTERNAL_.o_coordx_case_alt  = vec_128[(64'sd1)];
  // index end

  assign c$vecflat_126 = {c_coordx,dt_69};

  // index begin
  wire [4:0] vec_129 [0:2-1];

  genvar i_131;
  generate
  for (i_131=0; i_131 < 2; i_131=i_131+1) begin : mk_array_129
    assign vec_129[(2-1)-i_131] = c$vecflat_126[i_131*5+:5];
  end
  endgenerate

  assign \c$_INTERNAL_.o_coordx_case_alt_0  = vec_129[(64'sd0)];
  // index end

  assign c$vecflat_127 = {c_waitcounter,dt_70};

  // index begin
  wire [6:0] vec_130 [0:2-1];

  genvar i_132;
  generate
  for (i_132=0; i_132 < 2; i_132=i_132+1) begin : mk_array_130
    assign vec_130[(2-1)-i_132] = c$vecflat_127[i_132*7+:7];
  end
  endgenerate

  assign \c$_INTERNAL_.o_waitcounter_case_alt  = vec_130[(64'sd1)];
  // index end

  assign c$vecflat_128 = {c_waitcounter,dt_70};

  // index begin
  wire [6:0] vec_131 [0:2-1];

  genvar i_133;
  generate
  for (i_133=0; i_133 < 2; i_133=i_133+1) begin : mk_array_131
    assign vec_131[(2-1)-i_133] = c$vecflat_128[i_133*7+:7];
  end
  endgenerate

  assign \c$_INTERNAL_.o_waitcounter_case_alt_0  = vec_131[(64'sd0)];
  // index end

  assign c$vecflat_129 = {dt_58,1'b1,1'b0};

  // index begin
  wire  vec_132 [0:3-1];

  genvar i_134;
  generate
  for (i_134=0; i_134 < 3; i_134=i_134+1) begin : mk_array_132
    assign vec_132[(3-1)-i_134] = c$vecflat_129[i_134*1+:1];
  end
  endgenerate

  assign c$o_bufferPin_case_alt_1 = vec_132[(64'sd1)];
  // index end

  assign c$vecflat_130 = {dt_58,1'b1,1'b0};

  // index begin
  wire  vec_133 [0:3-1];

  genvar i_135;
  generate
  for (i_135=0; i_135 < 3; i_135=i_135+1) begin : mk_array_133
    assign vec_133[(3-1)-i_135] = c$vecflat_130[i_135*1+:1];
  end
  endgenerate

  assign c$o_bufferPin_case_alt_2 = vec_133[(64'sd0)];
  // index end

  assign c$vecflat_131 = {dt_63
                         ,{1'b0,13'bxxxxxxxxxxxxx}
                         ,dt_71};

  // index begin
  wire [13:0] vec_134 [0:3-1];

  genvar i_136;
  generate
  for (i_136=0; i_136 < 3; i_136=i_136+1) begin : mk_array_134
    assign vec_134[(3-1)-i_136] = c$vecflat_131[i_136*14+:14];
  end
  endgenerate

  assign c$o_ramwrite_case_alt_1 = vec_134[(64'sd1)];
  // index end

  assign c$vecflat_132 = {dt_63
                         ,{1'b0,13'bxxxxxxxxxxxxx}
                         ,dt_71};

  // index begin
  wire [13:0] vec_135 [0:3-1];

  genvar i_137;
  generate
  for (i_137=0; i_137 < 3; i_137=i_137+1) begin : mk_array_135
    assign vec_135[(3-1)-i_137] = c$vecflat_132[i_137*14+:14];
  end
  endgenerate

  assign c$o_ramwrite_case_alt_2 = vec_135[(64'sd0)];
  // index end

  assign c$vecflat_133 = {dt_64
                         ,dt_68
                         ,dt_72
                         ,dt_73};

  // index begin
  wire [9:0] vec_136 [0:4-1];

  genvar i_138;
  generate
  for (i_138=0; i_138 < 4; i_138=i_138+1) begin : mk_array_136
    assign vec_136[(4-1)-i_138] = c$vecflat_133[i_138*10+:10];
  end
  endgenerate

  assign c$o_rampos_case_alt_1 = vec_136[(64'sd2)];
  // index end

  assign c$o_rampos_case_alt_2_selection_res = (bs_49[(64'sd2)]) == (1'b1);

  always @(*) begin
    if(c$o_rampos_case_alt_2_selection_res)
      c$o_rampos_case_alt_2 = c$o_rampos_case_alt_3;
    else
      c$o_rampos_case_alt_2 = c$o_rampos_case_alt_4;
  end

  assign c$vecflat_134 = {dt_66,1'b1,1'b0};

  // index begin
  wire  vec_137 [0:3-1];

  genvar i_139;
  generate
  for (i_139=0; i_139 < 3; i_139=i_139+1) begin : mk_array_137
    assign vec_137[(3-1)-i_139] = c$vecflat_134[i_139*1+:1];
  end
  endgenerate

  assign c$o_extclock_case_alt_1 = vec_137[(64'sd1)];
  // index end

  assign c$vecflat_135 = {dt_66,1'b1,1'b0};

  // index begin
  wire  vec_138 [0:3-1];

  genvar i_140;
  generate
  for (i_140=0; i_140 < 3; i_140=i_140+1) begin : mk_array_138
    assign vec_138[(3-1)-i_140] = c$vecflat_135[i_140*1+:1];
  end
  endgenerate

  assign c$o_extclock_case_alt_2 = vec_138[(64'sd0)];
  // index end

  assign bs_44 = {((result_121[(64'sd0)])),({((result_121[(64'sd1)])),((result_121[(64'sd2)]))})};

  assign bs_45 = {((result_121[(64'sd3)])),((result_121[(64'sd4)]))};

  assign bs_46 = {((result_121[(64'sd5)])),((result_121[(64'sd6)]))};

  assign bs_47 = {((result_121[(64'sd7)])),((result_121[(64'sd8)]))};

  assign bs_48 = {((result_121[(64'sd22)])),({((result_121[(64'sd23)])),((result_121[(64'sd24)]))})};

  assign bs_49 = {((result_121[(64'sd18)])),({((result_121[(64'sd19)])),({((result_121[(64'sd20)])),((result_121[(64'sd21)]))})})};

  assign c$vecflat_136 = {dt_64
                         ,dt_68
                         ,dt_72
                         ,dt_73};

  // index begin
  wire [9:0] vec_139 [0:4-1];

  genvar i_141;
  generate
  for (i_141=0; i_141 < 4; i_141=i_141+1) begin : mk_array_139
    assign vec_139[(4-1)-i_141] = c$vecflat_136[i_141*10+:10];
  end
  endgenerate

  assign c$o_rampos_case_alt_3 = vec_139[(64'sd1)];
  // index end

  assign c$vecflat_137 = {dt_64
                         ,dt_68
                         ,dt_72
                         ,dt_73};

  // index begin
  wire [9:0] vec_140 [0:4-1];

  genvar i_142;
  generate
  for (i_142=0; i_142 < 4; i_142=i_142+1) begin : mk_array_140
    assign vec_140[(4-1)-i_142] = c$vecflat_137[i_142*10+:10];
  end
  endgenerate

  assign c$o_rampos_case_alt_4 = vec_140[(64'sd0)];
  // index end

  assign bs_50 = {((result_121[(64'sd11)])),((result_121[(64'sd12)]))};

  assign bs_51 = {((result_121[(64'sd15)])),({((result_121[(64'sd16)])),((result_121[(64'sd17)]))})};

  assign bs_52 = {((result_121[(64'sd13)])),((result_121[(64'sd14)]))};

  assign bs_53 = {((result_121[(64'sd9)])),((result_121[(64'sd10)]))};

  assign bs_54 = {((result_121[(64'sd25)])),((result_121[(64'sd26)]))};

  // register begin
  reg [4:0] c_coordx_reg = 5'd31;
  always @(posedge \$d(%,%)1 [1:1] or posedge \$d(%,%)1 [0:0]) begin : c_coordx_register
    if (\$d(%,%)1 [0:0]) begin
      c_coordx_reg <= 5'd31;
    end else begin
      c_coordx_reg <= result_119;
    end
  end
  assign c_coordx = c_coordx_reg;
  // register end

  // register begin
  reg [6:0] c_waitcounter_reg = 7'd0;
  always @(posedge \$d(%,%)1 [1:1] or posedge \$d(%,%)1 [0:0]) begin : c_waitcounter_register
    if (\$d(%,%)1 [0:0]) begin
      c_waitcounter_reg <= 7'd0;
    end else begin
      c_waitcounter_reg <= result_120;
    end
  end
  assign c_waitcounter = c_waitcounter_reg;
  // register end

  // register begin
  reg [3:0] c_coordy_reg = 4'd0;
  always @(posedge \$d(%,%)1 [1:1] or posedge \$d(%,%)1 [0:0]) begin : c_coordy_register
    if (\$d(%,%)1 [0:0]) begin
      c_coordy_reg <= 4'd0;
    end else begin
      c_coordy_reg <= result_116;
    end
  end
  assign c_coordy = c_coordy_reg;
  // register end

  // register begin
  reg  dt_58_reg = (1'b1);
  always @(posedge \$d(%,%)1 [1:1] or posedge \$d(%,%)1 [0:0]) begin : dt_58_register
    if (\$d(%,%)1 [0:0]) begin
      dt_58_reg <= (1'b1);
    end else begin
      dt_58_reg <= result_110;
    end
  end
  assign dt_58 = dt_58_reg;
  // register end

  // register begin
  reg [2:0] dt_59_reg = 3'b000;
  always @(posedge \$d(%,%)1 [1:1] or posedge \$d(%,%)1 [0:0]) begin : dt_59_register
    if (\$d(%,%)1 [0:0]) begin
      dt_59_reg <= 3'b000;
    end else begin
      dt_59_reg <= result_111;
    end
  end
  assign dt_59 = dt_59_reg;
  // register end

  assign dt_60 = result_125;

  // register begin
  reg [2:0] dt_61_reg = 3'b000;
  always @(posedge \$d(%,%)1 [1:1] or posedge \$d(%,%)1 [0:0]) begin : dt_61_register
    if (\$d(%,%)1 [0:0]) begin
      dt_61_reg <= 3'b000;
    end else begin
      dt_61_reg <= result_112;
    end
  end
  assign dt_61 = dt_61_reg;
  // register end

  // register begin
  reg [2:0] dt_62_reg = 3'b000;
  always @(posedge \$d(%,%)1 [1:1] or posedge \$d(%,%)1 [0:0]) begin : dt_62_register
    if (\$d(%,%)1 [0:0]) begin
      dt_62_reg <= 3'b000;
    end else begin
      dt_62_reg <= result_113;
    end
  end
  assign dt_62 = dt_62_reg;
  // register end

  // register begin
  reg [13:0] dt_63_reg = {1'b0,13'bxxxxxxxxxxxxx};
  always @(posedge \$d(%,%)1 [1:1] or posedge \$d(%,%)1 [0:0]) begin : dt_63_register
    if (\$d(%,%)1 [0:0]) begin
      dt_63_reg <= {1'b0,13'bxxxxxxxxxxxxx};
    end else begin
      dt_63_reg <= result_114;
    end
  end
  assign dt_63 = dt_63_reg;
  // register end

  // register begin
  reg [9:0] dt_64_reg = 10'd0;
  always @(posedge \$d(%,%)1 [1:1] or posedge \$d(%,%)1 [0:0]) begin : dt_64_register
    if (\$d(%,%)1 [0:0]) begin
      dt_64_reg <= 10'd0;
    end else begin
      dt_64_reg <= result_115;
    end
  end
  assign dt_64 = dt_64_reg;
  // register end

  assign dt_65 = w23;

  // register begin
  reg  dt_66_reg = (1'b0);
  always @(posedge \$d(%,%)1 [1:1] or posedge \$d(%,%)1 [0:0]) begin : dt_66_register
    if (\$d(%,%)1 [0:0]) begin
      dt_66_reg <= (1'b0);
    end else begin
      dt_66_reg <= result_117;
    end
  end
  assign dt_66 = dt_66_reg;
  // register end

  // register begin
  reg  dt_67_reg = (1'b1);
  always @(posedge \$d(%,%)1 [1:1] or posedge \$d(%,%)1 [0:0]) begin : dt_67_register
    if (\$d(%,%)1 [0:0]) begin
      dt_67_reg <= (1'b1);
    end else begin
      dt_67_reg <= result_118;
    end
  end
  assign dt_67 = dt_67_reg;
  // register end

  assign w23 = c_coordy + 4'd1;

  assign dt_68 = c$dt_app_arg_3 + (c$dt_app_arg_4 * 10'd32);

  assign dt_69 = c_coordx + 5'd1;

  assign dt_70 = c_waitcounter + 7'd1;

  assign c$dt_app_arg_3 = {{(10-5) {1'b0}},c_coordx};

  assign result_121 = {(((~ w129) & c$cout_app_arg_20)),({(w129),({((c$cout_app_arg_20 & c$cout_app_arg_21)),({((c$cout_app_arg_20 & (~ c$cout_app_arg_21))),({1'b0,({((~ ((~ (((~ w73) & (~ w26_0)) & \_INTERNAL_.w123 )) & c$cout_app_arg_22))),({c$cout_app_arg_25,({((c$cout_app_arg_23 & c$w101_app_arg)),({((~ ((~ (((~ (w116 & c$w50_app_arg)) & c$w53_app_arg) & w78)) & (~ ((~ ((~ ((~ (w68 & w48)) & w26_0)) & w85)) & c$w94_app_arg))))),({(w107),({((c$cout_app_arg_23 & w52)),({((~ w102)),({(c$cout_app_arg_20),({1'b0,({((c$cout_app_arg_24 & c$w53_app_arg)),({((~ ((~ w94) & (~ w93)))),({(c$cout_app_arg_24),({(w93),({((\c$_INTERNAL_.w7_app_arg_0  & (~ w81))),({(w81),({c$cout_app_arg_25,({(w78),({(w65),({(w66),({((c$cout_app_arg_20 & w58)),({((~ w58)),1'b0})})})})})})})})})})})})})})})})})})})})})})})})})};

  assign dt_71 = {1'b1,{dt_73,result_101[2:0]}};

  assign dt_72 = c$dt_app_arg_3 + ((10'd16 + c$dt_app_arg_4) * 10'd32);

  assign c$dt_app_arg_4 = {{(10-4) {1'b0}},w23};

  assign c$bv_7 = result_101[12:8];

  assign c$bv_8 = result_101[7:3];

  assign dt_73 = ({{(10-5) {1'b0}},result_101[12:8]}) + (({{(10-5) {1'b0}},result_101[7:3]}) * 10'd32);

  assign w129 = (~ w106) & c$w129_app_arg;

  assign c$cout_app_arg_20 = ~ \_INTERNAL_.w62 ;

  assign \_INTERNAL_.w62  = \_INTERNAL_.w61  & \c$_INTERNAL_.w6_0 ;

  assign c$w129_app_arg = cin_8[(64'sd0)];

  assign cin_8 = {result_122,({result_124,result_123})};

  assign w106 = w104 & w102;

  assign \_INTERNAL_.w61  = (~ (\c$_INTERNAL_.w61_app_arg_0  & \c$_INTERNAL_.w61_app_arg )) & w50;

  // register begin
  reg  c$_INTERNAL_w6_0_reg = (1'b0);
  always @(posedge \$d(%,%)1 [1:1] or posedge \$d(%,%)1 [0:0]) begin : c$_INTERNAL_w6_0_register
    if (\$d(%,%)1 [0:0]) begin
      c$_INTERNAL_w6_0_reg <= (1'b0);
    end else begin
      c$_INTERNAL_w6_0_reg <= ((~ ((\c$_INTERNAL_.w6_app_arg_0  & c$w94_app_arg) & (~ w116))) & (~ ((~ ((~ (w97 & w66)) & w101)) & w53)));
    end
  end
  assign \c$_INTERNAL_.w6_0  = c$_INTERNAL_w6_0_reg;
  // register end

  assign c$cout_app_arg_21 = cin_8[(64'sd1)];

  assign w50 = (~ (c$w50_app_arg & \_INTERNAL_.w8 )) & \c$_INTERNAL_.w7_0 ;

  assign w104 = (~ (w39 & \_INTERNAL_.w14 )) & c$w104_app_arg;

  assign w102 = (~ w101) & (~ w90);

  always @(*) begin
    if(b_18)
      result_122 = 1'b1;
    else
      result_122 = 1'b0;
  end

  // register begin
  reg  c$_INTERNAL_w7_0_reg = (1'b0);
  always @(posedge \$d(%,%)1 [1:1] or posedge \$d(%,%)1 [0:0]) begin : c$_INTERNAL_w7_0_register
    if (\$d(%,%)1 [0:0]) begin
      c$_INTERNAL_w7_0_reg <= (1'b0);
    end else begin
      c$_INTERNAL_w7_0_reg <= (~ ((~ ((~ ((~ ((~ ((~ w79) & c$w77_app_arg)) & c$w101_app_arg_0)) & w33_0)) & c$w94_app_arg)) & (~ (\c$_INTERNAL_.w7_app_arg_0  & c$w53_app_arg))));
    end
  end
  assign \c$_INTERNAL_.w7_0  = c$_INTERNAL_w7_0_reg;
  // register end

  assign c$w104_app_arg = ~ \_INTERNAL_.w28 ;

  always @(*) begin
    if(b_19)
      result_123 = 1'b1;
    else
      result_123 = 1'b0;
  end

  always @(*) begin
    if(b_20)
      result_124 = 1'b1;
    else
      result_124 = 1'b0;
  end

  assign b_18 = c_coordx == 5'd31;

  assign w101 = (~ (c$w101_app_arg_0 & (~ \_INTERNAL_.w87 ))) & c$w101_app_arg;

  assign \_INTERNAL_.w28  = \_INTERNAL_.w24  & \c$_INTERNAL_.w61_app_arg ;

  assign w90 = ((~ (\_INTERNAL_.w87  & \_INTERNAL_.w8 )) & \c$_INTERNAL_.w7_0 ) & \_INTERNAL_.w31 ;

  assign \c$_INTERNAL_.w61_app_arg  = ~ \_INTERNAL_.w8 ;

  assign \c$_INTERNAL_.w61_app_arg_0  = ~ \_INTERNAL_.w59 ;

  assign b_19 = c_waitcounter == 7'd0;

  assign b_20 = result_107 == (1'b1);

  assign w39 = \c$_INTERNAL_.w59_app_arg  & \_INTERNAL_.w8 ;

  assign \_INTERNAL_.w31  = (~ (\_INTERNAL_.w29  & \c$_INTERNAL_.w31_app_arg )) & c$w104_app_arg;

  // register begin
  reg  _INTERNAL_w8_reg = (1'b0);
  always @(posedge \$d(%,%)1 [1:1] or posedge \$d(%,%)1 [0:0]) begin : _INTERNAL_w8_register
    if (\$d(%,%)1 [0:0]) begin
      _INTERNAL_w8_reg <= (1'b0);
    end else begin
      _INTERNAL_w8_reg <= (((~ w69) & (~ w64)) & (~ (w107 & c$w94_app_arg)));
    end
  end
  assign \_INTERNAL_.w8  = _INTERNAL_w8_reg;
  // register end

  assign \_INTERNAL_.w24  = \_INTERNAL_.w19  & (~ \_INTERNAL_.w15 );

  assign \_INTERNAL_.w14  = \c$_INTERNAL_.w14_app_arg_0  & \c$_INTERNAL_.w14_app_arg ;

  assign \_INTERNAL_.w59  = \c$_INTERNAL_.w59_app_arg  & \_INTERNAL_.w14 ;

  assign w53 = (~ w52) & c$w53_app_arg;

  assign w77 = c$w77_app_arg & (~ (w69 & w10_0));

  assign c$cout_app_arg_22 = ~ w57;

  assign c$w101_app_arg = ~ \c$_INTERNAL_.w7_0 ;

  assign c$w50_app_arg = ~ w48;

  assign w48 = c$w48_app_arg_0 & c$w48_app_arg;

  assign \_INTERNAL_.w19  = (~ \_INTERNAL_.w18 ) & \c$_INTERNAL_.w19_app_arg ;

  assign w116 = (~ (((~ w56) & c$w104_app_arg) & (~ ((\c$_INTERNAL_.w87_app_arg  & \_INTERNAL_.w8 ) & w37)))) & c$w101_app_arg;

  assign w57 = w56 & w53;

  assign c$cout_app_arg_23 = ~ w104;

  assign c$w77_app_arg = ~ w76;

  assign \c$_INTERNAL_.w6_app_arg_0  = ~ w32_0;

  assign c$w53_app_arg = cin_8[(64'sd2)];

  assign \c$_INTERNAL_.w59_app_arg  = ~ \_INTERNAL_.w38 ;

  assign \c$_INTERNAL_.w14_app_arg  = ~ \_INTERNAL_.w12 ;

  assign \c$_INTERNAL_.w14_app_arg_0  = ~ \_INTERNAL_.w13 ;

  assign w32_0 = (~ \_INTERNAL_.w31 ) & \c$_INTERNAL_.w7_0 ;

  assign w107 = w106 & c$w107_app_arg;

  assign \_INTERNAL_.w12  = \c$_INTERNAL_.w12_app_arg_0  & \c$_INTERNAL_.w12_app_arg ;

  assign \_INTERNAL_.w13  = \_INTERNAL_.w5  & \_INTERNAL_.w4 ;

  assign \_INTERNAL_.w15  = \c$_INTERNAL_.w14_app_arg_0  & \c$_INTERNAL_.w15_app_arg ;

  assign \_INTERNAL_.w38  = w37 & c$w48_app_arg_0;

  assign \_INTERNAL_.w123  = (~ (c$cout_app_arg_20 & c$w53_app_arg)) & w45;

  assign w56 = ((\_INTERNAL_.w5  & c$w129_app_arg) & \c$_INTERNAL_.w61_app_arg ) & \_INTERNAL_.w9 ;

  assign w52 = (~ ((~ w50) & c$w45_app_arg)) & c$w50_app_arg;

  assign w76 = (~ (c$w76_app_arg & \c$_INTERNAL_.w19_app_arg )) & w74;

  assign \c$_INTERNAL_.w19_app_arg  = ~ \_INTERNAL_.w14 ;

  assign c$w101_app_arg_0 = ~ w99;

  assign c$w48_app_arg = ~ \_INTERNAL_.w24 ;

  assign c$w48_app_arg_0 = ~ \_INTERNAL_.w35 ;

  assign \_INTERNAL_.w35  = \c$_INTERNAL_.w14_app_arg  & \c$_INTERNAL_.w15_app_arg ;

  assign w99 = (~ (w97 & \_INTERNAL_.w41 )) & \_INTERNAL_.w8 ;

  assign w10_0 = \_INTERNAL_.w9  & \c$_INTERNAL_.w12_app_arg_0 ;

  assign \_INTERNAL_.w87  = \c$_INTERNAL_.w87_app_arg_0  & \c$_INTERNAL_.w87_app_arg ;

  assign \_INTERNAL_.w29  = \_INTERNAL_.w23  & \c$_INTERNAL_.w61_app_arg ;

  assign w69 = w68 & \c$_INTERNAL_.w7_0 ;

  assign \_INTERNAL_.w9  = \c$_INTERNAL_.w15_app_arg  & \c$_INTERNAL_.w12_app_arg ;

  assign w45 = (~ (((~ w39) & c$w101_app_arg) & (~ (\_INTERNAL_.w41  & \c$_INTERNAL_.w61_app_arg )))) & c$w45_app_arg;

  // register begin
  reg  _INTERNAL_w5_reg = (1'b0);
  always @(posedge \$d(%,%)1 [1:1] or posedge \$d(%,%)1 [0:0]) begin : _INTERNAL_w5_register
    if (\$d(%,%)1 [0:0]) begin
      _INTERNAL_w5_reg <= (1'b0);
    end else begin
      _INTERNAL_w5_reg <= ((~ \_INTERNAL_.w123 ) & (~ w46));
    end
  end
  assign \_INTERNAL_.w5  = _INTERNAL_w5_reg;
  // register end

  // register begin
  reg  _INTERNAL_w4_reg = (1'b0);
  always @(posedge \$d(%,%)1 [1:1] or posedge \$d(%,%)1 [0:0]) begin : _INTERNAL_w4_register
    if (\$d(%,%)1 [0:0]) begin
      _INTERNAL_w4_reg <= (1'b0);
    end else begin
      _INTERNAL_w4_reg <= w94;
    end
  end
  assign \_INTERNAL_.w4  = _INTERNAL_w4_reg;
  // register end

  assign \_INTERNAL_.w18  = \c$_INTERNAL_.w6_0  & \_INTERNAL_.w4 ;

  assign w37 = (~ w36) & c$w48_app_arg;

  assign w74 = w73 & (~ (c$w74_app_arg & \_INTERNAL_.w8 ));

  assign \c$_INTERNAL_.w7_app_arg_0  = ~ w82;

  assign \c$_INTERNAL_.w15_app_arg  = ~ \c$_INTERNAL_.w6_0 ;

  assign \c$_INTERNAL_.w12_app_arg  = ~ \_INTERNAL_.w4 ;

  assign \c$_INTERNAL_.w12_app_arg_0  = ~ \_INTERNAL_.w5 ;

  assign c$w107_app_arg = ~ \_INTERNAL_.w61 ;

  assign \c$_INTERNAL_.w31_app_arg  = ~ \_INTERNAL_.w22 ;

  assign w26_0 = (~ (\_INTERNAL_.w24  & \_INTERNAL_.w8 )) & \c$_INTERNAL_.w7_0 ;

  assign w64 = \c$_INTERNAL_.w61_app_arg  & c$w101_app_arg;

  assign w97 = \c$_INTERNAL_.w61_app_arg_0  & \c$_INTERNAL_.w87_app_arg ;

  assign \_INTERNAL_.w22  = (~ ((\c$_INTERNAL_.w61_app_arg  & \c$_INTERNAL_.w22_app_arg ) & \c$_INTERNAL_.w23_app_arg )) & (~ \_INTERNAL_.w17 );

  assign \_INTERNAL_.w23  = \c$_INTERNAL_.w23_app_arg  & \c$_INTERNAL_.w6_0 ;

  assign w68 = (~ (\_INTERNAL_.w15  & \_INTERNAL_.w8 )) & c$w76_app_arg;

  assign w94 = c$cout_app_arg_20 & c$w94_app_arg;

  assign w66 = c$w66_app_arg & c$cout_app_arg_20;

  assign w73 = (~ (w37 & \c$_INTERNAL_.w61_app_arg )) & c$w101_app_arg;

  assign w82 = (~ w74) & c$w82_app_arg;

  assign c$w45_app_arg = ~ w34;

  assign \c$_INTERNAL_.w87_app_arg  = ~ \_INTERNAL_.w11 ;

  assign \c$_INTERNAL_.w87_app_arg_0  = ~ \_INTERNAL_.w16 ;

  assign w33_0 = \c$_INTERNAL_.w6_app_arg_0  & c$w82_app_arg;

  assign w34 = (~ w33_0) & \c$_INTERNAL_.w31_app_arg ;

  assign \_INTERNAL_.w11  = w10_0 & c$w129_app_arg;

  assign \_INTERNAL_.w16  = \_INTERNAL_.w15  & \c$_INTERNAL_.w22_app_arg ;

  assign w36 = \_INTERNAL_.w18  & \_INTERNAL_.w5 ;

  assign w78 = w77 & c$cout_app_arg_20;

  assign c$w82_app_arg = ~ w27;

  assign c$w76_app_arg = ~ \_INTERNAL_.w29 ;

  assign c$w66_app_arg = ~ w65;

  assign c$w94_app_arg = ~ c$w53_app_arg;

  assign \c$_INTERNAL_.w23_app_arg  = ~ \_INTERNAL_.w19 ;

  assign w27 = w26_0 & c$w74_app_arg;

  assign \_INTERNAL_.w17  = \c$_INTERNAL_.w87_app_arg_0  & \_INTERNAL_.w14 ;

  assign \_INTERNAL_.w41  = (~ w40) & c$w48_app_arg;

  assign w46 = (~ w45) & c$w53_app_arg;

  assign w65 = w64 & w40;

  assign c$w74_app_arg = ~ \_INTERNAL_.w23 ;

  assign w40 = \_INTERNAL_.w17  & (~ \_INTERNAL_.w9 );

  assign w85 = (~ (w79 & \c$_INTERNAL_.w19_app_arg )) & c$w66_app_arg;

  assign c$cout_app_arg_24 = ~ w92;

  assign \c$_INTERNAL_.w22_app_arg  = ~ c$w129_app_arg;

  assign w92 = (~ (w90 & \c$_INTERNAL_.w6_0 )) & (~ ((~ w85) & (~ \_INTERNAL_.w41 )));

  assign w79 = \_INTERNAL_.w8  & c$w101_app_arg;

  assign w93 = w92 & c$cout_app_arg_20;

  assign w81 = (~ (w79 & w36)) & c$w107_app_arg;

  assign c$cout_app_arg_25 = (~ w77);

  assign w58 = c$cout_app_arg_22 & (~ (w46 & \_INTERNAL_.w11 ));

  assign \$d(%,%)1  = {\$d(%,%) [1:1]
                      ,\$d(%,%) [0:0]};

  // blockRamFile begin
  reg [2:0] RAM_1 [0:1024-1];

  initial begin
    $readmemb("../LEDMatrixInitial.txt",RAM_1);
  end

  always @(posedge \$d(%,%) [1:1]) begin : TopEntity_blockRamFile_1
    if (c$ds_app_arg) begin
      RAM_1[(wild_4)] <= tup[2:0];
    end
    result_125 <= RAM_1[(wild_5)];
  end
  // blockRamFile end

  always @(*) begin
    case(wrM[13:13])
      1'b0 : c$ds_app_arg = 1'b0;
      default : c$ds_app_arg = 1'b1;
    endcase
  end

  assign wrM = result_109[20:7];

  always @(*) begin
    case(wrM[13:13])
      1'b0 : tup = {13 {1'bx}};
      default : tup = x_4;
    endcase
  end

  assign wild_4 = $signed(($signed({{(64-10) {1'b0}},x_2})));

  assign wild_5 = $signed(($signed({{(64-10) {1'b0}},x_3})));

  assign x_2 = tup[12:3];

  assign x_3 = result_109[30:21];

  assign x_4 = wrM[12:0];

  assign result_126 = {sensorOut[2:2]
                      ,sensorOut[3:3]
                      ,sensorOut[0:0]
                      ,1'b1
                      ,sensorOut[1:1]
                      ,result_161
                      ,c$case_alt_9
                      ,result_127[0:0]
                      ,result_127[1:1]};

  assign sensorOut = result_328[147:144];

  assign result_127 = {result_135[1:1]
                      ,result_135[0:0]};

  assign b_21 = ((c$ds1_app_arg_1 < 16'sd0) ? -c$ds1_app_arg_1 : c$ds1_app_arg_1) > 16'sd4096;

  assign b_22 = c$ds1_app_arg_1 > 16'sd20480;

  always @(*) begin
    case(result_161)
      2'b10 : b_23 = 1'b1;
      default : b_23 = 1'b0;
    endcase
  end

  always @(*) begin
    if(b_21)
      result_128 = 1'b1;
    else
      result_128 = 1'b0;
  end

  always @(*) begin
    if(b_22)
      result_129 = 1'b1;
    else
      result_129 = 1'b0;
  end

  always @(*) begin
    case(result_161)
      2'b00 : b_24 = 1'b1;
      default : b_24 = 1'b0;
    endcase
  end

  always @(*) begin
    if(b_23)
      result_130 = 1'b1;
    else
      result_130 = 1'b0;
  end

  assign b_25 = ((((gyrox < 16'sd0) ? -gyrox : gyrox) + ((gyroy < 16'sd0) ? -gyroy : gyroy)) + ((gyroz < 16'sd0) ? -gyroz : gyroz)) < 16'sd1792;

  always @(*) begin
    if(b_24)
      result_131 = 1'b1;
    else
      result_131 = 1'b0;
  end

  always @(*) begin
    if(b_25)
      result_132 = 1'b1;
    else
      result_132 = 1'b0;
  end

  assign w7_0 = ((cin_9[(64'sd0)]) & c$w9_app_arg_0) & (cin_9[(64'sd3)]);

  assign cin_9 = {result_132,({result_131,({result_130,({result_128,result_129})})})};

  assign c$w9_app_arg_0 = cin_9[(64'sd4)];

  assign w9_1 = c$w9_app_arg_0 & ((cin_9[(64'sd1)]) & (cin_9[(64'sd2)]));

  // register begin
  reg  dt_74_reg = 1'b0;
  always @(posedge \$d(%,%) [1:1] or posedge \$d(%,%) [0:0]) begin : dt_74_register
    if (\$d(%,%) [0:0]) begin
      dt_74_reg <= 1'b0;
    end else begin
      dt_74_reg <= result_133;
    end
  end
  assign dt_74 = dt_74_reg;
  // register end

  // register begin
  reg  dt_75_reg = 1'b0;
  always @(posedge \$d(%,%) [1:1] or posedge \$d(%,%) [0:0]) begin : dt_75_register
    if (\$d(%,%) [0:0]) begin
      dt_75_reg <= 1'b0;
    end else begin
      dt_75_reg <= result_134;
    end
  end
  assign dt_75 = dt_75_reg;
  // register end

  assign cout = {1'b0,({(w9_1),({((~ w9_1)),({1'b0,({(w7_0),((~ w7_0))})})})})};

  assign bs_55 = {((cout[(64'sd3)])),({((cout[(64'sd4)])),((cout[(64'sd5)]))})};

  assign bs_56 = {((cout[(64'sd0)])),({((cout[(64'sd1)])),((cout[(64'sd2)]))})};

  assign c$vecflat_138 = {1'b0,1'b1,dt_74};

  // index begin
  wire  vec_141 [0:3-1];

  genvar i_143;
  generate
  for (i_143=0; i_143 < 3; i_143=i_143+1) begin : mk_array_141
    assign vec_141[(3-1)-i_143] = c$vecflat_138[i_143*1+:1];
  end
  endgenerate

  assign c$o_shot_case_alt = vec_141[(64'sd0)];
  // index end

  assign c$vecflat_139 = {1'b0,1'b1,dt_74};

  // index begin
  wire  vec_142 [0:3-1];

  genvar i_144;
  generate
  for (i_144=0; i_144 < 3; i_144=i_144+1) begin : mk_array_142
    assign vec_142[(3-1)-i_144] = c$vecflat_139[i_144*1+:1];
  end
  endgenerate

  assign c$o_shot_case_alt_0 = vec_142[(64'sd1)];
  // index end

  assign c$vecflat_140 = {1'b0,1'b1,dt_75};

  // index begin
  wire  vec_143 [0:3-1];

  genvar i_145;
  generate
  for (i_145=0; i_145 < 3; i_145=i_145+1) begin : mk_array_143
    assign vec_143[(3-1)-i_145] = c$vecflat_140[i_145*1+:1];
  end
  endgenerate

  assign c$o_reset_case_alt = vec_143[(64'sd0)];
  // index end

  assign c$vecflat_141 = {1'b0,1'b1,dt_75};

  // index begin
  wire  vec_144 [0:3-1];

  genvar i_146;
  generate
  for (i_146=0; i_146 < 3; i_146=i_146+1) begin : mk_array_144
    assign vec_144[(3-1)-i_146] = c$vecflat_141[i_146*1+:1];
  end
  endgenerate

  assign c$o_reset_case_alt_0 = vec_144[(64'sd1)];
  // index end

  assign c$o_shot_case_alt_1_selection_res = (bs_55[(64'sd1)]) == (1'b1);

  always @(*) begin
    if(c$o_shot_case_alt_1_selection_res)
      c$o_shot_case_alt_1 = c$o_shot_case_alt_0;
    else
      c$o_shot_case_alt_1 = c$o_shot_case_alt;
  end

  assign c$vecflat_142 = {1'b0,1'b1,dt_74};

  // index begin
  wire  vec_145 [0:3-1];

  genvar i_147;
  generate
  for (i_147=0; i_147 < 3; i_147=i_147+1) begin : mk_array_145
    assign vec_145[(3-1)-i_147] = c$vecflat_142[i_147*1+:1];
  end
  endgenerate

  assign c$o_shot_case_alt_2 = vec_145[(64'sd2)];
  // index end

  assign c$o_reset_case_alt_1_selection_res = (bs_56[(64'sd1)]) == (1'b1);

  always @(*) begin
    if(c$o_reset_case_alt_1_selection_res)
      c$o_reset_case_alt_1 = c$o_reset_case_alt_0;
    else
      c$o_reset_case_alt_1 = c$o_reset_case_alt;
  end

  assign c$vecflat_143 = {1'b0,1'b1,dt_75};

  // index begin
  wire  vec_146 [0:3-1];

  genvar i_148;
  generate
  for (i_148=0; i_148 < 3; i_148=i_148+1) begin : mk_array_146
    assign vec_146[(3-1)-i_148] = c$vecflat_143[i_148*1+:1];
  end
  endgenerate

  assign c$o_reset_case_alt_2 = vec_146[(64'sd2)];
  // index end

  assign result_133_selection_res = (bs_55[(64'sd0)]) == (1'b1);

  always @(*) begin
    if(result_133_selection_res)
      result_133 = c$o_shot_case_alt_2;
    else
      result_133 = c$o_shot_case_alt_1;
  end

  assign result_134_selection_res = (bs_56[(64'sd0)]) == (1'b1);

  always @(*) begin
    if(result_134_selection_res)
      result_134 = c$o_reset_case_alt_2;
    else
      result_134 = c$o_reset_case_alt_1;
  end

  assign result_135 = {result_134,result_133};

  assign c$case_alt_9 = result_145[7:0];

  assign b_26 = ((gyrox < 16'sd0) ? -gyrox : gyrox) <= 16'sd128;

  assign b_27 = c_prescaler == 10'd0;

  assign b_28 = ((gyroz < 16'sd0) ? -gyroz : gyroz) <= 16'sd128;

  always @(*) begin
    if(b_26)
      result_136 = 1'b1;
    else
      result_136 = 1'b0;
  end

  always @(*) begin
    if(b_27)
      result_137 = 1'b1;
    else
      result_137 = 1'b0;
  end

  always @(*) begin
    case(result_161)
      2'b10 : b_29 = 1'b1;
      default : b_29 = 1'b0;
    endcase
  end

  always @(*) begin
    if(b_28)
      result_138 = 1'b1;
    else
      result_138 = 1'b0;
  end

  always @(*) begin
    case(result_161)
      2'b01 : b_30 = 1'b1;
      default : b_30 = 1'b0;
    endcase
  end

  always @(*) begin
    if(b_29)
      result_139 = 1'b1;
    else
      result_139 = 1'b0;
  end

  always @(*) begin
    case(result_161)
      2'b00 : b_31 = 1'b1;
      default : b_31 = 1'b0;
    endcase
  end

  always @(*) begin
    if(b_30)
      result_140 = 1'b1;
    else
      result_140 = 1'b0;
  end

  always @(*) begin
    if(b_31)
      result_141 = 1'b1;
    else
      result_141 = 1'b0;
  end

  assign cin_10 = {result_141,({result_140,({result_139,({result_138,({result_136,result_137})})})})};

  assign c$w9_app_arg_1 = cin_10[(64'sd0)];

  assign c$w11_app_arg_1 = ~ w8_1;

  assign w8_1 = (c$w9_app_arg_1 & (cin_10[(64'sd3)])) & (~ (cin_10[(64'sd1)]));

  assign w9_2 = c$w9_app_arg_1 & (~ (cin_10[(64'sd2)]));

  assign w10_1 = ((cin_10[(64'sd5)]) & w11_2) & w9_2;

  assign w11_2 = (~ ((cin_10[(64'sd4)]) & w9_2)) & c$w11_app_arg_1;

  assign dt_76 = c_internalRotation;

  assign dt_77 = c$dt_app_arg_6 - c$dt_app_arg_5;

  assign c$dt_app_arg_5 = $signed({{(28-16) {gyroz[16-1]}},gyroz});

  assign dt_78 = c$dt_app_arg_6 + c$dt_app_arg_5;

  // register begin
  reg [7:0] dt_79_reg = 8'd0;
  always @(posedge \$d(%,%) [1:1] or posedge \$d(%,%) [0:0]) begin : dt_79_register
    if (\$d(%,%) [0:0]) begin
      dt_79_reg <= 8'd0;
    end else begin
      dt_79_reg <= result_144;
    end
  end
  assign dt_79 = dt_79_reg;
  // register end

  // register begin
  reg signed [27:0] c_internalRotation_reg = 28'sd0;
  always @(posedge \$d(%,%) [1:1] or posedge \$d(%,%) [0:0]) begin : c_internalRotation_register
    if (\$d(%,%) [0:0]) begin
      c_internalRotation_reg <= 28'sd0;
    end else begin
      c_internalRotation_reg <= result_143;
    end
  end
  assign c_internalRotation = c_internalRotation_reg;
  // register end

  assign \_INTERNAL_.cout  = {1'b0,({1'b1,({1'b0,({1'b1,({((w11_2 & (~ w10_1))),({(w10_1),({(((~ w11_2) & c$w11_app_arg_1)),(w8_1)})})})})})})};

  assign c$dt_app_arg_6 = c_internalRotation + 28'sd80;

  // register begin
  reg [9:0] c_prescaler_reg = 10'd0;
  always @(posedge \$d(%,%) [1:1] or posedge \$d(%,%) [0:0]) begin : c_prescaler_register
    if (\$d(%,%) [0:0]) begin
      c_prescaler_reg <= 10'd0;
    end else begin
      c_prescaler_reg <= result_142;
    end
  end
  assign c_prescaler = c_prescaler_reg;
  // register end

  assign dt_80 = c_prescaler;

  assign dt_81 = (c_prescaler + 10'd1) % 10'd751;

  assign dt_82 = c$dt_app_arg_6 + ($signed({{(28-16) {gyrox[16-1]}},gyrox}));

  assign c$bv_9 = (($unsigned(c_internalRotation)) >> (64'sd20));

  assign dt_83 = (c$bv_9[0+:8]);

  assign bs_57 = {((\_INTERNAL_.cout [(64'sd4)])),((\_INTERNAL_.cout [(64'sd5)]))};

  assign c$vecflat_144 = {dt_82
                         ,{dt_78,{dt_77,dt_76}}};

  // index begin
  wire signed [27:0] vec_147 [0:4-1];

  genvar i_149;
  generate
  for (i_149=0; i_149 < 4; i_149=i_149+1) begin : mk_array_147
    assign vec_147[(4-1)-i_149] = c$vecflat_144[i_149*28+:28];
  end
  endgenerate

  assign \c$_INTERNAL_.o_internalRotation_case_alt  = vec_147[(64'sd0)];
  // index end

  assign c$vecflat_145 = {dt_82
                         ,{dt_78,{dt_77,dt_76}}};

  // index begin
  wire signed [27:0] vec_148 [0:4-1];

  genvar i_150;
  generate
  for (i_150=0; i_150 < 4; i_150=i_150+1) begin : mk_array_148
    assign vec_148[(4-1)-i_150] = c$vecflat_145[i_150*28+:28];
  end
  endgenerate

  assign \c$_INTERNAL_.o_internalRotation_case_alt_0  = vec_148[(64'sd1)];
  // index end

  assign bs_58 = {((\_INTERNAL_.cout [(64'sd0)])),({((\_INTERNAL_.cout [(64'sd1)])),({((\_INTERNAL_.cout [(64'sd2)])),((\_INTERNAL_.cout [(64'sd3)]))})})};

  assign bs_59 = {((\_INTERNAL_.cout [(64'sd6)])),((\_INTERNAL_.cout [(64'sd7)]))};

  assign \c$_INTERNAL_.o_internalRotation_case_alt_1_selection_res  = (bs_58[(64'sd2)]) == (1'b1);

  always @(*) begin
    if(\c$_INTERNAL_.o_internalRotation_case_alt_1_selection_res )
      \c$_INTERNAL_.o_internalRotation_case_alt_1  = \c$_INTERNAL_.o_internalRotation_case_alt_0 ;
    else
      \c$_INTERNAL_.o_internalRotation_case_alt_1  = \c$_INTERNAL_.o_internalRotation_case_alt ;
  end

  assign c$vecflat_146 = {dt_82
                         ,{dt_78,{dt_77,dt_76}}};

  // index begin
  wire signed [27:0] vec_149 [0:4-1];

  genvar i_151;
  generate
  for (i_151=0; i_151 < 4; i_151=i_151+1) begin : mk_array_149
    assign vec_149[(4-1)-i_151] = c$vecflat_146[i_151*28+:28];
  end
  endgenerate

  assign \c$_INTERNAL_.o_internalRotation_case_alt_2  = vec_149[(64'sd2)];
  // index end

  assign c$vecflat_147 = {dt_81,dt_80};

  // index begin
  wire [9:0] vec_150 [0:2-1];

  genvar i_152;
  generate
  for (i_152=0; i_152 < 2; i_152=i_152+1) begin : mk_array_150
    assign vec_150[(2-1)-i_152] = c$vecflat_147[i_152*10+:10];
  end
  endgenerate

  assign \c$_INTERNAL_.o_prescaler_case_alt  = vec_150[(64'sd0)];
  // index end

  assign c$vecflat_148 = {dt_81,dt_80};

  // index begin
  wire [9:0] vec_151 [0:2-1];

  genvar i_153;
  generate
  for (i_153=0; i_153 < 2; i_153=i_153+1) begin : mk_array_151
    assign vec_151[(2-1)-i_153] = c$vecflat_148[i_153*10+:10];
  end
  endgenerate

  assign \c$_INTERNAL_.o_prescaler_case_alt_0  = vec_151[(64'sd1)];
  // index end

  assign \c$_INTERNAL_.o_internalRotation_case_alt_3_selection_res  = (bs_58[(64'sd1)]) == (1'b1);

  always @(*) begin
    if(\c$_INTERNAL_.o_internalRotation_case_alt_3_selection_res )
      \c$_INTERNAL_.o_internalRotation_case_alt_3  = \c$_INTERNAL_.o_internalRotation_case_alt_2 ;
    else
      \c$_INTERNAL_.o_internalRotation_case_alt_3  = \c$_INTERNAL_.o_internalRotation_case_alt_1 ;
  end

  assign c$vecflat_149 = {dt_82
                         ,{dt_78,{dt_77,dt_76}}};

  // index begin
  wire signed [27:0] vec_152 [0:4-1];

  genvar i_154;
  generate
  for (i_154=0; i_154 < 4; i_154=i_154+1) begin : mk_array_152
    assign vec_152[(4-1)-i_154] = c$vecflat_149[i_154*28+:28];
  end
  endgenerate

  assign \c$_INTERNAL_.o_internalRotation_case_alt_4  = vec_152[(64'sd3)];
  // index end

  assign c$vecflat_150 = {dt_83,dt_79};

  // index begin
  wire [7:0] vec_153 [0:2-1];

  genvar i_155;
  generate
  for (i_155=0; i_155 < 2; i_155=i_155+1) begin : mk_array_153
    assign vec_153[(2-1)-i_155] = c$vecflat_150[i_155*8+:8];
  end
  endgenerate

  assign c$o_rotation_case_alt = vec_153[(64'sd0)];
  // index end

  assign c$vecflat_151 = {dt_83,dt_79};

  // index begin
  wire [7:0] vec_154 [0:2-1];

  genvar i_156;
  generate
  for (i_156=0; i_156 < 2; i_156=i_156+1) begin : mk_array_154
    assign vec_154[(2-1)-i_156] = c$vecflat_151[i_156*8+:8];
  end
  endgenerate

  assign c$o_rotation_case_alt_0 = vec_154[(64'sd1)];
  // index end

  assign result_142_selection_res = (bs_57[(64'sd0)]) == (1'b1);

  always @(*) begin
    if(result_142_selection_res)
      result_142 = \c$_INTERNAL_.o_prescaler_case_alt_0 ;
    else
      result_142 = \c$_INTERNAL_.o_prescaler_case_alt ;
  end

  assign result_143_selection_res = (bs_58[(64'sd0)]) == (1'b1);

  always @(*) begin
    if(result_143_selection_res)
      result_143 = \c$_INTERNAL_.o_internalRotation_case_alt_4 ;
    else
      result_143 = \c$_INTERNAL_.o_internalRotation_case_alt_3 ;
  end

  assign result_144_selection_res = (bs_59[(64'sd0)]) == (1'b1);

  always @(*) begin
    if(result_144_selection_res)
      result_144 = c$o_rotation_case_alt_0;
    else
      result_144 = c$o_rotation_case_alt;
  end

  assign result_145 = {result_143
                      ,result_142
                      ,result_144};

  assign result_146 = {result_149
                      ,result_148
                      ,result_147
                      ,result_150};

  assign result_147_selection_res = (bs_60[(64'sd0)]) == (1'b1);

  always @(*) begin
    if(result_147_selection_res)
      result_147 = \c$_INTERNAL_.o_reseter_case_alt ;
    else
      result_147 = \c$_INTERNAL_.o_reseter_case_alt_0 ;
  end

  assign result_148_selection_res = (bs_61[(64'sd0)]) == (1'b1);

  always @(*) begin
    if(result_148_selection_res)
      result_148 = \c$_INTERNAL_.o_prescaler_case_alt_1 ;
    else
      result_148 = \c$_INTERNAL_.o_prescaler_case_alt_2 ;
  end

  assign result_149_selection_res = (bs_62[(64'sd0)]) == (1'b1);

  always @(*) begin
    if(result_149_selection_res)
      result_149 = \c$_INTERNAL_.o_gamemode_case_alt ;
    else
      result_149 = \c$_INTERNAL_.o_gamemode_case_alt_0 ;
  end

  assign result_150_selection_res = (bs_63[(64'sd0)]) == (1'b1);

  always @(*) begin
    if(result_150_selection_res)
      result_150 = \c$_INTERNAL_.o_rotation_case_alt ;
    else
      result_150 = \c$_INTERNAL_.o_rotation_case_alt_0 ;
  end

  assign c$vecflat_152 = {c_reseter,dt_84};

  // index begin
  wire [23:0] vec_155 [0:2-1];

  genvar i_157;
  generate
  for (i_157=0; i_157 < 2; i_157=i_157+1) begin : mk_array_155
    assign vec_155[(2-1)-i_157] = c$vecflat_152[i_157*24+:24];
  end
  endgenerate

  assign \c$_INTERNAL_.o_reseter_case_alt  = vec_155[(64'sd1)];
  // index end

  assign c$vecflat_153 = {c_reseter,dt_84};

  // index begin
  wire [23:0] vec_156 [0:2-1];

  genvar i_158;
  generate
  for (i_158=0; i_158 < 2; i_158=i_158+1) begin : mk_array_156
    assign vec_156[(2-1)-i_158] = c$vecflat_153[i_158*24+:24];
  end
  endgenerate

  assign \c$_INTERNAL_.o_reseter_case_alt_0  = vec_156[(64'sd0)];
  // index end

  assign c$vecflat_154 = {c_prescaler_0,dt_85};

  // index begin
  wire [9:0] vec_157 [0:2-1];

  genvar i_159;
  generate
  for (i_159=0; i_159 < 2; i_159=i_159+1) begin : mk_array_157
    assign vec_157[(2-1)-i_159] = c$vecflat_154[i_159*10+:10];
  end
  endgenerate

  assign \c$_INTERNAL_.o_prescaler_case_alt_1  = vec_157[(64'sd1)];
  // index end

  assign c$vecflat_155 = {c_prescaler_0,dt_85};

  // index begin
  wire [9:0] vec_158 [0:2-1];

  genvar i_160;
  generate
  for (i_160=0; i_160 < 2; i_160=i_160+1) begin : mk_array_158
    assign vec_158[(2-1)-i_160] = c$vecflat_155[i_160*10+:10];
  end
  endgenerate

  assign \c$_INTERNAL_.o_prescaler_case_alt_2  = vec_158[(64'sd0)];
  // index end

  // index begin
  wire [1:0] vec_159 [0:4-1];

  genvar i_161;
  generate
  for (i_161=0; i_161 < 4; i_161=i_161+1) begin : mk_array_159
    assign vec_159[(4-1)-i_161] = vs[i_161*2+:2];
  end
  endgenerate

  assign \c$_INTERNAL_.o_gamemode_case_alt  = vec_159[(64'sd3)];
  // index end

  assign \c$_INTERNAL_.o_gamemode_case_alt_0_selection_res  = (bs_62[(64'sd1)]) == (1'b1);

  always @(*) begin
    if(\c$_INTERNAL_.o_gamemode_case_alt_0_selection_res )
      \c$_INTERNAL_.o_gamemode_case_alt_0  = \c$_INTERNAL_.o_gamemode_case_alt_1 ;
    else
      \c$_INTERNAL_.o_gamemode_case_alt_0  = \c$_INTERNAL_.o_gamemode_case_alt_2 ;
  end

  assign c$vecflat_156 = {c_rotation
                         ,28'sd0
                         ,dt_86};

  // index begin
  wire signed [27:0] vec_160 [0:3-1];

  genvar i_162;
  generate
  for (i_162=0; i_162 < 3; i_162=i_162+1) begin : mk_array_160
    assign vec_160[(3-1)-i_162] = c$vecflat_156[i_162*28+:28];
  end
  endgenerate

  assign \c$_INTERNAL_.o_rotation_case_alt  = vec_160[(64'sd2)];
  // index end

  assign \c$_INTERNAL_.o_rotation_case_alt_0_selection_res  = (bs_63[(64'sd1)]) == (1'b1);

  always @(*) begin
    if(\c$_INTERNAL_.o_rotation_case_alt_0_selection_res )
      \c$_INTERNAL_.o_rotation_case_alt_0  = \c$_INTERNAL_.o_rotation_case_alt_1 ;
    else
      \c$_INTERNAL_.o_rotation_case_alt_0  = \c$_INTERNAL_.o_rotation_case_alt_2 ;
  end

  assign vs = {c_gamemode,2'd2,2'd1,2'd0};

  // index begin
  wire [1:0] vec_161 [0:4-1];

  genvar i_163;
  generate
  for (i_163=0; i_163 < 4; i_163=i_163+1) begin : mk_array_161
    assign vec_161[(4-1)-i_163] = vs[i_163*2+:2];
  end
  endgenerate

  assign \c$_INTERNAL_.o_gamemode_case_alt_1  = vec_161[(64'sd2)];
  // index end

  assign \c$_INTERNAL_.o_gamemode_case_alt_2_selection_res  = (bs_62[(64'sd2)]) == (1'b1);

  always @(*) begin
    if(\c$_INTERNAL_.o_gamemode_case_alt_2_selection_res )
      \c$_INTERNAL_.o_gamemode_case_alt_2  = \c$_INTERNAL_.o_gamemode_case_alt_3 ;
    else
      \c$_INTERNAL_.o_gamemode_case_alt_2  = \c$_INTERNAL_.o_gamemode_case_alt_4 ;
  end

  assign c$vecflat_157 = {c_rotation
                         ,28'sd0
                         ,dt_86};

  // index begin
  wire signed [27:0] vec_162 [0:3-1];

  genvar i_164;
  generate
  for (i_164=0; i_164 < 3; i_164=i_164+1) begin : mk_array_162
    assign vec_162[(3-1)-i_164] = c$vecflat_157[i_164*28+:28];
  end
  endgenerate

  assign \c$_INTERNAL_.o_rotation_case_alt_1  = vec_162[(64'sd1)];
  // index end

  assign c$vecflat_158 = {c_rotation
                         ,28'sd0
                         ,dt_86};

  // index begin
  wire signed [27:0] vec_163 [0:3-1];

  genvar i_165;
  generate
  for (i_165=0; i_165 < 3; i_165=i_165+1) begin : mk_array_163
    assign vec_163[(3-1)-i_165] = c$vecflat_158[i_165*28+:28];
  end
  endgenerate

  assign \c$_INTERNAL_.o_rotation_case_alt_2  = vec_163[(64'sd0)];
  // index end

  // register begin
  reg [1:0] c_gamemode_reg = 2'd2;
  always @(posedge \$d(%,%) [1:1] or posedge \$d(%,%) [0:0]) begin : c_gamemode_register
    if (\$d(%,%) [0:0]) begin
      c_gamemode_reg <= 2'd2;
    end else begin
      c_gamemode_reg <= result_149;
    end
  end
  assign c_gamemode = c_gamemode_reg;
  // register end

  assign bs_60 = {((result_151[(64'sd6)])),((result_151[(64'sd7)]))};

  assign bs_61 = {((result_151[(64'sd4)])),((result_151[(64'sd5)]))};

  assign bs_62 = {((result_151[(64'sd0)])),({((result_151[(64'sd1)])),({((result_151[(64'sd2)])),((result_151[(64'sd3)]))})})};

  // index begin
  wire [1:0] vec_164 [0:4-1];

  genvar i_166;
  generate
  for (i_166=0; i_166 < 4; i_166=i_166+1) begin : mk_array_164
    assign vec_164[(4-1)-i_166] = vs[i_166*2+:2];
  end
  endgenerate

  assign \c$_INTERNAL_.o_gamemode_case_alt_3  = vec_164[(64'sd1)];
  // index end

  // index begin
  wire [1:0] vec_165 [0:4-1];

  genvar i_167;
  generate
  for (i_167=0; i_167 < 4; i_167=i_167+1) begin : mk_array_165
    assign vec_165[(4-1)-i_167] = vs[i_167*2+:2];
  end
  endgenerate

  assign \c$_INTERNAL_.o_gamemode_case_alt_4  = vec_165[(64'sd0)];
  // index end

  assign bs_63 = {((result_151[(64'sd8)])),({((result_151[(64'sd9)])),((result_151[(64'sd10)]))})};

  // register begin
  reg [23:0] c_reseter_reg = 24'd0;
  always @(posedge \$d(%,%) [1:1] or posedge \$d(%,%) [0:0]) begin : c_reseter_register
    if (\$d(%,%) [0:0]) begin
      c_reseter_reg <= 24'd0;
    end else begin
      c_reseter_reg <= result_147;
    end
  end
  assign c_reseter = c_reseter_reg;
  // register end

  // register begin
  reg [9:0] c_prescaler_0_reg = 10'd0;
  always @(posedge \$d(%,%) [1:1] or posedge \$d(%,%) [0:0]) begin : c_prescaler_0_register
    if (\$d(%,%) [0:0]) begin
      c_prescaler_0_reg <= 10'd0;
    end else begin
      c_prescaler_0_reg <= result_148;
    end
  end
  assign c_prescaler_0 = c_prescaler_0_reg;
  // register end

  // register begin
  reg signed [27:0] c_rotation_reg = 28'sd0;
  always @(posedge \$d(%,%) [1:1] or posedge \$d(%,%) [0:0]) begin : c_rotation_register
    if (\$d(%,%) [0:0]) begin
      c_rotation_reg <= 28'sd0;
    end else begin
      c_rotation_reg <= result_150;
    end
  end
  assign c_rotation = c_rotation_reg;
  // register end

  assign dt_84 = c_reseter + 24'd1;

  assign dt_85 = c_prescaler_0 + 10'd1;

  assign result_151 = {(((~ (w43 & w38)) & (~ w40_0))),({(w43),({((w40_0 & w37_0)),({1'b1,({1'b0,({1'b1,({1'b0,({((w16_0 & c$w23_app_arg)),({(\_INTERNAL_.w33 ),({(w27_0),(((~ \_INTERNAL_.w33 ) & w28))})})})})})})})})})};

  assign dt_86 = (c_rotation + 28'sd80) + ($signed({{(28-16) {gyroy[16-1]}},gyroy}));

  assign w43 = (~ (w39_0 & w36_0)) & (~ w37_0);

  assign w40_0 = (~ w39_0) & (~ w38);

  assign w38 = (~ (cin_11[(64'sd3)])) & (cin_11[(64'sd0)]);

  assign w37_0 = (~ w36_0) & w28;

  assign w39_0 = \_INTERNAL_.w33  & c$w28_app_arg;

  assign w36_0 = (cin_11[(64'sd2)]) & (cin_11[(64'sd1)]);

  assign w28 = (~ w27_0) & c$w28_app_arg;

  assign cin_11 = {result_152,({result_153,({result_154,({result_155,({result_156,({result_157,({result_158,({result_160,result_159})})})})})})})};

  assign \_INTERNAL_.w33  = (~ (((~ (\c$_INTERNAL_.w33_app_arg_0  & c$w27_app_arg)) & \c$_INTERNAL_.w33_app_arg ) & w12_1)) & (~ (\c$_INTERNAL_.w15_0  & c$w23_app_arg));

  assign c$w28_app_arg = ~ w23_0;

  assign w23_0 = (~ ((~ (\_INTERNAL_.w20  & \c$_INTERNAL_.w18_0 )) & (~ w16_0))) & c$w23_app_arg;

  assign w27_0 = ((~ \_INTERNAL_.w20 ) & \c$_INTERNAL_.w33_app_arg ) & (~ ((~ (w13_1 & c$w27_app_arg_0)) & c$w27_app_arg));

  always @(*) begin
    if(b_32)
      result_152 = 1'b1;
    else
      result_152 = 1'b0;
  end

  assign c$w23_app_arg = cin_11[(64'sd4)];

  always @(*) begin
    if(b_33)
      result_153 = 1'b1;
    else
      result_153 = 1'b0;
  end

  assign b_32 = c_rotation < -28'sd33554432;

  assign w16_0 = \c$_INTERNAL_.w15_0  & c$w27_app_arg;

  assign w12_1 = (~ (\c$_INTERNAL_.w15_app_arg_0  & c$w27_app_arg_0)) & c$w12_app_arg;

  assign \c$_INTERNAL_.w15_0  = ((~ \c$_INTERNAL_.w15_app_arg_0 ) & \c$_INTERNAL_.w18_app_arg ) & w13_1;

  always @(*) begin
    if(b_34)
      result_154 = 1'b1;
    else
      result_154 = 1'b0;
  end

  assign b_33 = c_rotation > 28'sd33554432;

  assign \_INTERNAL_.w20  = (~ (\c$_INTERNAL_.w18_0  & \c$_INTERNAL_.w15_app_arg_0 )) & (~ c$w27_app_arg);

  assign w13_1 = w12_1 & (~ \c$_INTERNAL_.w33_app_arg_0 );

  assign c$w27_app_arg = cin_11[(64'sd7)];

  assign \c$_INTERNAL_.w33_app_arg  = ~ c$w23_app_arg;

  assign c$w12_app_arg = ~ w10_2;

  always @(*) begin
    if(b_35)
      result_155 = 1'b1;
    else
      result_155 = 1'b0;
  end

  always @(*) begin
    case(c_gamemode)
      2'b00 : b_34 = 1'b1;
      default : b_34 = 1'b0;
    endcase
  end

  // register begin
  reg  w10_2_reg = (1'b0);
  always @(posedge \$d(%,%) [1:1] or posedge \$d(%,%) [0:0]) begin : w10_2_register
    if (\$d(%,%) [0:0]) begin
      w10_2_reg <= (1'b0);
    end else begin
      w10_2_reg <= w39_0;
    end
  end
  assign w10_2 = w10_2_reg;
  // register end

  always @(*) begin
    if(b_36)
      result_156 = 1'b1;
    else
      result_156 = 1'b0;
  end

  always @(*) begin
    case(c_gamemode)
      2'b01 : b_35 = 1'b1;
      default : b_35 = 1'b0;
    endcase
  end

  assign \c$_INTERNAL_.w18_0  = (\c$_INTERNAL_.w33_app_arg_0  & \c$_INTERNAL_.w18_app_arg ) & c$w12_app_arg;

  assign c$w27_app_arg_0 = cin_11[(64'sd5)];

  assign \c$_INTERNAL_.w33_app_arg_0  = cin_11[(64'sd8)];

  assign \c$_INTERNAL_.w15_app_arg_0  = cin_11[(64'sd6)];

  always @(*) begin
    if(b_37)
      result_157 = 1'b1;
    else
      result_157 = 1'b0;
  end

  always @(*) begin
    case(c_gamemode)
      2'b10 : b_36 = 1'b1;
      default : b_36 = 1'b0;
    endcase
  end

  always @(*) begin
    if(b_38)
      result_158 = 1'b1;
    else
      result_158 = 1'b0;
  end

  assign b_37 = ((gyroy < 16'sd0) ? -gyroy : gyroy) <= 16'sd128;

  assign \c$_INTERNAL_.w18_app_arg  = ~ c$w27_app_arg_0;

  always @(*) begin
    if(b_39)
      result_159 = 1'b1;
    else
      result_159 = 1'b0;
  end

  always @(*) begin
    if(b_40)
      result_160 = 1'b1;
    else
      result_160 = 1'b0;
  end

  assign b_38 = ((c_rotation < 28'sd0) ? -c_rotation : c_rotation) < 28'sd256;

  assign b_39 = c_prescaler_0 == 10'd0;

  assign b_40 = c_reseter == 24'd0;

  assign result_161 = result_146[63:62];

  // register begin
  reg  c$tup_app_arg_reg = 1'b0;
  always @(posedge \$d(%,%) [1:1] or posedge \$d(%,%) [0:0]) begin : c$tup_app_arg_register
    if (\$d(%,%) [0:0]) begin
      c$tup_app_arg_reg <= 1'b0;
    end else begin
      c$tup_app_arg_reg <= result_162[0:0];
    end
  end
  assign c$tup_app_arg = c$tup_app_arg_reg;
  // register end

  // register begin
  reg  c$tup_app_arg_0_reg = 1'b0;
  always @(posedge \$d(%,%) [1:1] or posedge \$d(%,%) [0:0]) begin : c$tup_app_arg_0_register
    if (\$d(%,%) [0:0]) begin
      c$tup_app_arg_0_reg <= 1'b0;
    end else begin
      c$tup_app_arg_0_reg <= result_183[0:0];
    end
  end
  assign c$tup_app_arg_0 = c$tup_app_arg_0_reg;
  // register end

  // register begin
  reg  c$tup_app_arg_1_reg = 1'b0;
  always @(posedge \$d(%,%) [1:1] or posedge \$d(%,%) [0:0]) begin : c$tup_app_arg_1_register
    if (\$d(%,%) [0:0]) begin
      c$tup_app_arg_1_reg <= 1'b0;
    end else begin
      c$tup_app_arg_1_reg <= result_169[0:0];
    end
  end
  assign c$tup_app_arg_1 = c$tup_app_arg_1_reg;
  // register end

  // register begin
  reg  c$tup_app_arg_2_reg = 1'b0;
  always @(posedge \$d(%,%) [1:1] or posedge \$d(%,%) [0:0]) begin : c$tup_app_arg_2_register
    if (\$d(%,%) [0:0]) begin
      c$tup_app_arg_2_reg <= 1'b0;
    end else begin
      c$tup_app_arg_2_reg <= result_176[0:0];
    end
  end
  assign c$tup_app_arg_2 = c$tup_app_arg_2_reg;
  // register end

  assign spiOutput = result_271[17:0];

  // register begin
  reg [17:0] c$ds1_app_arg_0_reg = {2'b00,16'bxxxxxxxxxxxxxxxx};
  always @(posedge \$d(%,%) [1:1] or posedge \$d(%,%) [0:0]) begin : c$ds1_app_arg_0_register
    if (\$d(%,%) [0:0]) begin
      c$ds1_app_arg_0_reg <= {2'b00,16'bxxxxxxxxxxxxxxxx};
    end else begin
      c$ds1_app_arg_0_reg <= result_272[33:16];
    end
  end
  assign c$ds1_app_arg_0 = c$ds1_app_arg_0_reg;
  // register end

  assign result_162 = {result_163
                      ,result_164
                      ,result_165
                      ,result_166};

  assign result_163_selection_res = (bs_64[(64'sd0)]) == (1'b1);

  always @(*) begin
    if(result_163_selection_res)
      result_163 = c$o_regmanage_case_alt;
    else
      result_163 = c$o_regmanage_case_alt_0;
  end

  assign result_164_selection_res = (bs_65[(64'sd0)]) == (1'b1);

  always @(*) begin
    if(result_164_selection_res)
      result_164 = c$o_sensorType_case_alt;
    else
      result_164 = c$o_sensorType_case_alt_0;
  end

  assign result_165_selection_res = (bs_66[(64'sd0)]) == (1'b1);

  always @(*) begin
    if(result_165_selection_res)
      result_165 = c$o_sensorcontrol_case_alt;
    else
      result_165 = c$o_sensorcontrol_case_alt_0;
  end

  assign result_166_selection_res = (bs_67[(64'sd0)]) == (1'b1);

  always @(*) begin
    if(result_166_selection_res)
      result_166 = c$o_status_case_alt;
    else
      result_166 = c$o_status_case_alt_0;
  end

  assign c$vecflat_159 = {dt_87
                         ,{1'b0,13'bxxxxxxxxxxxxx}
                         ,dt_91
                         ,dt_92
                         ,dt_93
                         ,dt_94
                         ,dt_95
                         ,dt_96};

  // index begin
  wire [13:0] vec_166 [0:8-1];

  genvar i_168;
  generate
  for (i_168=0; i_168 < 8; i_168=i_168+1) begin : mk_array_166
    assign vec_166[(8-1)-i_168] = c$vecflat_159[i_168*14+:14];
  end
  endgenerate

  assign c$o_regmanage_case_alt = vec_166[(64'sd7)];
  // index end

  assign c$o_regmanage_case_alt_0_selection_res = (bs_64[(64'sd1)]) == (1'b1);

  always @(*) begin
    if(c$o_regmanage_case_alt_0_selection_res)
      c$o_regmanage_case_alt_0 = c$o_regmanage_case_alt_1;
    else
      c$o_regmanage_case_alt_0 = c$o_regmanage_case_alt_2;
  end

  assign c$vecflat_160 = {dt_88,2'd0};

  // index begin
  wire [1:0] vec_167 [0:2-1];

  genvar i_169;
  generate
  for (i_169=0; i_169 < 2; i_169=i_169+1) begin : mk_array_167
    assign vec_167[(2-1)-i_169] = c$vecflat_160[i_169*2+:2];
  end
  endgenerate

  assign c$o_sensorType_case_alt = vec_167[(64'sd1)];
  // index end

  assign c$vecflat_161 = {dt_88,2'd0};

  // index begin
  wire [1:0] vec_168 [0:2-1];

  genvar i_170;
  generate
  for (i_170=0; i_170 < 2; i_170=i_170+1) begin : mk_array_168
    assign vec_168[(2-1)-i_170] = c$vecflat_161[i_170*2+:2];
  end
  endgenerate

  assign c$o_sensorType_case_alt_0 = vec_168[(64'sd0)];
  // index end

  assign c$vecflat_162 = {dt_89
                         ,{2'b00,16'bxxxxxxxxxxxxxxxx}
                         ,{2'b10,8'b00101000,8'bxxxxxxxx}
                         ,{2'b10,8'b00101001,8'bxxxxxxxx}
                         ,{2'b10,8'b00101010,8'bxxxxxxxx}
                         ,{2'b10,8'b00101011,8'bxxxxxxxx}
                         ,{2'b10,8'b00101100,8'bxxxxxxxx}
                         ,{2'b10,8'b00101101,8'bxxxxxxxx}};

  // index begin
  wire [17:0] vec_169 [0:8-1];

  genvar i_171;
  generate
  for (i_171=0; i_171 < 8; i_171=i_171+1) begin : mk_array_169
    assign vec_169[(8-1)-i_171] = c$vecflat_162[i_171*18+:18];
  end
  endgenerate

  assign c$o_sensorcontrol_case_alt = vec_169[(64'sd7)];
  // index end

  assign c$o_sensorcontrol_case_alt_0_selection_res = (bs_66[(64'sd1)]) == (1'b1);

  always @(*) begin
    if(c$o_sensorcontrol_case_alt_0_selection_res)
      c$o_sensorcontrol_case_alt_0 = c$o_sensorcontrol_case_alt_1;
    else
      c$o_sensorcontrol_case_alt_0 = c$o_sensorcontrol_case_alt_2;
  end

  assign c$vecflat_163 = {dt_90,1'b0,1'b1};

  // index begin
  wire  vec_170 [0:3-1];

  genvar i_172;
  generate
  for (i_172=0; i_172 < 3; i_172=i_172+1) begin : mk_array_170
    assign vec_170[(3-1)-i_172] = c$vecflat_163[i_172*1+:1];
  end
  endgenerate

  assign c$o_status_case_alt = vec_170[(64'sd2)];
  // index end

  assign c$o_status_case_alt_0_selection_res = (bs_67[(64'sd1)]) == (1'b1);

  always @(*) begin
    if(c$o_status_case_alt_0_selection_res)
      c$o_status_case_alt_0 = c$o_status_case_alt_1;
    else
      c$o_status_case_alt_0 = c$o_status_case_alt_2;
  end

  assign c$vecflat_164 = {dt_87
                         ,{1'b0,13'bxxxxxxxxxxxxx}
                         ,dt_91
                         ,dt_92
                         ,dt_93
                         ,dt_94
                         ,dt_95
                         ,dt_96};

  // index begin
  wire [13:0] vec_171 [0:8-1];

  genvar i_173;
  generate
  for (i_173=0; i_173 < 8; i_173=i_173+1) begin : mk_array_171
    assign vec_171[(8-1)-i_173] = c$vecflat_164[i_173*14+:14];
  end
  endgenerate

  assign c$o_regmanage_case_alt_1 = vec_171[(64'sd6)];
  // index end

  assign c$o_regmanage_case_alt_2_selection_res = (bs_64[(64'sd2)]) == (1'b1);

  always @(*) begin
    if(c$o_regmanage_case_alt_2_selection_res)
      c$o_regmanage_case_alt_2 = c$o_regmanage_case_alt_3;
    else
      c$o_regmanage_case_alt_2 = c$o_regmanage_case_alt_4;
  end

  assign c$vecflat_165 = {dt_89
                         ,{2'b00,16'bxxxxxxxxxxxxxxxx}
                         ,{2'b10,8'b00101000,8'bxxxxxxxx}
                         ,{2'b10,8'b00101001,8'bxxxxxxxx}
                         ,{2'b10,8'b00101010,8'bxxxxxxxx}
                         ,{2'b10,8'b00101011,8'bxxxxxxxx}
                         ,{2'b10,8'b00101100,8'bxxxxxxxx}
                         ,{2'b10,8'b00101101,8'bxxxxxxxx}};

  // index begin
  wire [17:0] vec_172 [0:8-1];

  genvar i_174;
  generate
  for (i_174=0; i_174 < 8; i_174=i_174+1) begin : mk_array_172
    assign vec_172[(8-1)-i_174] = c$vecflat_165[i_174*18+:18];
  end
  endgenerate

  assign c$o_sensorcontrol_case_alt_1 = vec_172[(64'sd6)];
  // index end

  assign c$o_sensorcontrol_case_alt_2_selection_res = (bs_66[(64'sd2)]) == (1'b1);

  always @(*) begin
    if(c$o_sensorcontrol_case_alt_2_selection_res)
      c$o_sensorcontrol_case_alt_2 = c$o_sensorcontrol_case_alt_3;
    else
      c$o_sensorcontrol_case_alt_2 = c$o_sensorcontrol_case_alt_4;
  end

  assign c$vecflat_166 = {dt_90,1'b0,1'b1};

  // index begin
  wire  vec_173 [0:3-1];

  genvar i_175;
  generate
  for (i_175=0; i_175 < 3; i_175=i_175+1) begin : mk_array_173
    assign vec_173[(3-1)-i_175] = c$vecflat_166[i_175*1+:1];
  end
  endgenerate

  assign c$o_status_case_alt_1 = vec_173[(64'sd1)];
  // index end

  assign c$vecflat_167 = {dt_90,1'b0,1'b1};

  // index begin
  wire  vec_174 [0:3-1];

  genvar i_176;
  generate
  for (i_176=0; i_176 < 3; i_176=i_176+1) begin : mk_array_174
    assign vec_174[(3-1)-i_176] = c$vecflat_167[i_176*1+:1];
  end
  endgenerate

  assign c$o_status_case_alt_2 = vec_174[(64'sd0)];
  // index end

  assign bs_64 = {((result_167[(64'sd0)])),({((result_167[(64'sd1)])),({((result_167[(64'sd2)])),({((result_167[(64'sd3)])),({((result_167[(64'sd4)])),({((result_167[(64'sd5)])),({((result_167[(64'sd6)])),((result_167[(64'sd7)]))})})})})})})};

  assign c$vecflat_168 = {dt_87
                         ,{1'b0,13'bxxxxxxxxxxxxx}
                         ,dt_91
                         ,dt_92
                         ,dt_93
                         ,dt_94
                         ,dt_95
                         ,dt_96};

  // index begin
  wire [13:0] vec_175 [0:8-1];

  genvar i_177;
  generate
  for (i_177=0; i_177 < 8; i_177=i_177+1) begin : mk_array_175
    assign vec_175[(8-1)-i_177] = c$vecflat_168[i_177*14+:14];
  end
  endgenerate

  assign c$o_regmanage_case_alt_3 = vec_175[(64'sd5)];
  // index end

  assign c$o_regmanage_case_alt_4_selection_res = (bs_64[(64'sd3)]) == (1'b1);

  always @(*) begin
    if(c$o_regmanage_case_alt_4_selection_res)
      c$o_regmanage_case_alt_4 = c$o_regmanage_case_alt_5;
    else
      c$o_regmanage_case_alt_4 = c$o_regmanage_case_alt_6;
  end

  assign bs_65 = {((result_167[(64'sd8)])),((result_167[(64'sd9)]))};

  assign bs_66 = {((result_167[(64'sd10)])),({((result_167[(64'sd11)])),({((result_167[(64'sd12)])),({((result_167[(64'sd13)])),({((result_167[(64'sd14)])),({((result_167[(64'sd15)])),({((result_167[(64'sd16)])),((result_167[(64'sd17)]))})})})})})})};

  assign c$vecflat_169 = {dt_89
                         ,{2'b00,16'bxxxxxxxxxxxxxxxx}
                         ,{2'b10,8'b00101000,8'bxxxxxxxx}
                         ,{2'b10,8'b00101001,8'bxxxxxxxx}
                         ,{2'b10,8'b00101010,8'bxxxxxxxx}
                         ,{2'b10,8'b00101011,8'bxxxxxxxx}
                         ,{2'b10,8'b00101100,8'bxxxxxxxx}
                         ,{2'b10,8'b00101101,8'bxxxxxxxx}};

  // index begin
  wire [17:0] vec_176 [0:8-1];

  genvar i_178;
  generate
  for (i_178=0; i_178 < 8; i_178=i_178+1) begin : mk_array_176
    assign vec_176[(8-1)-i_178] = c$vecflat_169[i_178*18+:18];
  end
  endgenerate

  assign c$o_sensorcontrol_case_alt_3 = vec_176[(64'sd5)];
  // index end

  assign c$o_sensorcontrol_case_alt_4_selection_res = (bs_66[(64'sd3)]) == (1'b1);

  always @(*) begin
    if(c$o_sensorcontrol_case_alt_4_selection_res)
      c$o_sensorcontrol_case_alt_4 = c$o_sensorcontrol_case_alt_5;
    else
      c$o_sensorcontrol_case_alt_4 = c$o_sensorcontrol_case_alt_6;
  end

  assign bs_67 = {((result_167[(64'sd18)])),({((result_167[(64'sd19)])),((result_167[(64'sd20)]))})};

  assign c$vecflat_170 = {dt_87
                         ,{1'b0,13'bxxxxxxxxxxxxx}
                         ,dt_91
                         ,dt_92
                         ,dt_93
                         ,dt_94
                         ,dt_95
                         ,dt_96};

  // index begin
  wire [13:0] vec_177 [0:8-1];

  genvar i_179;
  generate
  for (i_179=0; i_179 < 8; i_179=i_179+1) begin : mk_array_177
    assign vec_177[(8-1)-i_179] = c$vecflat_170[i_179*14+:14];
  end
  endgenerate

  assign c$o_regmanage_case_alt_5 = vec_177[(64'sd4)];
  // index end

  assign c$o_regmanage_case_alt_6_selection_res = (bs_64[(64'sd4)]) == (1'b1);

  always @(*) begin
    if(c$o_regmanage_case_alt_6_selection_res)
      c$o_regmanage_case_alt_6 = c$o_regmanage_case_alt_7;
    else
      c$o_regmanage_case_alt_6 = c$o_regmanage_case_alt_8;
  end

  // register begin
  reg [13:0] dt_87_reg = {1'b0,13'bxxxxxxxxxxxxx};
  always @(posedge \$d(%,%) [1:1] or posedge \$d(%,%) [0:0]) begin : dt_87_register
    if (\$d(%,%) [0:0]) begin
      dt_87_reg <= {1'b0,13'bxxxxxxxxxxxxx};
    end else begin
      dt_87_reg <= result_163;
    end
  end
  assign dt_87 = dt_87_reg;
  // register end

  // register begin
  reg [1:0] dt_88_reg = 2'd3;
  always @(posedge \$d(%,%) [1:1] or posedge \$d(%,%) [0:0]) begin : dt_88_register
    if (\$d(%,%) [0:0]) begin
      dt_88_reg <= 2'd3;
    end else begin
      dt_88_reg <= result_164;
    end
  end
  assign dt_88 = dt_88_reg;
  // register end

  assign c$vecflat_171 = {dt_89
                         ,{2'b00,16'bxxxxxxxxxxxxxxxx}
                         ,{2'b10,8'b00101000,8'bxxxxxxxx}
                         ,{2'b10,8'b00101001,8'bxxxxxxxx}
                         ,{2'b10,8'b00101010,8'bxxxxxxxx}
                         ,{2'b10,8'b00101011,8'bxxxxxxxx}
                         ,{2'b10,8'b00101100,8'bxxxxxxxx}
                         ,{2'b10,8'b00101101,8'bxxxxxxxx}};

  // index begin
  wire [17:0] vec_178 [0:8-1];

  genvar i_180;
  generate
  for (i_180=0; i_180 < 8; i_180=i_180+1) begin : mk_array_178
    assign vec_178[(8-1)-i_180] = c$vecflat_171[i_180*18+:18];
  end
  endgenerate

  assign c$o_sensorcontrol_case_alt_5 = vec_178[(64'sd4)];
  // index end

  assign c$o_sensorcontrol_case_alt_6_selection_res = (bs_66[(64'sd4)]) == (1'b1);

  always @(*) begin
    if(c$o_sensorcontrol_case_alt_6_selection_res)
      c$o_sensorcontrol_case_alt_6 = c$o_sensorcontrol_case_alt_7;
    else
      c$o_sensorcontrol_case_alt_6 = c$o_sensorcontrol_case_alt_8;
  end

  // register begin
  reg [17:0] dt_89_reg = {2'b00,16'bxxxxxxxxxxxxxxxx};
  always @(posedge \$d(%,%) [1:1] or posedge \$d(%,%) [0:0]) begin : dt_89_register
    if (\$d(%,%) [0:0]) begin
      dt_89_reg <= {2'b00,16'bxxxxxxxxxxxxxxxx};
    end else begin
      dt_89_reg <= result_165;
    end
  end
  assign dt_89 = dt_89_reg;
  // register end

  // register begin
  reg  dt_90_reg = 1'b0;
  always @(posedge \$d(%,%) [1:1] or posedge \$d(%,%) [0:0]) begin : dt_90_register
    if (\$d(%,%) [0:0]) begin
      dt_90_reg <= 1'b0;
    end else begin
      dt_90_reg <= result_166;
    end
  end
  assign dt_90 = dt_90_reg;
  // register end

  assign c$vecflat_172 = {dt_87
                         ,{1'b0,13'bxxxxxxxxxxxxx}
                         ,dt_91
                         ,dt_92
                         ,dt_93
                         ,dt_94
                         ,dt_95
                         ,dt_96};

  // index begin
  wire [13:0] vec_179 [0:8-1];

  genvar i_181;
  generate
  for (i_181=0; i_181 < 8; i_181=i_181+1) begin : mk_array_179
    assign vec_179[(8-1)-i_181] = c$vecflat_172[i_181*14+:14];
  end
  endgenerate

  assign c$o_regmanage_case_alt_7 = vec_179[(64'sd3)];
  // index end

  assign c$o_regmanage_case_alt_8_selection_res = (bs_64[(64'sd5)]) == (1'b1);

  always @(*) begin
    if(c$o_regmanage_case_alt_8_selection_res)
      c$o_regmanage_case_alt_8 = c$o_regmanage_case_alt_9;
    else
      c$o_regmanage_case_alt_8 = c$o_regmanage_case_alt_10;
  end

  assign c$vecflat_173 = {dt_89
                         ,{2'b00,16'bxxxxxxxxxxxxxxxx}
                         ,{2'b10,8'b00101000,8'bxxxxxxxx}
                         ,{2'b10,8'b00101001,8'bxxxxxxxx}
                         ,{2'b10,8'b00101010,8'bxxxxxxxx}
                         ,{2'b10,8'b00101011,8'bxxxxxxxx}
                         ,{2'b10,8'b00101100,8'bxxxxxxxx}
                         ,{2'b10,8'b00101101,8'bxxxxxxxx}};

  // index begin
  wire [17:0] vec_180 [0:8-1];

  genvar i_182;
  generate
  for (i_182=0; i_182 < 8; i_182=i_182+1) begin : mk_array_180
    assign vec_180[(8-1)-i_182] = c$vecflat_173[i_182*18+:18];
  end
  endgenerate

  assign c$o_sensorcontrol_case_alt_7 = vec_180[(64'sd3)];
  // index end

  assign c$o_sensorcontrol_case_alt_8_selection_res = (bs_66[(64'sd5)]) == (1'b1);

  always @(*) begin
    if(c$o_sensorcontrol_case_alt_8_selection_res)
      c$o_sensorcontrol_case_alt_8 = c$o_sensorcontrol_case_alt_9;
    else
      c$o_sensorcontrol_case_alt_8 = c$o_sensorcontrol_case_alt_10;
  end

  assign c$vecflat_174 = {dt_87
                         ,{1'b0,13'bxxxxxxxxxxxxx}
                         ,dt_91
                         ,dt_92
                         ,dt_93
                         ,dt_94
                         ,dt_95
                         ,dt_96};

  // index begin
  wire [13:0] vec_181 [0:8-1];

  genvar i_183;
  generate
  for (i_183=0; i_183 < 8; i_183=i_183+1) begin : mk_array_181
    assign vec_181[(8-1)-i_183] = c$vecflat_174[i_183*14+:14];
  end
  endgenerate

  assign c$o_regmanage_case_alt_9 = vec_181[(64'sd2)];
  // index end

  assign c$o_regmanage_case_alt_10_selection_res = (bs_64[(64'sd6)]) == (1'b1);

  always @(*) begin
    if(c$o_regmanage_case_alt_10_selection_res)
      c$o_regmanage_case_alt_10 = c$o_regmanage_case_alt_11;
    else
      c$o_regmanage_case_alt_10 = c$o_regmanage_case_alt_12;
  end

  assign c$vecflat_175 = {dt_89
                         ,{2'b00,16'bxxxxxxxxxxxxxxxx}
                         ,{2'b10,8'b00101000,8'bxxxxxxxx}
                         ,{2'b10,8'b00101001,8'bxxxxxxxx}
                         ,{2'b10,8'b00101010,8'bxxxxxxxx}
                         ,{2'b10,8'b00101011,8'bxxxxxxxx}
                         ,{2'b10,8'b00101100,8'bxxxxxxxx}
                         ,{2'b10,8'b00101101,8'bxxxxxxxx}};

  // index begin
  wire [17:0] vec_182 [0:8-1];

  genvar i_184;
  generate
  for (i_184=0; i_184 < 8; i_184=i_184+1) begin : mk_array_182
    assign vec_182[(8-1)-i_184] = c$vecflat_175[i_184*18+:18];
  end
  endgenerate

  assign c$o_sensorcontrol_case_alt_9 = vec_182[(64'sd2)];
  // index end

  assign c$o_sensorcontrol_case_alt_10_selection_res = (bs_66[(64'sd6)]) == (1'b1);

  always @(*) begin
    if(c$o_sensorcontrol_case_alt_10_selection_res)
      c$o_sensorcontrol_case_alt_10 = c$o_sensorcontrol_case_alt_11;
    else
      c$o_sensorcontrol_case_alt_10 = c$o_sensorcontrol_case_alt_12;
  end

  assign c$vecflat_176 = {dt_87
                         ,{1'b0,13'bxxxxxxxxxxxxx}
                         ,dt_91
                         ,dt_92
                         ,dt_93
                         ,dt_94
                         ,dt_95
                         ,dt_96};

  // index begin
  wire [13:0] vec_183 [0:8-1];

  genvar i_185;
  generate
  for (i_185=0; i_185 < 8; i_185=i_185+1) begin : mk_array_183
    assign vec_183[(8-1)-i_185] = c$vecflat_176[i_185*14+:14];
  end
  endgenerate

  assign c$o_regmanage_case_alt_11 = vec_183[(64'sd1)];
  // index end

  assign c$vecflat_177 = {dt_87
                         ,{1'b0,13'bxxxxxxxxxxxxx}
                         ,dt_91
                         ,dt_92
                         ,dt_93
                         ,dt_94
                         ,dt_95
                         ,dt_96};

  // index begin
  wire [13:0] vec_184 [0:8-1];

  genvar i_186;
  generate
  for (i_186=0; i_186 < 8; i_186=i_186+1) begin : mk_array_184
    assign vec_184[(8-1)-i_186] = c$vecflat_177[i_186*14+:14];
  end
  endgenerate

  assign c$o_regmanage_case_alt_12 = vec_184[(64'sd0)];
  // index end

  assign c$vecflat_178 = {dt_89
                         ,{2'b00,16'bxxxxxxxxxxxxxxxx}
                         ,{2'b10,8'b00101000,8'bxxxxxxxx}
                         ,{2'b10,8'b00101001,8'bxxxxxxxx}
                         ,{2'b10,8'b00101010,8'bxxxxxxxx}
                         ,{2'b10,8'b00101011,8'bxxxxxxxx}
                         ,{2'b10,8'b00101100,8'bxxxxxxxx}
                         ,{2'b10,8'b00101101,8'bxxxxxxxx}};

  // index begin
  wire [17:0] vec_185 [0:8-1];

  genvar i_187;
  generate
  for (i_187=0; i_187 < 8; i_187=i_187+1) begin : mk_array_185
    assign vec_185[(8-1)-i_187] = c$vecflat_178[i_187*18+:18];
  end
  endgenerate

  assign c$o_sensorcontrol_case_alt_11 = vec_185[(64'sd1)];
  // index end

  assign c$vecflat_179 = {dt_89
                         ,{2'b00,16'bxxxxxxxxxxxxxxxx}
                         ,{2'b10,8'b00101000,8'bxxxxxxxx}
                         ,{2'b10,8'b00101001,8'bxxxxxxxx}
                         ,{2'b10,8'b00101010,8'bxxxxxxxx}
                         ,{2'b10,8'b00101011,8'bxxxxxxxx}
                         ,{2'b10,8'b00101100,8'bxxxxxxxx}
                         ,{2'b10,8'b00101101,8'bxxxxxxxx}};

  // index begin
  wire [17:0] vec_186 [0:8-1];

  genvar i_188;
  generate
  for (i_188=0; i_188 < 8; i_188=i_188+1) begin : mk_array_186
    assign vec_186[(8-1)-i_188] = c$vecflat_179[i_188*18+:18];
  end
  endgenerate

  assign c$o_sensorcontrol_case_alt_12 = vec_186[(64'sd0)];
  // index end

  assign result_167 = {c$cout_app_arg_26,({(c$cout_app_arg_27),({1'b0,({c$cout_app_arg_28,({c$cout_app_arg_29,({c$cout_app_arg_30,({c$cout_app_arg_31,({c$cout_app_arg_32,({(w20_0),({(((~ (c$cout_app_arg_27 & w7_1)) & \c$_INTERNAL_.w4_app_arg )),({1'b0,({1'b1,({1'b0,({c$cout_app_arg_32,({c$cout_app_arg_30,({c$cout_app_arg_29,({c$cout_app_arg_31,({c$cout_app_arg_28,({c$cout_app_arg_26,({((~ w7_1)),1'b0})})})})})})})})})})})})})})})})})})})};

  always @(*) begin
    case(spiOutput[17:16])
      2'b10 : dt_91 = {1'b1,{4'd3,1'd1,dat}};
      default : dt_91 = {1'b0,13'bxxxxxxxxxxxxx};
    endcase
  end

  assign c$cout_app_arg_26 = w10_3;

  assign w10_3 = w9_3 & w8_2;

  always @(*) begin
    case(spiOutput[17:16])
      2'b10 : dt_92 = {1'b1,{4'd3,1'd0,dat}};
      default : dt_92 = {1'b0,13'bxxxxxxxxxxxxx};
    endcase
  end

  assign w9_3 = \_INTERNAL_.w3  & c$w9_app_arg_2;

  assign w8_2 = \c$_INTERNAL_.w5_0  & \c$_INTERNAL_.w4_0 ;

  assign c$cout_app_arg_27 = ~ w10_3;

  // register begin
  reg  c$_INTERNAL_w4_0_reg = (1'b0);
  always @(posedge \$d(%,%) [1:1] or posedge \$d(%,%) [0:0]) begin : c$_INTERNAL_w4_0_register
    if (\$d(%,%) [0:0]) begin
      c$_INTERNAL_w4_0_reg <= (1'b0);
    end else begin
      c$_INTERNAL_w4_0_reg <= (~ ((\c$_INTERNAL_.w4_app_arg  & (~ w17_0)) & (~ ((~ w9_3) & \c$_INTERNAL_.w4_0 ))));
    end
  end
  assign \c$_INTERNAL_.w4_0  = c$_INTERNAL_w4_0_reg;
  // register end

  // register begin
  reg  _INTERNAL_w3_reg = (1'b0);
  always @(posedge \$d(%,%) [1:1] or posedge \$d(%,%) [0:0]) begin : _INTERNAL_w3_register
    if (\$d(%,%) [0:0]) begin
      _INTERNAL_w3_reg <= (1'b0);
    end else begin
      _INTERNAL_w3_reg <= (~ ((~ ((\c$_INTERNAL_.w3_app_arg  & c$w11_app_arg_2) & (~ (w6_0 & (~ \c$_INTERNAL_.w3_app_arg_0 ))))) & (~ ((~ (\c$_INTERNAL_.w3_app_arg  & (~ (w8_2 & \c$_INTERNAL_.w3_app_arg_0 )))) & \_INTERNAL_.w3 ))));
    end
  end
  assign \_INTERNAL_.w3  = _INTERNAL_w3_reg;
  // register end

  // register begin
  reg  c$_INTERNAL_w5_0_reg = (1'b0);
  always @(posedge \$d(%,%) [1:1] or posedge \$d(%,%) [0:0]) begin : c$_INTERNAL_w5_0_register
    if (\$d(%,%) [0:0]) begin
      c$_INTERNAL_w5_0_reg <= (1'b0);
    end else begin
      c$_INTERNAL_w5_0_reg <= (~ ((~ (c$cout_app_arg_27 & \c$_INTERNAL_.w5_0 )) & (~ w15_0)));
    end
  end
  assign \c$_INTERNAL_.w5_0  = c$_INTERNAL_w5_0_reg;
  // register end

  assign c$cout_app_arg_28 = w12_2;

  assign c$w9_app_arg_2 = cin_12[(64'sd0)];

  always @(*) begin
    case(spiOutput[17:16])
      2'b10 : dt_93 = {1'b1,{4'd1,1'd1,dat}};
      default : dt_93 = {1'b0,13'bxxxxxxxxxxxxx};
    endcase
  end

  assign ds2 = spiOutput[15:0];

  assign cin_12 = {c$cin_app_arg_11,result_168};

  assign w12_2 = w11_3 & w8_2;

  assign c$cout_app_arg_29 = w17_0;

  assign w17_0 = w16_1 & w9_3;

  assign w11_3 = c$w11_app_arg_2 & c$w9_app_arg_2;

  assign c$cout_app_arg_30 = w18_0;

  always @(*) begin
    if(b_41)
      result_168 = 1'b1;
    else
      result_168 = 1'b0;
  end

  always @(*) begin
    if(startAcc)
      c$cin_app_arg_11 = 1'b1;
    else
      c$cin_app_arg_11 = 1'b0;
  end

  always @(*) begin
    case(spiOutput[17:16])
      2'b10 : dt_94 = {1'b1,{4'd2,1'd1,dat}};
      default : dt_94 = {1'b0,13'bxxxxxxxxxxxxx};
    endcase
  end

  assign w16_1 = \c$_INTERNAL_.w5_0  & c$w16_app_arg_0;

  assign w18_0 = w16_1 & w11_3;

  assign c$cout_app_arg_31 = w15_0;

  assign c$w11_app_arg_2 = ~ \_INTERNAL_.w3 ;

  always @(*) begin
    case(spiOutput[17:16])
      2'b00 : b_41 = 1'b0;
      default : b_41 = 1'b1;
    endcase
  end

  assign w15_0 = w14 & \_INTERNAL_.w3 ;

  assign c$cout_app_arg_32 = w19_0;

  assign \c$_INTERNAL_.w4_app_arg  = ~ w20_0;

  assign c$w16_app_arg_0 = ~ \c$_INTERNAL_.w4_0 ;

  always @(*) begin
    case(spiOutput[17:16])
      2'b10 : dt_95 = {1'b1,{4'd2,1'd0,dat}};
      default : dt_95 = {1'b0,13'bxxxxxxxxxxxxx};
    endcase
  end

  assign w20_0 = w6_0 & \_INTERNAL_.w3 ;

  assign w14 = (\c$_INTERNAL_.w4_0  & c$w9_app_arg_2) & c$w14_app_arg;

  assign w19_0 = w14 & c$w11_app_arg_2;

  assign w6_0 = c$w14_app_arg & c$w16_app_arg_0;

  assign c$w14_app_arg = ~ \c$_INTERNAL_.w5_0 ;

  assign \c$_INTERNAL_.w3_app_arg  = ~ w24;

  always @(*) begin
    case(spiOutput[17:16])
      2'b10 : dt_96 = {1'b1,{4'd1,1'd0,dat}};
      default : dt_96 = {1'b0,13'bxxxxxxxxxxxxx};
    endcase
  end

  assign w24 = c$w24_app_arg & (~ c$w9_app_arg_2);

  assign \c$_INTERNAL_.w3_app_arg_0  = cin_12[(64'sd1)];

  assign c$w24_app_arg = ~ w6_0;

  assign dat = ds2[7:0];

  assign w7_1 = c$w24_app_arg & c$w9_app_arg_2;

  assign result_169 = {result_170
                      ,result_171
                      ,result_172
                      ,result_173};

  assign result_170_selection_res = (bs_68[(64'sd0)]) == (1'b1);

  always @(*) begin
    if(result_170_selection_res)
      result_170 = c$o_regmanage_case_alt_13;
    else
      result_170 = c$o_regmanage_case_alt_14;
  end

  assign result_171_selection_res = (bs_69[(64'sd0)]) == (1'b1);

  always @(*) begin
    if(result_171_selection_res)
      result_171 = c$o_sensorType_case_alt_1;
    else
      result_171 = c$o_sensorType_case_alt_2;
  end

  assign result_172_selection_res = (bs_70[(64'sd0)]) == (1'b1);

  always @(*) begin
    if(result_172_selection_res)
      result_172 = c$o_sensorcontrol_case_alt_13;
    else
      result_172 = c$o_sensorcontrol_case_alt_14;
  end

  assign result_173_selection_res = (bs_71[(64'sd0)]) == (1'b1);

  always @(*) begin
    if(result_173_selection_res)
      result_173 = c$o_status_case_alt_3;
    else
      result_173 = c$o_status_case_alt_4;
  end

  assign c$vecflat_180 = {dt_97
                         ,{1'b0,13'bxxxxxxxxxxxxx}};

  // index begin
  wire [13:0] vec_187 [0:2-1];

  genvar i_189;
  generate
  for (i_189=0; i_189 < 2; i_189=i_189+1) begin : mk_array_187
    assign vec_187[(2-1)-i_189] = c$vecflat_180[i_189*14+:14];
  end
  endgenerate

  assign c$o_regmanage_case_alt_13 = vec_187[(64'sd1)];
  // index end

  assign c$vecflat_181 = {dt_97
                         ,{1'b0,13'bxxxxxxxxxxxxx}};

  // index begin
  wire [13:0] vec_188 [0:2-1];

  genvar i_190;
  generate
  for (i_190=0; i_190 < 2; i_190=i_190+1) begin : mk_array_188
    assign vec_188[(2-1)-i_190] = c$vecflat_181[i_190*14+:14];
  end
  endgenerate

  assign c$o_regmanage_case_alt_14 = vec_188[(64'sd0)];
  // index end

  assign c$vecflat_182 = {dt_98,2'd0,2'd1};

  // index begin
  wire [1:0] vec_189 [0:3-1];

  genvar i_191;
  generate
  for (i_191=0; i_191 < 3; i_191=i_191+1) begin : mk_array_189
    assign vec_189[(3-1)-i_191] = c$vecflat_182[i_191*2+:2];
  end
  endgenerate

  assign c$o_sensorType_case_alt_1 = vec_189[(64'sd2)];
  // index end

  assign c$o_sensorType_case_alt_2_selection_res = (bs_69[(64'sd1)]) == (1'b1);

  always @(*) begin
    if(c$o_sensorType_case_alt_2_selection_res)
      c$o_sensorType_case_alt_2 = c$o_sensorType_case_alt_3;
    else
      c$o_sensorType_case_alt_2 = c$o_sensorType_case_alt_4;
  end

  assign c$vecflat_183 = {dt_99
                         ,{2'b00,16'bxxxxxxxxxxxxxxxx}
                         ,{2'b01,{8'b00011111,8'b00111000}}
                         ,{2'b01,{8'b00100000,8'b00100000}}
                         ,{2'b01,{8'b00010000,8'b11001000}}
                         ,{2'b01,{8'b00011110,8'b00111000}}
                         ,{2'b01,{8'b00100000,8'b01011100}}
                         ,{2'b01,{8'b00100010,8'b10000000}}
                         ,{2'b01,{8'b00100011,8'b00001000}}};

  // index begin
  wire [17:0] vec_190 [0:9-1];

  genvar i_192;
  generate
  for (i_192=0; i_192 < 9; i_192=i_192+1) begin : mk_array_190
    assign vec_190[(9-1)-i_192] = c$vecflat_183[i_192*18+:18];
  end
  endgenerate

  assign c$o_sensorcontrol_case_alt_13 = vec_190[(64'sd8)];
  // index end

  assign c$o_sensorcontrol_case_alt_14_selection_res = (bs_70[(64'sd1)]) == (1'b1);

  always @(*) begin
    if(c$o_sensorcontrol_case_alt_14_selection_res)
      c$o_sensorcontrol_case_alt_14 = c$o_sensorcontrol_case_alt_15;
    else
      c$o_sensorcontrol_case_alt_14 = c$o_sensorcontrol_case_alt_16;
  end

  assign c$vecflat_184 = {dt_100,1'b0,1'b1};

  // index begin
  wire  vec_191 [0:3-1];

  genvar i_193;
  generate
  for (i_193=0; i_193 < 3; i_193=i_193+1) begin : mk_array_191
    assign vec_191[(3-1)-i_193] = c$vecflat_184[i_193*1+:1];
  end
  endgenerate

  assign c$o_status_case_alt_3 = vec_191[(64'sd2)];
  // index end

  assign c$o_status_case_alt_4_selection_res = (bs_71[(64'sd1)]) == (1'b1);

  always @(*) begin
    if(c$o_status_case_alt_4_selection_res)
      c$o_status_case_alt_4 = c$o_status_case_alt_5;
    else
      c$o_status_case_alt_4 = c$o_status_case_alt_6;
  end

  assign c$vecflat_185 = {dt_98,2'd0,2'd1};

  // index begin
  wire [1:0] vec_192 [0:3-1];

  genvar i_194;
  generate
  for (i_194=0; i_194 < 3; i_194=i_194+1) begin : mk_array_192
    assign vec_192[(3-1)-i_194] = c$vecflat_185[i_194*2+:2];
  end
  endgenerate

  assign c$o_sensorType_case_alt_3 = vec_192[(64'sd1)];
  // index end

  assign c$vecflat_186 = {dt_98,2'd0,2'd1};

  // index begin
  wire [1:0] vec_193 [0:3-1];

  genvar i_195;
  generate
  for (i_195=0; i_195 < 3; i_195=i_195+1) begin : mk_array_193
    assign vec_193[(3-1)-i_195] = c$vecflat_186[i_195*2+:2];
  end
  endgenerate

  assign c$o_sensorType_case_alt_4 = vec_193[(64'sd0)];
  // index end

  assign c$vecflat_187 = {dt_99
                         ,{2'b00,16'bxxxxxxxxxxxxxxxx}
                         ,{2'b01,{8'b00011111,8'b00111000}}
                         ,{2'b01,{8'b00100000,8'b00100000}}
                         ,{2'b01,{8'b00010000,8'b11001000}}
                         ,{2'b01,{8'b00011110,8'b00111000}}
                         ,{2'b01,{8'b00100000,8'b01011100}}
                         ,{2'b01,{8'b00100010,8'b10000000}}
                         ,{2'b01,{8'b00100011,8'b00001000}}};

  // index begin
  wire [17:0] vec_194 [0:9-1];

  genvar i_196;
  generate
  for (i_196=0; i_196 < 9; i_196=i_196+1) begin : mk_array_194
    assign vec_194[(9-1)-i_196] = c$vecflat_187[i_196*18+:18];
  end
  endgenerate

  assign c$o_sensorcontrol_case_alt_15 = vec_194[(64'sd7)];
  // index end

  assign c$o_sensorcontrol_case_alt_16_selection_res = (bs_70[(64'sd2)]) == (1'b1);

  always @(*) begin
    if(c$o_sensorcontrol_case_alt_16_selection_res)
      c$o_sensorcontrol_case_alt_16 = c$o_sensorcontrol_case_alt_17;
    else
      c$o_sensorcontrol_case_alt_16 = c$o_sensorcontrol_case_alt_18;
  end

  assign c$vecflat_188 = {dt_100,1'b0,1'b1};

  // index begin
  wire  vec_195 [0:3-1];

  genvar i_197;
  generate
  for (i_197=0; i_197 < 3; i_197=i_197+1) begin : mk_array_195
    assign vec_195[(3-1)-i_197] = c$vecflat_188[i_197*1+:1];
  end
  endgenerate

  assign c$o_status_case_alt_5 = vec_195[(64'sd1)];
  // index end

  assign c$vecflat_189 = {dt_100,1'b0,1'b1};

  // index begin
  wire  vec_196 [0:3-1];

  genvar i_198;
  generate
  for (i_198=0; i_198 < 3; i_198=i_198+1) begin : mk_array_196
    assign vec_196[(3-1)-i_198] = c$vecflat_189[i_198*1+:1];
  end
  endgenerate

  assign c$o_status_case_alt_6 = vec_196[(64'sd0)];
  // index end

  assign bs_68 = {((result_174[(64'sd0)])),((result_174[(64'sd1)]))};

  assign bs_69 = {((result_174[(64'sd2)])),({((result_174[(64'sd3)])),((result_174[(64'sd4)]))})};

  assign bs_70 = {((result_174[(64'sd5)])),({((result_174[(64'sd6)])),({((result_174[(64'sd7)])),({((result_174[(64'sd8)])),({((result_174[(64'sd9)])),({((result_174[(64'sd10)])),({((result_174[(64'sd11)])),({((result_174[(64'sd12)])),((result_174[(64'sd13)]))})})})})})})})};

  assign c$vecflat_190 = {dt_99
                         ,{2'b00,16'bxxxxxxxxxxxxxxxx}
                         ,{2'b01,{8'b00011111,8'b00111000}}
                         ,{2'b01,{8'b00100000,8'b00100000}}
                         ,{2'b01,{8'b00010000,8'b11001000}}
                         ,{2'b01,{8'b00011110,8'b00111000}}
                         ,{2'b01,{8'b00100000,8'b01011100}}
                         ,{2'b01,{8'b00100010,8'b10000000}}
                         ,{2'b01,{8'b00100011,8'b00001000}}};

  // index begin
  wire [17:0] vec_197 [0:9-1];

  genvar i_199;
  generate
  for (i_199=0; i_199 < 9; i_199=i_199+1) begin : mk_array_197
    assign vec_197[(9-1)-i_199] = c$vecflat_190[i_199*18+:18];
  end
  endgenerate

  assign c$o_sensorcontrol_case_alt_17 = vec_197[(64'sd6)];
  // index end

  assign c$o_sensorcontrol_case_alt_18_selection_res = (bs_70[(64'sd3)]) == (1'b1);

  always @(*) begin
    if(c$o_sensorcontrol_case_alt_18_selection_res)
      c$o_sensorcontrol_case_alt_18 = c$o_sensorcontrol_case_alt_19;
    else
      c$o_sensorcontrol_case_alt_18 = c$o_sensorcontrol_case_alt_20;
  end

  assign bs_71 = {((result_174[(64'sd14)])),({((result_174[(64'sd15)])),((result_174[(64'sd16)]))})};

  // register begin
  reg [13:0] dt_97_reg = {1'b0,13'bxxxxxxxxxxxxx};
  always @(posedge \$d(%,%) [1:1] or posedge \$d(%,%) [0:0]) begin : dt_97_register
    if (\$d(%,%) [0:0]) begin
      dt_97_reg <= {1'b0,13'bxxxxxxxxxxxxx};
    end else begin
      dt_97_reg <= result_170;
    end
  end
  assign dt_97 = dt_97_reg;
  // register end

  // register begin
  reg [1:0] dt_98_reg = 2'd3;
  always @(posedge \$d(%,%) [1:1] or posedge \$d(%,%) [0:0]) begin : dt_98_register
    if (\$d(%,%) [0:0]) begin
      dt_98_reg <= 2'd3;
    end else begin
      dt_98_reg <= result_171;
    end
  end
  assign dt_98 = dt_98_reg;
  // register end

  assign c$vecflat_191 = {dt_99
                         ,{2'b00,16'bxxxxxxxxxxxxxxxx}
                         ,{2'b01,{8'b00011111,8'b00111000}}
                         ,{2'b01,{8'b00100000,8'b00100000}}
                         ,{2'b01,{8'b00010000,8'b11001000}}
                         ,{2'b01,{8'b00011110,8'b00111000}}
                         ,{2'b01,{8'b00100000,8'b01011100}}
                         ,{2'b01,{8'b00100010,8'b10000000}}
                         ,{2'b01,{8'b00100011,8'b00001000}}};

  // index begin
  wire [17:0] vec_198 [0:9-1];

  genvar i_200;
  generate
  for (i_200=0; i_200 < 9; i_200=i_200+1) begin : mk_array_198
    assign vec_198[(9-1)-i_200] = c$vecflat_191[i_200*18+:18];
  end
  endgenerate

  assign c$o_sensorcontrol_case_alt_19 = vec_198[(64'sd5)];
  // index end

  assign c$o_sensorcontrol_case_alt_20_selection_res = (bs_70[(64'sd4)]) == (1'b1);

  always @(*) begin
    if(c$o_sensorcontrol_case_alt_20_selection_res)
      c$o_sensorcontrol_case_alt_20 = c$o_sensorcontrol_case_alt_21;
    else
      c$o_sensorcontrol_case_alt_20 = c$o_sensorcontrol_case_alt_22;
  end

  // register begin
  reg [17:0] dt_99_reg = {2'b00,16'bxxxxxxxxxxxxxxxx};
  always @(posedge \$d(%,%) [1:1] or posedge \$d(%,%) [0:0]) begin : dt_99_register
    if (\$d(%,%) [0:0]) begin
      dt_99_reg <= {2'b00,16'bxxxxxxxxxxxxxxxx};
    end else begin
      dt_99_reg <= result_172;
    end
  end
  assign dt_99 = dt_99_reg;
  // register end

  // register begin
  reg  dt_100_reg = 1'b0;
  always @(posedge \$d(%,%) [1:1] or posedge \$d(%,%) [0:0]) begin : dt_100_register
    if (\$d(%,%) [0:0]) begin
      dt_100_reg <= 1'b0;
    end else begin
      dt_100_reg <= result_173;
    end
  end
  assign dt_100 = dt_100_reg;
  // register end

  assign c$vecflat_192 = {dt_99
                         ,{2'b00,16'bxxxxxxxxxxxxxxxx}
                         ,{2'b01,{8'b00011111,8'b00111000}}
                         ,{2'b01,{8'b00100000,8'b00100000}}
                         ,{2'b01,{8'b00010000,8'b11001000}}
                         ,{2'b01,{8'b00011110,8'b00111000}}
                         ,{2'b01,{8'b00100000,8'b01011100}}
                         ,{2'b01,{8'b00100010,8'b10000000}}
                         ,{2'b01,{8'b00100011,8'b00001000}}};

  // index begin
  wire [17:0] vec_199 [0:9-1];

  genvar i_201;
  generate
  for (i_201=0; i_201 < 9; i_201=i_201+1) begin : mk_array_199
    assign vec_199[(9-1)-i_201] = c$vecflat_192[i_201*18+:18];
  end
  endgenerate

  assign c$o_sensorcontrol_case_alt_21 = vec_199[(64'sd4)];
  // index end

  assign c$o_sensorcontrol_case_alt_22_selection_res = (bs_70[(64'sd5)]) == (1'b1);

  always @(*) begin
    if(c$o_sensorcontrol_case_alt_22_selection_res)
      c$o_sensorcontrol_case_alt_22 = c$o_sensorcontrol_case_alt_23;
    else
      c$o_sensorcontrol_case_alt_22 = c$o_sensorcontrol_case_alt_24;
  end

  assign c$vecflat_193 = {dt_99
                         ,{2'b00,16'bxxxxxxxxxxxxxxxx}
                         ,{2'b01,{8'b00011111,8'b00111000}}
                         ,{2'b01,{8'b00100000,8'b00100000}}
                         ,{2'b01,{8'b00010000,8'b11001000}}
                         ,{2'b01,{8'b00011110,8'b00111000}}
                         ,{2'b01,{8'b00100000,8'b01011100}}
                         ,{2'b01,{8'b00100010,8'b10000000}}
                         ,{2'b01,{8'b00100011,8'b00001000}}};

  // index begin
  wire [17:0] vec_200 [0:9-1];

  genvar i_202;
  generate
  for (i_202=0; i_202 < 9; i_202=i_202+1) begin : mk_array_200
    assign vec_200[(9-1)-i_202] = c$vecflat_193[i_202*18+:18];
  end
  endgenerate

  assign c$o_sensorcontrol_case_alt_23 = vec_200[(64'sd3)];
  // index end

  assign c$o_sensorcontrol_case_alt_24_selection_res = (bs_70[(64'sd6)]) == (1'b1);

  always @(*) begin
    if(c$o_sensorcontrol_case_alt_24_selection_res)
      c$o_sensorcontrol_case_alt_24 = c$o_sensorcontrol_case_alt_25;
    else
      c$o_sensorcontrol_case_alt_24 = c$o_sensorcontrol_case_alt_26;
  end

  assign c$vecflat_194 = {dt_99
                         ,{2'b00,16'bxxxxxxxxxxxxxxxx}
                         ,{2'b01,{8'b00011111,8'b00111000}}
                         ,{2'b01,{8'b00100000,8'b00100000}}
                         ,{2'b01,{8'b00010000,8'b11001000}}
                         ,{2'b01,{8'b00011110,8'b00111000}}
                         ,{2'b01,{8'b00100000,8'b01011100}}
                         ,{2'b01,{8'b00100010,8'b10000000}}
                         ,{2'b01,{8'b00100011,8'b00001000}}};

  // index begin
  wire [17:0] vec_201 [0:9-1];

  genvar i_203;
  generate
  for (i_203=0; i_203 < 9; i_203=i_203+1) begin : mk_array_201
    assign vec_201[(9-1)-i_203] = c$vecflat_194[i_203*18+:18];
  end
  endgenerate

  assign c$o_sensorcontrol_case_alt_25 = vec_201[(64'sd2)];
  // index end

  assign c$o_sensorcontrol_case_alt_26_selection_res = (bs_70[(64'sd7)]) == (1'b1);

  always @(*) begin
    if(c$o_sensorcontrol_case_alt_26_selection_res)
      c$o_sensorcontrol_case_alt_26 = c$o_sensorcontrol_case_alt_27;
    else
      c$o_sensorcontrol_case_alt_26 = c$o_sensorcontrol_case_alt_28;
  end

  assign result_174 = {(w31),({(w32_1),({1'b0,({(w29_0),({((w27_1 & w21_0)),({((w23_1 & w13_2)),({((w21_0 & w13_2)),({(w24_0),({((w21_0 & w11_4)),({((w19_1 & \c$_INTERNAL_.w3_0 )),({((~ (\c$_INTERNAL_.w3_app_arg_1  & c$w9_app_arg_3))),({1'b0,({((w14_0 & c$w32_app_arg)),({((~ w14_0)),({1'b0,({(c$w32_app_arg),1'b0})})})})})})})})})})})})})})})};

  assign c$vecflat_195 = {dt_99
                         ,{2'b00,16'bxxxxxxxxxxxxxxxx}
                         ,{2'b01,{8'b00011111,8'b00111000}}
                         ,{2'b01,{8'b00100000,8'b00100000}}
                         ,{2'b01,{8'b00010000,8'b11001000}}
                         ,{2'b01,{8'b00011110,8'b00111000}}
                         ,{2'b01,{8'b00100000,8'b01011100}}
                         ,{2'b01,{8'b00100010,8'b10000000}}
                         ,{2'b01,{8'b00100011,8'b00001000}}};

  // index begin
  wire [17:0] vec_202 [0:9-1];

  genvar i_204;
  generate
  for (i_204=0; i_204 < 9; i_204=i_204+1) begin : mk_array_202
    assign vec_202[(9-1)-i_204] = c$vecflat_195[i_204*18+:18];
  end
  endgenerate

  assign c$o_sensorcontrol_case_alt_27 = vec_202[(64'sd1)];
  // index end

  assign c$vecflat_196 = {dt_99
                         ,{2'b00,16'bxxxxxxxxxxxxxxxx}
                         ,{2'b01,{8'b00011111,8'b00111000}}
                         ,{2'b01,{8'b00100000,8'b00100000}}
                         ,{2'b01,{8'b00010000,8'b11001000}}
                         ,{2'b01,{8'b00011110,8'b00111000}}
                         ,{2'b01,{8'b00100000,8'b01011100}}
                         ,{2'b01,{8'b00100010,8'b10000000}}
                         ,{2'b01,{8'b00100011,8'b00001000}}};

  // index begin
  wire [17:0] vec_203 [0:9-1];

  genvar i_205;
  generate
  for (i_205=0; i_205 < 9; i_205=i_205+1) begin : mk_array_203
    assign vec_203[(9-1)-i_205] = c$vecflat_196[i_205*18+:18];
  end
  endgenerate

  assign c$o_sensorcontrol_case_alt_28 = vec_203[(64'sd0)];
  // index end

  assign w31 = (w7_2 & \c$_INTERNAL_.w6_1 ) & w21_0;

  assign w21_0 = c$w21_app_arg_0 & c$w21_app_arg;

  assign w32_1 = (~ w31) & c$w32_app_arg;

  assign w7_2 = c$w7_app_arg_0 & c$w7_app_arg;

  // register begin
  reg  c$_INTERNAL_w6_1_reg = (1'b0);
  always @(posedge \$d(%,%) [1:1] or posedge \$d(%,%) [0:0]) begin : c$_INTERNAL_w6_1_register
    if (\$d(%,%) [0:0]) begin
      c$_INTERNAL_w6_1_reg <= (1'b0);
    end else begin
      c$_INTERNAL_w6_1_reg <= (~ ((~ (w32_1 & \c$_INTERNAL_.w6_1 )) & (~ w29_0)));
    end
  end
  assign \c$_INTERNAL_.w6_1  = c$_INTERNAL_w6_1_reg;
  // register end

  assign c$w32_app_arg = ~ w9_4;

  assign c$w21_app_arg = cin_13[(64'sd0)];

  assign c$w21_app_arg_0 = ~ \c$_INTERNAL_.w3_0 ;

  assign cin_13 = {c$cin_app_arg_12,result_175};

  assign w9_4 = c$w9_app_arg_3 & \c$_INTERNAL_.w6_1 ;

  assign w29_0 = w27_1 & w23_1;

  // register begin
  reg  c$_INTERNAL_w3_0_reg = (1'b0);
  always @(posedge \$d(%,%) [1:1] or posedge \$d(%,%) [0:0]) begin : c$_INTERNAL_w3_0_register
    if (\$d(%,%) [0:0]) begin
      c$_INTERNAL_w3_0_reg <= (1'b0);
    end else begin
      c$_INTERNAL_w3_0_reg <= ((~ (\c$_INTERNAL_.w3_app_arg_1  & \c$_INTERNAL_.w3_0 )) & (~ ((~ ((~ ((~ (w7_2 & (cin_13[(64'sd1)]))) & (~ w16_2))) & (~ ((~ w19_1) & \c$_INTERNAL_.w4_app_arg_0 )))) & c$w21_app_arg_0)));
    end
  end
  assign \c$_INTERNAL_.w3_0  = c$_INTERNAL_w3_0_reg;
  // register end

  assign c$w7_app_arg = ~ \c$_INTERNAL_.w4_1 ;

  assign c$w7_app_arg_0 = ~ \c$_INTERNAL_.w5_1 ;

  assign w23_1 = \c$_INTERNAL_.w3_0  & c$w21_app_arg;

  assign w27_1 = w10_4 & \c$_INTERNAL_.w5_1 ;

  // register begin
  reg  c$_INTERNAL_w4_1_reg = (1'b0);
  always @(posedge \$d(%,%) [1:1] or posedge \$d(%,%) [0:0]) begin : c$_INTERNAL_w4_1_register
    if (\$d(%,%) [0:0]) begin
      c$_INTERNAL_w4_1_reg <= (1'b0);
    end else begin
      c$_INTERNAL_w4_1_reg <= (w44 & (~ ((~ ((~ (\c$_INTERNAL_.w5_1  & \c$_INTERNAL_.w4_app_arg_0 )) & \c$_INTERNAL_.w3_0 )) & c$w7_app_arg)));
    end
  end
  assign \c$_INTERNAL_.w4_1  = c$_INTERNAL_w4_1_reg;
  // register end

  // register begin
  reg  c$_INTERNAL_w5_1_reg = (1'b0);
  always @(posedge \$d(%,%) [1:1] or posedge \$d(%,%) [0:0]) begin : c$_INTERNAL_w5_1_register
    if (\$d(%,%) [0:0]) begin
      c$_INTERNAL_w5_1_reg <= (1'b0);
    end else begin
      c$_INTERNAL_w5_1_reg <= (~ ((~ (w44 & \c$_INTERNAL_.w5_1 )) & (~ w24_0)));
    end
  end
  assign \c$_INTERNAL_.w5_1  = c$_INTERNAL_w5_1_reg;
  // register end

  assign c$w9_app_arg_3 = ~ w8_3;

  always @(*) begin
    if(b_42)
      result_175 = 1'b1;
    else
      result_175 = 1'b0;
  end

  always @(*) begin
    if(startInit)
      c$cin_app_arg_12 = 1'b1;
    else
      c$cin_app_arg_12 = 1'b0;
  end

  assign w8_3 = w7_2 & c$w21_app_arg_0;

  assign w10_4 = c$w10_app_arg & \c$_INTERNAL_.w4_1 ;

  always @(*) begin
    case(spiOutput[17:16])
      2'b00 : b_42 = 1'b0;
      default : b_42 = 1'b1;
    endcase
  end

  assign w44 = (~ (w23_1 & \c$_INTERNAL_.w4_1 )) & c$w10_app_arg;

  assign w13_2 = (\c$_INTERNAL_.w5_1  & c$w7_app_arg) & c$w10_app_arg;

  assign c$w10_app_arg = ~ \c$_INTERNAL_.w6_1 ;

  assign w24_0 = w23_1 & w11_4;

  assign \c$_INTERNAL_.w3_app_arg_1  = ~ w17_1;

  assign w17_1 = w16_2 & \c$_INTERNAL_.w4_app_arg_0 ;

  assign w11_4 = w10_4 & c$w7_app_arg_0;

  assign w16_2 = (~ w7_2) & c$w10_app_arg;

  assign w19_1 = w7_2 & c$w10_app_arg;

  assign \c$_INTERNAL_.w4_app_arg_0  = ~ c$w21_app_arg;

  assign w14_0 = (~ w13_2) & (~ w11_4);

  assign result_176 = {result_177
                      ,result_178
                      ,result_179
                      ,result_180};

  assign result_177_selection_res = (bs_72[(64'sd0)]) == (1'b1);

  always @(*) begin
    if(result_177_selection_res)
      result_177 = c$o_regmanage_case_alt_15;
    else
      result_177 = c$o_regmanage_case_alt_16;
  end

  assign result_178_selection_res = (bs_73[(64'sd0)]) == (1'b1);

  always @(*) begin
    if(result_178_selection_res)
      result_178 = c$o_sensorType_case_alt_5;
    else
      result_178 = c$o_sensorType_case_alt_6;
  end

  assign result_179_selection_res = (bs_74[(64'sd0)]) == (1'b1);

  always @(*) begin
    if(result_179_selection_res)
      result_179 = c$o_sensorcontrol_case_alt_29;
    else
      result_179 = c$o_sensorcontrol_case_alt_30;
  end

  assign result_180_selection_res = (bs_75[(64'sd0)]) == (1'b1);

  always @(*) begin
    if(result_180_selection_res)
      result_180 = c$o_status_case_alt_7;
    else
      result_180 = c$o_status_case_alt_8;
  end

  assign c$vecflat_197 = {dt_101
                         ,{1'b0,13'bxxxxxxxxxxxxx}
                         ,dt_105
                         ,dt_106
                         ,dt_107
                         ,dt_108
                         ,dt_109
                         ,dt_110};

  // index begin
  wire [13:0] vec_204 [0:8-1];

  genvar i_206;
  generate
  for (i_206=0; i_206 < 8; i_206=i_206+1) begin : mk_array_204
    assign vec_204[(8-1)-i_206] = c$vecflat_197[i_206*14+:14];
  end
  endgenerate

  assign c$o_regmanage_case_alt_15 = vec_204[(64'sd7)];
  // index end

  assign c$o_regmanage_case_alt_16_selection_res = (bs_72[(64'sd1)]) == (1'b1);

  always @(*) begin
    if(c$o_regmanage_case_alt_16_selection_res)
      c$o_regmanage_case_alt_16 = c$o_regmanage_case_alt_17;
    else
      c$o_regmanage_case_alt_16 = c$o_regmanage_case_alt_18;
  end

  assign c$vecflat_198 = {dt_102,2'd1};

  // index begin
  wire [1:0] vec_205 [0:2-1];

  genvar i_207;
  generate
  for (i_207=0; i_207 < 2; i_207=i_207+1) begin : mk_array_205
    assign vec_205[(2-1)-i_207] = c$vecflat_198[i_207*2+:2];
  end
  endgenerate

  assign c$o_sensorType_case_alt_5 = vec_205[(64'sd1)];
  // index end

  assign c$vecflat_199 = {dt_102,2'd1};

  // index begin
  wire [1:0] vec_206 [0:2-1];

  genvar i_208;
  generate
  for (i_208=0; i_208 < 2; i_208=i_208+1) begin : mk_array_206
    assign vec_206[(2-1)-i_208] = c$vecflat_199[i_208*2+:2];
  end
  endgenerate

  assign c$o_sensorType_case_alt_6 = vec_206[(64'sd0)];
  // index end

  assign c$vecflat_200 = {dt_103
                         ,{2'b00,16'bxxxxxxxxxxxxxxxx}
                         ,{2'b10,8'b01101000,8'bxxxxxxxx}
                         ,{2'b10,8'b01101001,8'bxxxxxxxx}
                         ,{2'b10,8'b01101010,8'bxxxxxxxx}
                         ,{2'b10,8'b01101011,8'bxxxxxxxx}
                         ,{2'b10,8'b01101100,8'bxxxxxxxx}
                         ,{2'b10,8'b01101101,8'bxxxxxxxx}};

  // index begin
  wire [17:0] vec_207 [0:8-1];

  genvar i_209;
  generate
  for (i_209=0; i_209 < 8; i_209=i_209+1) begin : mk_array_207
    assign vec_207[(8-1)-i_209] = c$vecflat_200[i_209*18+:18];
  end
  endgenerate

  assign c$o_sensorcontrol_case_alt_29 = vec_207[(64'sd7)];
  // index end

  assign c$o_sensorcontrol_case_alt_30_selection_res = (bs_74[(64'sd1)]) == (1'b1);

  always @(*) begin
    if(c$o_sensorcontrol_case_alt_30_selection_res)
      c$o_sensorcontrol_case_alt_30 = c$o_sensorcontrol_case_alt_31;
    else
      c$o_sensorcontrol_case_alt_30 = c$o_sensorcontrol_case_alt_32;
  end

  assign c$vecflat_201 = {dt_104,1'b0,1'b1};

  // index begin
  wire  vec_208 [0:3-1];

  genvar i_210;
  generate
  for (i_210=0; i_210 < 3; i_210=i_210+1) begin : mk_array_208
    assign vec_208[(3-1)-i_210] = c$vecflat_201[i_210*1+:1];
  end
  endgenerate

  assign c$o_status_case_alt_7 = vec_208[(64'sd2)];
  // index end

  assign c$o_status_case_alt_8_selection_res = (bs_75[(64'sd1)]) == (1'b1);

  always @(*) begin
    if(c$o_status_case_alt_8_selection_res)
      c$o_status_case_alt_8 = c$o_status_case_alt_9;
    else
      c$o_status_case_alt_8 = c$o_status_case_alt_10;
  end

  assign c$vecflat_202 = {dt_101
                         ,{1'b0,13'bxxxxxxxxxxxxx}
                         ,dt_105
                         ,dt_106
                         ,dt_107
                         ,dt_108
                         ,dt_109
                         ,dt_110};

  // index begin
  wire [13:0] vec_209 [0:8-1];

  genvar i_211;
  generate
  for (i_211=0; i_211 < 8; i_211=i_211+1) begin : mk_array_209
    assign vec_209[(8-1)-i_211] = c$vecflat_202[i_211*14+:14];
  end
  endgenerate

  assign c$o_regmanage_case_alt_17 = vec_209[(64'sd6)];
  // index end

  assign c$o_regmanage_case_alt_18_selection_res = (bs_72[(64'sd2)]) == (1'b1);

  always @(*) begin
    if(c$o_regmanage_case_alt_18_selection_res)
      c$o_regmanage_case_alt_18 = c$o_regmanage_case_alt_19;
    else
      c$o_regmanage_case_alt_18 = c$o_regmanage_case_alt_20;
  end

  assign c$vecflat_203 = {dt_103
                         ,{2'b00,16'bxxxxxxxxxxxxxxxx}
                         ,{2'b10,8'b01101000,8'bxxxxxxxx}
                         ,{2'b10,8'b01101001,8'bxxxxxxxx}
                         ,{2'b10,8'b01101010,8'bxxxxxxxx}
                         ,{2'b10,8'b01101011,8'bxxxxxxxx}
                         ,{2'b10,8'b01101100,8'bxxxxxxxx}
                         ,{2'b10,8'b01101101,8'bxxxxxxxx}};

  // index begin
  wire [17:0] vec_210 [0:8-1];

  genvar i_212;
  generate
  for (i_212=0; i_212 < 8; i_212=i_212+1) begin : mk_array_210
    assign vec_210[(8-1)-i_212] = c$vecflat_203[i_212*18+:18];
  end
  endgenerate

  assign c$o_sensorcontrol_case_alt_31 = vec_210[(64'sd6)];
  // index end

  assign c$o_sensorcontrol_case_alt_32_selection_res = (bs_74[(64'sd2)]) == (1'b1);

  always @(*) begin
    if(c$o_sensorcontrol_case_alt_32_selection_res)
      c$o_sensorcontrol_case_alt_32 = c$o_sensorcontrol_case_alt_33;
    else
      c$o_sensorcontrol_case_alt_32 = c$o_sensorcontrol_case_alt_34;
  end

  assign c$vecflat_204 = {dt_104,1'b0,1'b1};

  // index begin
  wire  vec_211 [0:3-1];

  genvar i_213;
  generate
  for (i_213=0; i_213 < 3; i_213=i_213+1) begin : mk_array_211
    assign vec_211[(3-1)-i_213] = c$vecflat_204[i_213*1+:1];
  end
  endgenerate

  assign c$o_status_case_alt_9 = vec_211[(64'sd1)];
  // index end

  assign c$vecflat_205 = {dt_104,1'b0,1'b1};

  // index begin
  wire  vec_212 [0:3-1];

  genvar i_214;
  generate
  for (i_214=0; i_214 < 3; i_214=i_214+1) begin : mk_array_212
    assign vec_212[(3-1)-i_214] = c$vecflat_205[i_214*1+:1];
  end
  endgenerate

  assign c$o_status_case_alt_10 = vec_212[(64'sd0)];
  // index end

  assign bs_72 = {((result_181[(64'sd0)])),({((result_181[(64'sd1)])),({((result_181[(64'sd2)])),({((result_181[(64'sd3)])),({((result_181[(64'sd4)])),({((result_181[(64'sd5)])),({((result_181[(64'sd6)])),((result_181[(64'sd7)]))})})})})})})};

  assign c$vecflat_206 = {dt_101
                         ,{1'b0,13'bxxxxxxxxxxxxx}
                         ,dt_105
                         ,dt_106
                         ,dt_107
                         ,dt_108
                         ,dt_109
                         ,dt_110};

  // index begin
  wire [13:0] vec_213 [0:8-1];

  genvar i_215;
  generate
  for (i_215=0; i_215 < 8; i_215=i_215+1) begin : mk_array_213
    assign vec_213[(8-1)-i_215] = c$vecflat_206[i_215*14+:14];
  end
  endgenerate

  assign c$o_regmanage_case_alt_19 = vec_213[(64'sd5)];
  // index end

  assign c$o_regmanage_case_alt_20_selection_res = (bs_72[(64'sd3)]) == (1'b1);

  always @(*) begin
    if(c$o_regmanage_case_alt_20_selection_res)
      c$o_regmanage_case_alt_20 = c$o_regmanage_case_alt_21;
    else
      c$o_regmanage_case_alt_20 = c$o_regmanage_case_alt_22;
  end

  assign bs_73 = {((result_181[(64'sd8)])),((result_181[(64'sd9)]))};

  assign bs_74 = {((result_181[(64'sd10)])),({((result_181[(64'sd11)])),({((result_181[(64'sd12)])),({((result_181[(64'sd13)])),({((result_181[(64'sd14)])),({((result_181[(64'sd15)])),({((result_181[(64'sd16)])),((result_181[(64'sd17)]))})})})})})})};

  assign c$vecflat_207 = {dt_103
                         ,{2'b00,16'bxxxxxxxxxxxxxxxx}
                         ,{2'b10,8'b01101000,8'bxxxxxxxx}
                         ,{2'b10,8'b01101001,8'bxxxxxxxx}
                         ,{2'b10,8'b01101010,8'bxxxxxxxx}
                         ,{2'b10,8'b01101011,8'bxxxxxxxx}
                         ,{2'b10,8'b01101100,8'bxxxxxxxx}
                         ,{2'b10,8'b01101101,8'bxxxxxxxx}};

  // index begin
  wire [17:0] vec_214 [0:8-1];

  genvar i_216;
  generate
  for (i_216=0; i_216 < 8; i_216=i_216+1) begin : mk_array_214
    assign vec_214[(8-1)-i_216] = c$vecflat_207[i_216*18+:18];
  end
  endgenerate

  assign c$o_sensorcontrol_case_alt_33 = vec_214[(64'sd5)];
  // index end

  assign c$o_sensorcontrol_case_alt_34_selection_res = (bs_74[(64'sd3)]) == (1'b1);

  always @(*) begin
    if(c$o_sensorcontrol_case_alt_34_selection_res)
      c$o_sensorcontrol_case_alt_34 = c$o_sensorcontrol_case_alt_35;
    else
      c$o_sensorcontrol_case_alt_34 = c$o_sensorcontrol_case_alt_36;
  end

  assign bs_75 = {((result_181[(64'sd18)])),({((result_181[(64'sd19)])),((result_181[(64'sd20)]))})};

  assign c$vecflat_208 = {dt_101
                         ,{1'b0,13'bxxxxxxxxxxxxx}
                         ,dt_105
                         ,dt_106
                         ,dt_107
                         ,dt_108
                         ,dt_109
                         ,dt_110};

  // index begin
  wire [13:0] vec_215 [0:8-1];

  genvar i_217;
  generate
  for (i_217=0; i_217 < 8; i_217=i_217+1) begin : mk_array_215
    assign vec_215[(8-1)-i_217] = c$vecflat_208[i_217*14+:14];
  end
  endgenerate

  assign c$o_regmanage_case_alt_21 = vec_215[(64'sd4)];
  // index end

  assign c$o_regmanage_case_alt_22_selection_res = (bs_72[(64'sd4)]) == (1'b1);

  always @(*) begin
    if(c$o_regmanage_case_alt_22_selection_res)
      c$o_regmanage_case_alt_22 = c$o_regmanage_case_alt_23;
    else
      c$o_regmanage_case_alt_22 = c$o_regmanage_case_alt_24;
  end

  // register begin
  reg [13:0] dt_101_reg = {1'b0,13'bxxxxxxxxxxxxx};
  always @(posedge \$d(%,%) [1:1] or posedge \$d(%,%) [0:0]) begin : dt_101_register
    if (\$d(%,%) [0:0]) begin
      dt_101_reg <= {1'b0,13'bxxxxxxxxxxxxx};
    end else begin
      dt_101_reg <= result_177;
    end
  end
  assign dt_101 = dt_101_reg;
  // register end

  // register begin
  reg [1:0] dt_102_reg = 2'd3;
  always @(posedge \$d(%,%) [1:1] or posedge \$d(%,%) [0:0]) begin : dt_102_register
    if (\$d(%,%) [0:0]) begin
      dt_102_reg <= 2'd3;
    end else begin
      dt_102_reg <= result_178;
    end
  end
  assign dt_102 = dt_102_reg;
  // register end

  assign c$vecflat_209 = {dt_103
                         ,{2'b00,16'bxxxxxxxxxxxxxxxx}
                         ,{2'b10,8'b01101000,8'bxxxxxxxx}
                         ,{2'b10,8'b01101001,8'bxxxxxxxx}
                         ,{2'b10,8'b01101010,8'bxxxxxxxx}
                         ,{2'b10,8'b01101011,8'bxxxxxxxx}
                         ,{2'b10,8'b01101100,8'bxxxxxxxx}
                         ,{2'b10,8'b01101101,8'bxxxxxxxx}};

  // index begin
  wire [17:0] vec_216 [0:8-1];

  genvar i_218;
  generate
  for (i_218=0; i_218 < 8; i_218=i_218+1) begin : mk_array_216
    assign vec_216[(8-1)-i_218] = c$vecflat_209[i_218*18+:18];
  end
  endgenerate

  assign c$o_sensorcontrol_case_alt_35 = vec_216[(64'sd4)];
  // index end

  assign c$o_sensorcontrol_case_alt_36_selection_res = (bs_74[(64'sd4)]) == (1'b1);

  always @(*) begin
    if(c$o_sensorcontrol_case_alt_36_selection_res)
      c$o_sensorcontrol_case_alt_36 = c$o_sensorcontrol_case_alt_37;
    else
      c$o_sensorcontrol_case_alt_36 = c$o_sensorcontrol_case_alt_38;
  end

  // register begin
  reg [17:0] dt_103_reg = {2'b00,16'bxxxxxxxxxxxxxxxx};
  always @(posedge \$d(%,%) [1:1] or posedge \$d(%,%) [0:0]) begin : dt_103_register
    if (\$d(%,%) [0:0]) begin
      dt_103_reg <= {2'b00,16'bxxxxxxxxxxxxxxxx};
    end else begin
      dt_103_reg <= result_179;
    end
  end
  assign dt_103 = dt_103_reg;
  // register end

  // register begin
  reg  dt_104_reg = 1'b0;
  always @(posedge \$d(%,%) [1:1] or posedge \$d(%,%) [0:0]) begin : dt_104_register
    if (\$d(%,%) [0:0]) begin
      dt_104_reg <= 1'b0;
    end else begin
      dt_104_reg <= result_180;
    end
  end
  assign dt_104 = dt_104_reg;
  // register end

  assign c$vecflat_210 = {dt_101
                         ,{1'b0,13'bxxxxxxxxxxxxx}
                         ,dt_105
                         ,dt_106
                         ,dt_107
                         ,dt_108
                         ,dt_109
                         ,dt_110};

  // index begin
  wire [13:0] vec_217 [0:8-1];

  genvar i_219;
  generate
  for (i_219=0; i_219 < 8; i_219=i_219+1) begin : mk_array_217
    assign vec_217[(8-1)-i_219] = c$vecflat_210[i_219*14+:14];
  end
  endgenerate

  assign c$o_regmanage_case_alt_23 = vec_217[(64'sd3)];
  // index end

  assign c$o_regmanage_case_alt_24_selection_res = (bs_72[(64'sd5)]) == (1'b1);

  always @(*) begin
    if(c$o_regmanage_case_alt_24_selection_res)
      c$o_regmanage_case_alt_24 = c$o_regmanage_case_alt_25;
    else
      c$o_regmanage_case_alt_24 = c$o_regmanage_case_alt_26;
  end

  assign c$vecflat_211 = {dt_103
                         ,{2'b00,16'bxxxxxxxxxxxxxxxx}
                         ,{2'b10,8'b01101000,8'bxxxxxxxx}
                         ,{2'b10,8'b01101001,8'bxxxxxxxx}
                         ,{2'b10,8'b01101010,8'bxxxxxxxx}
                         ,{2'b10,8'b01101011,8'bxxxxxxxx}
                         ,{2'b10,8'b01101100,8'bxxxxxxxx}
                         ,{2'b10,8'b01101101,8'bxxxxxxxx}};

  // index begin
  wire [17:0] vec_218 [0:8-1];

  genvar i_220;
  generate
  for (i_220=0; i_220 < 8; i_220=i_220+1) begin : mk_array_218
    assign vec_218[(8-1)-i_220] = c$vecflat_211[i_220*18+:18];
  end
  endgenerate

  assign c$o_sensorcontrol_case_alt_37 = vec_218[(64'sd3)];
  // index end

  assign c$o_sensorcontrol_case_alt_38_selection_res = (bs_74[(64'sd5)]) == (1'b1);

  always @(*) begin
    if(c$o_sensorcontrol_case_alt_38_selection_res)
      c$o_sensorcontrol_case_alt_38 = c$o_sensorcontrol_case_alt_39;
    else
      c$o_sensorcontrol_case_alt_38 = c$o_sensorcontrol_case_alt_40;
  end

  assign c$vecflat_212 = {dt_101
                         ,{1'b0,13'bxxxxxxxxxxxxx}
                         ,dt_105
                         ,dt_106
                         ,dt_107
                         ,dt_108
                         ,dt_109
                         ,dt_110};

  // index begin
  wire [13:0] vec_219 [0:8-1];

  genvar i_221;
  generate
  for (i_221=0; i_221 < 8; i_221=i_221+1) begin : mk_array_219
    assign vec_219[(8-1)-i_221] = c$vecflat_212[i_221*14+:14];
  end
  endgenerate

  assign c$o_regmanage_case_alt_25 = vec_219[(64'sd2)];
  // index end

  assign c$o_regmanage_case_alt_26_selection_res = (bs_72[(64'sd6)]) == (1'b1);

  always @(*) begin
    if(c$o_regmanage_case_alt_26_selection_res)
      c$o_regmanage_case_alt_26 = c$o_regmanage_case_alt_27;
    else
      c$o_regmanage_case_alt_26 = c$o_regmanage_case_alt_28;
  end

  assign c$vecflat_213 = {dt_103
                         ,{2'b00,16'bxxxxxxxxxxxxxxxx}
                         ,{2'b10,8'b01101000,8'bxxxxxxxx}
                         ,{2'b10,8'b01101001,8'bxxxxxxxx}
                         ,{2'b10,8'b01101010,8'bxxxxxxxx}
                         ,{2'b10,8'b01101011,8'bxxxxxxxx}
                         ,{2'b10,8'b01101100,8'bxxxxxxxx}
                         ,{2'b10,8'b01101101,8'bxxxxxxxx}};

  // index begin
  wire [17:0] vec_220 [0:8-1];

  genvar i_222;
  generate
  for (i_222=0; i_222 < 8; i_222=i_222+1) begin : mk_array_220
    assign vec_220[(8-1)-i_222] = c$vecflat_213[i_222*18+:18];
  end
  endgenerate

  assign c$o_sensorcontrol_case_alt_39 = vec_220[(64'sd2)];
  // index end

  assign c$o_sensorcontrol_case_alt_40_selection_res = (bs_74[(64'sd6)]) == (1'b1);

  always @(*) begin
    if(c$o_sensorcontrol_case_alt_40_selection_res)
      c$o_sensorcontrol_case_alt_40 = c$o_sensorcontrol_case_alt_41;
    else
      c$o_sensorcontrol_case_alt_40 = c$o_sensorcontrol_case_alt_42;
  end

  assign c$vecflat_214 = {dt_101
                         ,{1'b0,13'bxxxxxxxxxxxxx}
                         ,dt_105
                         ,dt_106
                         ,dt_107
                         ,dt_108
                         ,dt_109
                         ,dt_110};

  // index begin
  wire [13:0] vec_221 [0:8-1];

  genvar i_223;
  generate
  for (i_223=0; i_223 < 8; i_223=i_223+1) begin : mk_array_221
    assign vec_221[(8-1)-i_223] = c$vecflat_214[i_223*14+:14];
  end
  endgenerate

  assign c$o_regmanage_case_alt_27 = vec_221[(64'sd1)];
  // index end

  assign c$vecflat_215 = {dt_101
                         ,{1'b0,13'bxxxxxxxxxxxxx}
                         ,dt_105
                         ,dt_106
                         ,dt_107
                         ,dt_108
                         ,dt_109
                         ,dt_110};

  // index begin
  wire [13:0] vec_222 [0:8-1];

  genvar i_224;
  generate
  for (i_224=0; i_224 < 8; i_224=i_224+1) begin : mk_array_222
    assign vec_222[(8-1)-i_224] = c$vecflat_215[i_224*14+:14];
  end
  endgenerate

  assign c$o_regmanage_case_alt_28 = vec_222[(64'sd0)];
  // index end

  assign c$vecflat_216 = {dt_103
                         ,{2'b00,16'bxxxxxxxxxxxxxxxx}
                         ,{2'b10,8'b01101000,8'bxxxxxxxx}
                         ,{2'b10,8'b01101001,8'bxxxxxxxx}
                         ,{2'b10,8'b01101010,8'bxxxxxxxx}
                         ,{2'b10,8'b01101011,8'bxxxxxxxx}
                         ,{2'b10,8'b01101100,8'bxxxxxxxx}
                         ,{2'b10,8'b01101101,8'bxxxxxxxx}};

  // index begin
  wire [17:0] vec_223 [0:8-1];

  genvar i_225;
  generate
  for (i_225=0; i_225 < 8; i_225=i_225+1) begin : mk_array_223
    assign vec_223[(8-1)-i_225] = c$vecflat_216[i_225*18+:18];
  end
  endgenerate

  assign c$o_sensorcontrol_case_alt_41 = vec_223[(64'sd1)];
  // index end

  assign c$vecflat_217 = {dt_103
                         ,{2'b00,16'bxxxxxxxxxxxxxxxx}
                         ,{2'b10,8'b01101000,8'bxxxxxxxx}
                         ,{2'b10,8'b01101001,8'bxxxxxxxx}
                         ,{2'b10,8'b01101010,8'bxxxxxxxx}
                         ,{2'b10,8'b01101011,8'bxxxxxxxx}
                         ,{2'b10,8'b01101100,8'bxxxxxxxx}
                         ,{2'b10,8'b01101101,8'bxxxxxxxx}};

  // index begin
  wire [17:0] vec_224 [0:8-1];

  genvar i_226;
  generate
  for (i_226=0; i_226 < 8; i_226=i_226+1) begin : mk_array_224
    assign vec_224[(8-1)-i_226] = c$vecflat_217[i_226*18+:18];
  end
  endgenerate

  assign c$o_sensorcontrol_case_alt_42 = vec_224[(64'sd0)];
  // index end

  assign result_181 = {c$cout_app_arg_33,({(c$cout_app_arg_34),({1'b0,({c$cout_app_arg_35,({c$cout_app_arg_36,({c$cout_app_arg_37,({c$cout_app_arg_38,({c$cout_app_arg_39,({(w20_1),({(((~ (c$cout_app_arg_34 & w7_3)) & \c$_INTERNAL_.w4_app_arg_1 )),({1'b0,({1'b1,({1'b0,({c$cout_app_arg_39,({c$cout_app_arg_37,({c$cout_app_arg_36,({c$cout_app_arg_38,({c$cout_app_arg_35,({c$cout_app_arg_33,({((~ w7_3)),1'b0})})})})})})})})})})})})})})})})})})})};

  always @(*) begin
    case(spiOutput[17:16])
      2'b10 : dt_105 = {1'b1,{4'd9,1'd1,dat_0}};
      default : dt_105 = {1'b0,13'bxxxxxxxxxxxxx};
    endcase
  end

  assign c$cout_app_arg_33 = w10_5;

  assign w10_5 = w9_5 & w8_4;

  always @(*) begin
    case(spiOutput[17:16])
      2'b10 : dt_106 = {1'b1,{4'd9,1'd0,dat_0}};
      default : dt_106 = {1'b0,13'bxxxxxxxxxxxxx};
    endcase
  end

  assign w9_5 = \c$_INTERNAL_.w3_1  & c$w9_app_arg_4;

  assign w8_4 = \c$_INTERNAL_.w5_2  & \c$_INTERNAL_.w4_2 ;

  assign c$cout_app_arg_34 = ~ w10_5;

  // register begin
  reg  c$_INTERNAL_w4_2_reg = (1'b0);
  always @(posedge \$d(%,%) [1:1] or posedge \$d(%,%) [0:0]) begin : c$_INTERNAL_w4_2_register
    if (\$d(%,%) [0:0]) begin
      c$_INTERNAL_w4_2_reg <= (1'b0);
    end else begin
      c$_INTERNAL_w4_2_reg <= (~ ((\c$_INTERNAL_.w4_app_arg_1  & (~ w17_2)) & (~ ((~ w9_5) & \c$_INTERNAL_.w4_2 ))));
    end
  end
  assign \c$_INTERNAL_.w4_2  = c$_INTERNAL_w4_2_reg;
  // register end

  // register begin
  reg  c$_INTERNAL_w3_1_reg = (1'b0);
  always @(posedge \$d(%,%) [1:1] or posedge \$d(%,%) [0:0]) begin : c$_INTERNAL_w3_1_register
    if (\$d(%,%) [0:0]) begin
      c$_INTERNAL_w3_1_reg <= (1'b0);
    end else begin
      c$_INTERNAL_w3_1_reg <= (~ ((~ ((\c$_INTERNAL_.w3_app_arg_2  & c$w11_app_arg_3) & (~ (w6_1 & (~ \c$_INTERNAL_.w3_app_arg_3 ))))) & (~ ((~ (\c$_INTERNAL_.w3_app_arg_2  & (~ (w8_4 & \c$_INTERNAL_.w3_app_arg_3 )))) & \c$_INTERNAL_.w3_1 ))));
    end
  end
  assign \c$_INTERNAL_.w3_1  = c$_INTERNAL_w3_1_reg;
  // register end

  // register begin
  reg  c$_INTERNAL_w5_2_reg = (1'b0);
  always @(posedge \$d(%,%) [1:1] or posedge \$d(%,%) [0:0]) begin : c$_INTERNAL_w5_2_register
    if (\$d(%,%) [0:0]) begin
      c$_INTERNAL_w5_2_reg <= (1'b0);
    end else begin
      c$_INTERNAL_w5_2_reg <= (~ ((~ (c$cout_app_arg_34 & \c$_INTERNAL_.w5_2 )) & (~ w15_1)));
    end
  end
  assign \c$_INTERNAL_.w5_2  = c$_INTERNAL_w5_2_reg;
  // register end

  assign c$cout_app_arg_35 = w12_3;

  assign c$w9_app_arg_4 = cin_14[(64'sd0)];

  always @(*) begin
    case(spiOutput[17:16])
      2'b10 : dt_107 = {1'b1,{4'd7,1'd1,dat_0}};
      default : dt_107 = {1'b0,13'bxxxxxxxxxxxxx};
    endcase
  end

  assign ds2_0 = spiOutput[15:0];

  assign cin_14 = {c$cin_app_arg_13,result_182};

  assign w12_3 = w11_5 & w8_4;

  assign c$cout_app_arg_36 = w17_2;

  assign w17_2 = w16_3 & w9_5;

  assign w11_5 = c$w11_app_arg_3 & c$w9_app_arg_4;

  assign c$cout_app_arg_37 = w18_1;

  always @(*) begin
    if(b_43)
      result_182 = 1'b1;
    else
      result_182 = 1'b0;
  end

  always @(*) begin
    if(startMag)
      c$cin_app_arg_13 = 1'b1;
    else
      c$cin_app_arg_13 = 1'b0;
  end

  always @(*) begin
    case(spiOutput[17:16])
      2'b10 : dt_108 = {1'b1,{4'd8,1'd1,dat_0}};
      default : dt_108 = {1'b0,13'bxxxxxxxxxxxxx};
    endcase
  end

  assign w16_3 = \c$_INTERNAL_.w5_2  & c$w16_app_arg_1;

  assign w18_1 = w16_3 & w11_5;

  assign c$cout_app_arg_38 = w15_1;

  assign c$w11_app_arg_3 = ~ \c$_INTERNAL_.w3_1 ;

  always @(*) begin
    case(spiOutput[17:16])
      2'b00 : b_43 = 1'b0;
      default : b_43 = 1'b1;
    endcase
  end

  assign w15_1 = w14_1 & \c$_INTERNAL_.w3_1 ;

  assign c$cout_app_arg_39 = w19_2;

  assign \c$_INTERNAL_.w4_app_arg_1  = ~ w20_1;

  assign c$w16_app_arg_1 = ~ \c$_INTERNAL_.w4_2 ;

  always @(*) begin
    case(spiOutput[17:16])
      2'b10 : dt_109 = {1'b1,{4'd8,1'd0,dat_0}};
      default : dt_109 = {1'b0,13'bxxxxxxxxxxxxx};
    endcase
  end

  assign w20_1 = w6_1 & \c$_INTERNAL_.w3_1 ;

  assign w14_1 = (\c$_INTERNAL_.w4_2  & c$w9_app_arg_4) & c$w14_app_arg_0;

  assign w19_2 = w14_1 & c$w11_app_arg_3;

  assign w6_1 = c$w14_app_arg_0 & c$w16_app_arg_1;

  assign c$w14_app_arg_0 = ~ \c$_INTERNAL_.w5_2 ;

  assign \c$_INTERNAL_.w3_app_arg_2  = ~ w24_1;

  always @(*) begin
    case(spiOutput[17:16])
      2'b10 : dt_110 = {1'b1,{4'd7,1'd0,dat_0}};
      default : dt_110 = {1'b0,13'bxxxxxxxxxxxxx};
    endcase
  end

  assign w24_1 = c$w24_app_arg_0 & (~ c$w9_app_arg_4);

  assign \c$_INTERNAL_.w3_app_arg_3  = cin_14[(64'sd1)];

  assign c$w24_app_arg_0 = ~ w6_1;

  assign dat_0 = ds2_0[7:0];

  assign w7_3 = c$w24_app_arg_0 & c$w9_app_arg_4;

  assign result_183 = {result_184
                      ,result_185
                      ,result_186
                      ,result_187};

  assign result_184_selection_res = (bs_76[(64'sd0)]) == (1'b1);

  always @(*) begin
    if(result_184_selection_res)
      result_184 = c$o_regmanage_case_alt_29;
    else
      result_184 = c$o_regmanage_case_alt_30;
  end

  assign result_185_selection_res = (bs_77[(64'sd0)]) == (1'b1);

  always @(*) begin
    if(result_185_selection_res)
      result_185 = c$o_sensorType_case_alt_7;
    else
      result_185 = c$o_sensorType_case_alt_8;
  end

  assign result_186_selection_res = (bs_78[(64'sd0)]) == (1'b1);

  always @(*) begin
    if(result_186_selection_res)
      result_186 = c$o_sensorcontrol_case_alt_43;
    else
      result_186 = c$o_sensorcontrol_case_alt_44;
  end

  assign result_187_selection_res = (bs_79[(64'sd0)]) == (1'b1);

  always @(*) begin
    if(result_187_selection_res)
      result_187 = c$o_status_case_alt_11;
    else
      result_187 = c$o_status_case_alt_12;
  end

  assign c$vecflat_218 = {dt_111
                         ,{1'b0,13'bxxxxxxxxxxxxx}
                         ,dt_115
                         ,dt_116
                         ,dt_117
                         ,dt_118
                         ,dt_119
                         ,dt_120};

  // index begin
  wire [13:0] vec_225 [0:8-1];

  genvar i_227;
  generate
  for (i_227=0; i_227 < 8; i_227=i_227+1) begin : mk_array_225
    assign vec_225[(8-1)-i_227] = c$vecflat_218[i_227*14+:14];
  end
  endgenerate

  assign c$o_regmanage_case_alt_29 = vec_225[(64'sd7)];
  // index end

  assign c$o_regmanage_case_alt_30_selection_res = (bs_76[(64'sd1)]) == (1'b1);

  always @(*) begin
    if(c$o_regmanage_case_alt_30_selection_res)
      c$o_regmanage_case_alt_30 = c$o_regmanage_case_alt_31;
    else
      c$o_regmanage_case_alt_30 = c$o_regmanage_case_alt_32;
  end

  assign c$vecflat_219 = {dt_112,2'd0};

  // index begin
  wire [1:0] vec_226 [0:2-1];

  genvar i_228;
  generate
  for (i_228=0; i_228 < 2; i_228=i_228+1) begin : mk_array_226
    assign vec_226[(2-1)-i_228] = c$vecflat_219[i_228*2+:2];
  end
  endgenerate

  assign c$o_sensorType_case_alt_7 = vec_226[(64'sd1)];
  // index end

  assign c$vecflat_220 = {dt_112,2'd0};

  // index begin
  wire [1:0] vec_227 [0:2-1];

  genvar i_229;
  generate
  for (i_229=0; i_229 < 2; i_229=i_229+1) begin : mk_array_227
    assign vec_227[(2-1)-i_229] = c$vecflat_220[i_229*2+:2];
  end
  endgenerate

  assign c$o_sensorType_case_alt_8 = vec_227[(64'sd0)];
  // index end

  assign c$vecflat_221 = {dt_113
                         ,{2'b00,16'bxxxxxxxxxxxxxxxx}
                         ,{2'b10,8'b00011000,8'bxxxxxxxx}
                         ,{2'b10,8'b00011001,8'bxxxxxxxx}
                         ,{2'b10,8'b00011010,8'bxxxxxxxx}
                         ,{2'b10,8'b00011011,8'bxxxxxxxx}
                         ,{2'b10,8'b00011100,8'bxxxxxxxx}
                         ,{2'b10,8'b00011101,8'bxxxxxxxx}};

  // index begin
  wire [17:0] vec_228 [0:8-1];

  genvar i_230;
  generate
  for (i_230=0; i_230 < 8; i_230=i_230+1) begin : mk_array_228
    assign vec_228[(8-1)-i_230] = c$vecflat_221[i_230*18+:18];
  end
  endgenerate

  assign c$o_sensorcontrol_case_alt_43 = vec_228[(64'sd7)];
  // index end

  assign c$o_sensorcontrol_case_alt_44_selection_res = (bs_78[(64'sd1)]) == (1'b1);

  always @(*) begin
    if(c$o_sensorcontrol_case_alt_44_selection_res)
      c$o_sensorcontrol_case_alt_44 = c$o_sensorcontrol_case_alt_45;
    else
      c$o_sensorcontrol_case_alt_44 = c$o_sensorcontrol_case_alt_46;
  end

  assign c$vecflat_222 = {dt_114,1'b0,1'b1};

  // index begin
  wire  vec_229 [0:3-1];

  genvar i_231;
  generate
  for (i_231=0; i_231 < 3; i_231=i_231+1) begin : mk_array_229
    assign vec_229[(3-1)-i_231] = c$vecflat_222[i_231*1+:1];
  end
  endgenerate

  assign c$o_status_case_alt_11 = vec_229[(64'sd2)];
  // index end

  assign c$o_status_case_alt_12_selection_res = (bs_79[(64'sd1)]) == (1'b1);

  always @(*) begin
    if(c$o_status_case_alt_12_selection_res)
      c$o_status_case_alt_12 = c$o_status_case_alt_13;
    else
      c$o_status_case_alt_12 = c$o_status_case_alt_14;
  end

  assign c$vecflat_223 = {dt_111
                         ,{1'b0,13'bxxxxxxxxxxxxx}
                         ,dt_115
                         ,dt_116
                         ,dt_117
                         ,dt_118
                         ,dt_119
                         ,dt_120};

  // index begin
  wire [13:0] vec_230 [0:8-1];

  genvar i_232;
  generate
  for (i_232=0; i_232 < 8; i_232=i_232+1) begin : mk_array_230
    assign vec_230[(8-1)-i_232] = c$vecflat_223[i_232*14+:14];
  end
  endgenerate

  assign c$o_regmanage_case_alt_31 = vec_230[(64'sd6)];
  // index end

  assign c$o_regmanage_case_alt_32_selection_res = (bs_76[(64'sd2)]) == (1'b1);

  always @(*) begin
    if(c$o_regmanage_case_alt_32_selection_res)
      c$o_regmanage_case_alt_32 = c$o_regmanage_case_alt_33;
    else
      c$o_regmanage_case_alt_32 = c$o_regmanage_case_alt_34;
  end

  assign c$vecflat_224 = {dt_113
                         ,{2'b00,16'bxxxxxxxxxxxxxxxx}
                         ,{2'b10,8'b00011000,8'bxxxxxxxx}
                         ,{2'b10,8'b00011001,8'bxxxxxxxx}
                         ,{2'b10,8'b00011010,8'bxxxxxxxx}
                         ,{2'b10,8'b00011011,8'bxxxxxxxx}
                         ,{2'b10,8'b00011100,8'bxxxxxxxx}
                         ,{2'b10,8'b00011101,8'bxxxxxxxx}};

  // index begin
  wire [17:0] vec_231 [0:8-1];

  genvar i_233;
  generate
  for (i_233=0; i_233 < 8; i_233=i_233+1) begin : mk_array_231
    assign vec_231[(8-1)-i_233] = c$vecflat_224[i_233*18+:18];
  end
  endgenerate

  assign c$o_sensorcontrol_case_alt_45 = vec_231[(64'sd6)];
  // index end

  assign c$o_sensorcontrol_case_alt_46_selection_res = (bs_78[(64'sd2)]) == (1'b1);

  always @(*) begin
    if(c$o_sensorcontrol_case_alt_46_selection_res)
      c$o_sensorcontrol_case_alt_46 = c$o_sensorcontrol_case_alt_47;
    else
      c$o_sensorcontrol_case_alt_46 = c$o_sensorcontrol_case_alt_48;
  end

  assign c$vecflat_225 = {dt_114,1'b0,1'b1};

  // index begin
  wire  vec_232 [0:3-1];

  genvar i_234;
  generate
  for (i_234=0; i_234 < 3; i_234=i_234+1) begin : mk_array_232
    assign vec_232[(3-1)-i_234] = c$vecflat_225[i_234*1+:1];
  end
  endgenerate

  assign c$o_status_case_alt_13 = vec_232[(64'sd1)];
  // index end

  assign c$vecflat_226 = {dt_114,1'b0,1'b1};

  // index begin
  wire  vec_233 [0:3-1];

  genvar i_235;
  generate
  for (i_235=0; i_235 < 3; i_235=i_235+1) begin : mk_array_233
    assign vec_233[(3-1)-i_235] = c$vecflat_226[i_235*1+:1];
  end
  endgenerate

  assign c$o_status_case_alt_14 = vec_233[(64'sd0)];
  // index end

  assign bs_76 = {((result_188[(64'sd0)])),({((result_188[(64'sd1)])),({((result_188[(64'sd2)])),({((result_188[(64'sd3)])),({((result_188[(64'sd4)])),({((result_188[(64'sd5)])),({((result_188[(64'sd6)])),((result_188[(64'sd7)]))})})})})})})};

  assign c$vecflat_227 = {dt_111
                         ,{1'b0,13'bxxxxxxxxxxxxx}
                         ,dt_115
                         ,dt_116
                         ,dt_117
                         ,dt_118
                         ,dt_119
                         ,dt_120};

  // index begin
  wire [13:0] vec_234 [0:8-1];

  genvar i_236;
  generate
  for (i_236=0; i_236 < 8; i_236=i_236+1) begin : mk_array_234
    assign vec_234[(8-1)-i_236] = c$vecflat_227[i_236*14+:14];
  end
  endgenerate

  assign c$o_regmanage_case_alt_33 = vec_234[(64'sd5)];
  // index end

  assign c$o_regmanage_case_alt_34_selection_res = (bs_76[(64'sd3)]) == (1'b1);

  always @(*) begin
    if(c$o_regmanage_case_alt_34_selection_res)
      c$o_regmanage_case_alt_34 = c$o_regmanage_case_alt_35;
    else
      c$o_regmanage_case_alt_34 = c$o_regmanage_case_alt_36;
  end

  assign bs_77 = {((result_188[(64'sd8)])),((result_188[(64'sd9)]))};

  assign bs_78 = {((result_188[(64'sd10)])),({((result_188[(64'sd11)])),({((result_188[(64'sd12)])),({((result_188[(64'sd13)])),({((result_188[(64'sd14)])),({((result_188[(64'sd15)])),({((result_188[(64'sd16)])),((result_188[(64'sd17)]))})})})})})})};

  assign c$vecflat_228 = {dt_113
                         ,{2'b00,16'bxxxxxxxxxxxxxxxx}
                         ,{2'b10,8'b00011000,8'bxxxxxxxx}
                         ,{2'b10,8'b00011001,8'bxxxxxxxx}
                         ,{2'b10,8'b00011010,8'bxxxxxxxx}
                         ,{2'b10,8'b00011011,8'bxxxxxxxx}
                         ,{2'b10,8'b00011100,8'bxxxxxxxx}
                         ,{2'b10,8'b00011101,8'bxxxxxxxx}};

  // index begin
  wire [17:0] vec_235 [0:8-1];

  genvar i_237;
  generate
  for (i_237=0; i_237 < 8; i_237=i_237+1) begin : mk_array_235
    assign vec_235[(8-1)-i_237] = c$vecflat_228[i_237*18+:18];
  end
  endgenerate

  assign c$o_sensorcontrol_case_alt_47 = vec_235[(64'sd5)];
  // index end

  assign c$o_sensorcontrol_case_alt_48_selection_res = (bs_78[(64'sd3)]) == (1'b1);

  always @(*) begin
    if(c$o_sensorcontrol_case_alt_48_selection_res)
      c$o_sensorcontrol_case_alt_48 = c$o_sensorcontrol_case_alt_49;
    else
      c$o_sensorcontrol_case_alt_48 = c$o_sensorcontrol_case_alt_50;
  end

  assign bs_79 = {((result_188[(64'sd18)])),({((result_188[(64'sd19)])),((result_188[(64'sd20)]))})};

  assign c$vecflat_229 = {dt_111
                         ,{1'b0,13'bxxxxxxxxxxxxx}
                         ,dt_115
                         ,dt_116
                         ,dt_117
                         ,dt_118
                         ,dt_119
                         ,dt_120};

  // index begin
  wire [13:0] vec_236 [0:8-1];

  genvar i_238;
  generate
  for (i_238=0; i_238 < 8; i_238=i_238+1) begin : mk_array_236
    assign vec_236[(8-1)-i_238] = c$vecflat_229[i_238*14+:14];
  end
  endgenerate

  assign c$o_regmanage_case_alt_35 = vec_236[(64'sd4)];
  // index end

  assign c$o_regmanage_case_alt_36_selection_res = (bs_76[(64'sd4)]) == (1'b1);

  always @(*) begin
    if(c$o_regmanage_case_alt_36_selection_res)
      c$o_regmanage_case_alt_36 = c$o_regmanage_case_alt_37;
    else
      c$o_regmanage_case_alt_36 = c$o_regmanage_case_alt_38;
  end

  // register begin
  reg [13:0] dt_111_reg = {1'b0,13'bxxxxxxxxxxxxx};
  always @(posedge \$d(%,%) [1:1] or posedge \$d(%,%) [0:0]) begin : dt_111_register
    if (\$d(%,%) [0:0]) begin
      dt_111_reg <= {1'b0,13'bxxxxxxxxxxxxx};
    end else begin
      dt_111_reg <= result_184;
    end
  end
  assign dt_111 = dt_111_reg;
  // register end

  // register begin
  reg [1:0] dt_112_reg = 2'd3;
  always @(posedge \$d(%,%) [1:1] or posedge \$d(%,%) [0:0]) begin : dt_112_register
    if (\$d(%,%) [0:0]) begin
      dt_112_reg <= 2'd3;
    end else begin
      dt_112_reg <= result_185;
    end
  end
  assign dt_112 = dt_112_reg;
  // register end

  assign c$vecflat_230 = {dt_113
                         ,{2'b00,16'bxxxxxxxxxxxxxxxx}
                         ,{2'b10,8'b00011000,8'bxxxxxxxx}
                         ,{2'b10,8'b00011001,8'bxxxxxxxx}
                         ,{2'b10,8'b00011010,8'bxxxxxxxx}
                         ,{2'b10,8'b00011011,8'bxxxxxxxx}
                         ,{2'b10,8'b00011100,8'bxxxxxxxx}
                         ,{2'b10,8'b00011101,8'bxxxxxxxx}};

  // index begin
  wire [17:0] vec_237 [0:8-1];

  genvar i_239;
  generate
  for (i_239=0; i_239 < 8; i_239=i_239+1) begin : mk_array_237
    assign vec_237[(8-1)-i_239] = c$vecflat_230[i_239*18+:18];
  end
  endgenerate

  assign c$o_sensorcontrol_case_alt_49 = vec_237[(64'sd4)];
  // index end

  assign c$o_sensorcontrol_case_alt_50_selection_res = (bs_78[(64'sd4)]) == (1'b1);

  always @(*) begin
    if(c$o_sensorcontrol_case_alt_50_selection_res)
      c$o_sensorcontrol_case_alt_50 = c$o_sensorcontrol_case_alt_51;
    else
      c$o_sensorcontrol_case_alt_50 = c$o_sensorcontrol_case_alt_52;
  end

  // register begin
  reg [17:0] dt_113_reg = {2'b00,16'bxxxxxxxxxxxxxxxx};
  always @(posedge \$d(%,%) [1:1] or posedge \$d(%,%) [0:0]) begin : dt_113_register
    if (\$d(%,%) [0:0]) begin
      dt_113_reg <= {2'b00,16'bxxxxxxxxxxxxxxxx};
    end else begin
      dt_113_reg <= result_186;
    end
  end
  assign dt_113 = dt_113_reg;
  // register end

  // register begin
  reg  dt_114_reg = 1'b0;
  always @(posedge \$d(%,%) [1:1] or posedge \$d(%,%) [0:0]) begin : dt_114_register
    if (\$d(%,%) [0:0]) begin
      dt_114_reg <= 1'b0;
    end else begin
      dt_114_reg <= result_187;
    end
  end
  assign dt_114 = dt_114_reg;
  // register end

  assign c$vecflat_231 = {dt_111
                         ,{1'b0,13'bxxxxxxxxxxxxx}
                         ,dt_115
                         ,dt_116
                         ,dt_117
                         ,dt_118
                         ,dt_119
                         ,dt_120};

  // index begin
  wire [13:0] vec_238 [0:8-1];

  genvar i_240;
  generate
  for (i_240=0; i_240 < 8; i_240=i_240+1) begin : mk_array_238
    assign vec_238[(8-1)-i_240] = c$vecflat_231[i_240*14+:14];
  end
  endgenerate

  assign c$o_regmanage_case_alt_37 = vec_238[(64'sd3)];
  // index end

  assign c$o_regmanage_case_alt_38_selection_res = (bs_76[(64'sd5)]) == (1'b1);

  always @(*) begin
    if(c$o_regmanage_case_alt_38_selection_res)
      c$o_regmanage_case_alt_38 = c$o_regmanage_case_alt_39;
    else
      c$o_regmanage_case_alt_38 = c$o_regmanage_case_alt_40;
  end

  assign c$vecflat_232 = {dt_113
                         ,{2'b00,16'bxxxxxxxxxxxxxxxx}
                         ,{2'b10,8'b00011000,8'bxxxxxxxx}
                         ,{2'b10,8'b00011001,8'bxxxxxxxx}
                         ,{2'b10,8'b00011010,8'bxxxxxxxx}
                         ,{2'b10,8'b00011011,8'bxxxxxxxx}
                         ,{2'b10,8'b00011100,8'bxxxxxxxx}
                         ,{2'b10,8'b00011101,8'bxxxxxxxx}};

  // index begin
  wire [17:0] vec_239 [0:8-1];

  genvar i_241;
  generate
  for (i_241=0; i_241 < 8; i_241=i_241+1) begin : mk_array_239
    assign vec_239[(8-1)-i_241] = c$vecflat_232[i_241*18+:18];
  end
  endgenerate

  assign c$o_sensorcontrol_case_alt_51 = vec_239[(64'sd3)];
  // index end

  assign c$o_sensorcontrol_case_alt_52_selection_res = (bs_78[(64'sd5)]) == (1'b1);

  always @(*) begin
    if(c$o_sensorcontrol_case_alt_52_selection_res)
      c$o_sensorcontrol_case_alt_52 = c$o_sensorcontrol_case_alt_53;
    else
      c$o_sensorcontrol_case_alt_52 = c$o_sensorcontrol_case_alt_54;
  end

  assign c$vecflat_233 = {dt_111
                         ,{1'b0,13'bxxxxxxxxxxxxx}
                         ,dt_115
                         ,dt_116
                         ,dt_117
                         ,dt_118
                         ,dt_119
                         ,dt_120};

  // index begin
  wire [13:0] vec_240 [0:8-1];

  genvar i_242;
  generate
  for (i_242=0; i_242 < 8; i_242=i_242+1) begin : mk_array_240
    assign vec_240[(8-1)-i_242] = c$vecflat_233[i_242*14+:14];
  end
  endgenerate

  assign c$o_regmanage_case_alt_39 = vec_240[(64'sd2)];
  // index end

  assign c$o_regmanage_case_alt_40_selection_res = (bs_76[(64'sd6)]) == (1'b1);

  always @(*) begin
    if(c$o_regmanage_case_alt_40_selection_res)
      c$o_regmanage_case_alt_40 = c$o_regmanage_case_alt_41;
    else
      c$o_regmanage_case_alt_40 = c$o_regmanage_case_alt_42;
  end

  assign c$vecflat_234 = {dt_113
                         ,{2'b00,16'bxxxxxxxxxxxxxxxx}
                         ,{2'b10,8'b00011000,8'bxxxxxxxx}
                         ,{2'b10,8'b00011001,8'bxxxxxxxx}
                         ,{2'b10,8'b00011010,8'bxxxxxxxx}
                         ,{2'b10,8'b00011011,8'bxxxxxxxx}
                         ,{2'b10,8'b00011100,8'bxxxxxxxx}
                         ,{2'b10,8'b00011101,8'bxxxxxxxx}};

  // index begin
  wire [17:0] vec_241 [0:8-1];

  genvar i_243;
  generate
  for (i_243=0; i_243 < 8; i_243=i_243+1) begin : mk_array_241
    assign vec_241[(8-1)-i_243] = c$vecflat_234[i_243*18+:18];
  end
  endgenerate

  assign c$o_sensorcontrol_case_alt_53 = vec_241[(64'sd2)];
  // index end

  assign c$o_sensorcontrol_case_alt_54_selection_res = (bs_78[(64'sd6)]) == (1'b1);

  always @(*) begin
    if(c$o_sensorcontrol_case_alt_54_selection_res)
      c$o_sensorcontrol_case_alt_54 = c$o_sensorcontrol_case_alt_55;
    else
      c$o_sensorcontrol_case_alt_54 = c$o_sensorcontrol_case_alt_56;
  end

  assign c$vecflat_235 = {dt_111
                         ,{1'b0,13'bxxxxxxxxxxxxx}
                         ,dt_115
                         ,dt_116
                         ,dt_117
                         ,dt_118
                         ,dt_119
                         ,dt_120};

  // index begin
  wire [13:0] vec_242 [0:8-1];

  genvar i_244;
  generate
  for (i_244=0; i_244 < 8; i_244=i_244+1) begin : mk_array_242
    assign vec_242[(8-1)-i_244] = c$vecflat_235[i_244*14+:14];
  end
  endgenerate

  assign c$o_regmanage_case_alt_41 = vec_242[(64'sd1)];
  // index end

  assign c$vecflat_236 = {dt_111
                         ,{1'b0,13'bxxxxxxxxxxxxx}
                         ,dt_115
                         ,dt_116
                         ,dt_117
                         ,dt_118
                         ,dt_119
                         ,dt_120};

  // index begin
  wire [13:0] vec_243 [0:8-1];

  genvar i_245;
  generate
  for (i_245=0; i_245 < 8; i_245=i_245+1) begin : mk_array_243
    assign vec_243[(8-1)-i_245] = c$vecflat_236[i_245*14+:14];
  end
  endgenerate

  assign c$o_regmanage_case_alt_42 = vec_243[(64'sd0)];
  // index end

  assign c$vecflat_237 = {dt_113
                         ,{2'b00,16'bxxxxxxxxxxxxxxxx}
                         ,{2'b10,8'b00011000,8'bxxxxxxxx}
                         ,{2'b10,8'b00011001,8'bxxxxxxxx}
                         ,{2'b10,8'b00011010,8'bxxxxxxxx}
                         ,{2'b10,8'b00011011,8'bxxxxxxxx}
                         ,{2'b10,8'b00011100,8'bxxxxxxxx}
                         ,{2'b10,8'b00011101,8'bxxxxxxxx}};

  // index begin
  wire [17:0] vec_244 [0:8-1];

  genvar i_246;
  generate
  for (i_246=0; i_246 < 8; i_246=i_246+1) begin : mk_array_244
    assign vec_244[(8-1)-i_246] = c$vecflat_237[i_246*18+:18];
  end
  endgenerate

  assign c$o_sensorcontrol_case_alt_55 = vec_244[(64'sd1)];
  // index end

  assign c$vecflat_238 = {dt_113
                         ,{2'b00,16'bxxxxxxxxxxxxxxxx}
                         ,{2'b10,8'b00011000,8'bxxxxxxxx}
                         ,{2'b10,8'b00011001,8'bxxxxxxxx}
                         ,{2'b10,8'b00011010,8'bxxxxxxxx}
                         ,{2'b10,8'b00011011,8'bxxxxxxxx}
                         ,{2'b10,8'b00011100,8'bxxxxxxxx}
                         ,{2'b10,8'b00011101,8'bxxxxxxxx}};

  // index begin
  wire [17:0] vec_245 [0:8-1];

  genvar i_247;
  generate
  for (i_247=0; i_247 < 8; i_247=i_247+1) begin : mk_array_245
    assign vec_245[(8-1)-i_247] = c$vecflat_238[i_247*18+:18];
  end
  endgenerate

  assign c$o_sensorcontrol_case_alt_56 = vec_245[(64'sd0)];
  // index end

  assign result_188 = {c$cout_app_arg_40,({(c$cout_app_arg_41),({1'b0,({c$cout_app_arg_42,({c$cout_app_arg_43,({c$cout_app_arg_44,({c$cout_app_arg_45,({c$cout_app_arg_46,({(w20_2),({(((~ (c$cout_app_arg_41 & w7_4)) & \c$_INTERNAL_.w4_app_arg_2 )),({1'b0,({1'b1,({1'b0,({c$cout_app_arg_46,({c$cout_app_arg_44,({c$cout_app_arg_43,({c$cout_app_arg_45,({c$cout_app_arg_42,({c$cout_app_arg_40,({((~ w7_4)),1'b0})})})})})})})})})})})})})})})})})})})};

  always @(*) begin
    case(spiOutput[17:16])
      2'b10 : dt_115 = {1'b1,{4'd6,1'd1,dat_1}};
      default : dt_115 = {1'b0,13'bxxxxxxxxxxxxx};
    endcase
  end

  assign c$cout_app_arg_40 = w10_6;

  assign w10_6 = w9_6 & w8_5;

  always @(*) begin
    case(spiOutput[17:16])
      2'b10 : dt_116 = {1'b1,{4'd6,1'd0,dat_1}};
      default : dt_116 = {1'b0,13'bxxxxxxxxxxxxx};
    endcase
  end

  assign w9_6 = \c$_INTERNAL_.w3_2  & c$w9_app_arg_5;

  assign w8_5 = \c$_INTERNAL_.w5_3  & \c$_INTERNAL_.w4_3 ;

  assign c$cout_app_arg_41 = ~ w10_6;

  // register begin
  reg  c$_INTERNAL_w4_3_reg = (1'b0);
  always @(posedge \$d(%,%) [1:1] or posedge \$d(%,%) [0:0]) begin : c$_INTERNAL_w4_3_register
    if (\$d(%,%) [0:0]) begin
      c$_INTERNAL_w4_3_reg <= (1'b0);
    end else begin
      c$_INTERNAL_w4_3_reg <= (~ ((\c$_INTERNAL_.w4_app_arg_2  & (~ w17_3)) & (~ ((~ w9_6) & \c$_INTERNAL_.w4_3 ))));
    end
  end
  assign \c$_INTERNAL_.w4_3  = c$_INTERNAL_w4_3_reg;
  // register end

  // register begin
  reg  c$_INTERNAL_w3_2_reg = (1'b0);
  always @(posedge \$d(%,%) [1:1] or posedge \$d(%,%) [0:0]) begin : c$_INTERNAL_w3_2_register
    if (\$d(%,%) [0:0]) begin
      c$_INTERNAL_w3_2_reg <= (1'b0);
    end else begin
      c$_INTERNAL_w3_2_reg <= (~ ((~ ((\c$_INTERNAL_.w3_app_arg_4  & c$w11_app_arg_4) & (~ (w6_2 & (~ \c$_INTERNAL_.w3_app_arg_5 ))))) & (~ ((~ (\c$_INTERNAL_.w3_app_arg_4  & (~ (w8_5 & \c$_INTERNAL_.w3_app_arg_5 )))) & \c$_INTERNAL_.w3_2 ))));
    end
  end
  assign \c$_INTERNAL_.w3_2  = c$_INTERNAL_w3_2_reg;
  // register end

  // register begin
  reg  c$_INTERNAL_w5_3_reg = (1'b0);
  always @(posedge \$d(%,%) [1:1] or posedge \$d(%,%) [0:0]) begin : c$_INTERNAL_w5_3_register
    if (\$d(%,%) [0:0]) begin
      c$_INTERNAL_w5_3_reg <= (1'b0);
    end else begin
      c$_INTERNAL_w5_3_reg <= (~ ((~ (c$cout_app_arg_41 & \c$_INTERNAL_.w5_3 )) & (~ w15_2)));
    end
  end
  assign \c$_INTERNAL_.w5_3  = c$_INTERNAL_w5_3_reg;
  // register end

  assign c$cout_app_arg_42 = w12_4;

  assign c$w9_app_arg_5 = cin_15[(64'sd0)];

  always @(*) begin
    case(spiOutput[17:16])
      2'b10 : dt_117 = {1'b1,{4'd4,1'd1,dat_1}};
      default : dt_117 = {1'b0,13'bxxxxxxxxxxxxx};
    endcase
  end

  assign ds2_1 = spiOutput[15:0];

  assign cin_15 = {c$cin_app_arg_14,result_189};

  assign w12_4 = w11_6 & w8_5;

  assign c$cout_app_arg_43 = w17_3;

  assign w17_3 = w16_4 & w9_6;

  assign w11_6 = c$w11_app_arg_4 & c$w9_app_arg_5;

  assign c$cout_app_arg_44 = w18_2;

  always @(*) begin
    if(b_44)
      result_189 = 1'b1;
    else
      result_189 = 1'b0;
  end

  always @(*) begin
    if(startGyr)
      c$cin_app_arg_14 = 1'b1;
    else
      c$cin_app_arg_14 = 1'b0;
  end

  always @(*) begin
    case(spiOutput[17:16])
      2'b10 : dt_118 = {1'b1,{4'd5,1'd1,dat_1}};
      default : dt_118 = {1'b0,13'bxxxxxxxxxxxxx};
    endcase
  end

  assign w16_4 = \c$_INTERNAL_.w5_3  & c$w16_app_arg_2;

  assign w18_2 = w16_4 & w11_6;

  assign c$cout_app_arg_45 = w15_2;

  assign c$w11_app_arg_4 = ~ \c$_INTERNAL_.w3_2 ;

  always @(*) begin
    case(spiOutput[17:16])
      2'b00 : b_44 = 1'b0;
      default : b_44 = 1'b1;
    endcase
  end

  assign w15_2 = w14_2 & \c$_INTERNAL_.w3_2 ;

  assign c$cout_app_arg_46 = w19_3;

  assign \c$_INTERNAL_.w4_app_arg_2  = ~ w20_2;

  assign c$w16_app_arg_2 = ~ \c$_INTERNAL_.w4_3 ;

  always @(*) begin
    case(spiOutput[17:16])
      2'b10 : dt_119 = {1'b1,{4'd5,1'd0,dat_1}};
      default : dt_119 = {1'b0,13'bxxxxxxxxxxxxx};
    endcase
  end

  assign w20_2 = w6_2 & \c$_INTERNAL_.w3_2 ;

  assign w14_2 = (\c$_INTERNAL_.w4_3  & c$w9_app_arg_5) & c$w14_app_arg_1;

  assign w19_3 = w14_2 & c$w11_app_arg_4;

  assign w6_2 = c$w14_app_arg_1 & c$w16_app_arg_2;

  assign c$w14_app_arg_1 = ~ \c$_INTERNAL_.w5_3 ;

  assign \c$_INTERNAL_.w3_app_arg_4  = ~ w24_2;

  always @(*) begin
    case(spiOutput[17:16])
      2'b10 : dt_120 = {1'b1,{4'd4,1'd0,dat_1}};
      default : dt_120 = {1'b0,13'bxxxxxxxxxxxxx};
    endcase
  end

  assign w24_2 = c$w24_app_arg_1 & (~ c$w9_app_arg_5);

  assign \c$_INTERNAL_.w3_app_arg_5  = cin_15[(64'sd1)];

  assign c$w24_app_arg_1 = ~ w6_2;

  assign dat_1 = ds2_1[7:0];

  assign w7_4 = c$w24_app_arg_1 & c$w9_app_arg_5;

  assign result_190_selection_res = (result_191[(64'sd0)]) == (1'b1);

  always @(*) begin
    if(result_190_selection_res)
      result_190 = c$o_partcontrol_case_alt;
    else
      result_190 = c$o_partcontrol_case_alt_0;
  end

  assign c$vecflat_239 = {dt_121
                         ,{1'b1,1'b0,1'b0,1'b0}
                         ,{1'b0,1'b1,1'b0,1'b0}
                         ,{1'b0,1'b0,1'b1,1'b0}
                         ,{1'b0,1'b0,1'b0,1'b1}
                         ,{1'b0,1'b0,1'b0,1'b0}};

  // index begin
  wire [3:0] vec_246 [0:6-1];

  genvar i_248;
  generate
  for (i_248=0; i_248 < 6; i_248=i_248+1) begin : mk_array_246
    assign vec_246[(6-1)-i_248] = c$vecflat_239[i_248*4+:4];
  end
  endgenerate

  assign c$o_partcontrol_case_alt = vec_246[(64'sd5)];
  // index end

  assign c$o_partcontrol_case_alt_0_selection_res = (result_191[(64'sd1)]) == (1'b1);

  always @(*) begin
    if(c$o_partcontrol_case_alt_0_selection_res)
      c$o_partcontrol_case_alt_0 = c$o_partcontrol_case_alt_1;
    else
      c$o_partcontrol_case_alt_0 = c$o_partcontrol_case_alt_2;
  end

  assign c$vecflat_240 = {dt_121
                         ,{1'b1,1'b0,1'b0,1'b0}
                         ,{1'b0,1'b1,1'b0,1'b0}
                         ,{1'b0,1'b0,1'b1,1'b0}
                         ,{1'b0,1'b0,1'b0,1'b1}
                         ,{1'b0,1'b0,1'b0,1'b0}};

  // index begin
  wire [3:0] vec_247 [0:6-1];

  genvar i_249;
  generate
  for (i_249=0; i_249 < 6; i_249=i_249+1) begin : mk_array_247
    assign vec_247[(6-1)-i_249] = c$vecflat_240[i_249*4+:4];
  end
  endgenerate

  assign c$o_partcontrol_case_alt_1 = vec_247[(64'sd4)];
  // index end

  assign c$o_partcontrol_case_alt_2_selection_res = (result_191[(64'sd2)]) == (1'b1);

  always @(*) begin
    if(c$o_partcontrol_case_alt_2_selection_res)
      c$o_partcontrol_case_alt_2 = c$o_partcontrol_case_alt_3;
    else
      c$o_partcontrol_case_alt_2 = c$o_partcontrol_case_alt_4;
  end

  assign c$vecflat_241 = {dt_121
                         ,{1'b1,1'b0,1'b0,1'b0}
                         ,{1'b0,1'b1,1'b0,1'b0}
                         ,{1'b0,1'b0,1'b1,1'b0}
                         ,{1'b0,1'b0,1'b0,1'b1}
                         ,{1'b0,1'b0,1'b0,1'b0}};

  // index begin
  wire [3:0] vec_248 [0:6-1];

  genvar i_250;
  generate
  for (i_250=0; i_250 < 6; i_250=i_250+1) begin : mk_array_248
    assign vec_248[(6-1)-i_250] = c$vecflat_241[i_250*4+:4];
  end
  endgenerate

  assign c$o_partcontrol_case_alt_3 = vec_248[(64'sd3)];
  // index end

  assign c$o_partcontrol_case_alt_4_selection_res = (result_191[(64'sd3)]) == (1'b1);

  always @(*) begin
    if(c$o_partcontrol_case_alt_4_selection_res)
      c$o_partcontrol_case_alt_4 = c$o_partcontrol_case_alt_5;
    else
      c$o_partcontrol_case_alt_4 = c$o_partcontrol_case_alt_6;
  end

  assign c$vecflat_242 = {dt_121
                         ,{1'b1,1'b0,1'b0,1'b0}
                         ,{1'b0,1'b1,1'b0,1'b0}
                         ,{1'b0,1'b0,1'b1,1'b0}
                         ,{1'b0,1'b0,1'b0,1'b1}
                         ,{1'b0,1'b0,1'b0,1'b0}};

  // index begin
  wire [3:0] vec_249 [0:6-1];

  genvar i_251;
  generate
  for (i_251=0; i_251 < 6; i_251=i_251+1) begin : mk_array_249
    assign vec_249[(6-1)-i_251] = c$vecflat_242[i_251*4+:4];
  end
  endgenerate

  assign c$o_partcontrol_case_alt_5 = vec_249[(64'sd2)];
  // index end

  assign c$o_partcontrol_case_alt_6_selection_res = (result_191[(64'sd4)]) == (1'b1);

  always @(*) begin
    if(c$o_partcontrol_case_alt_6_selection_res)
      c$o_partcontrol_case_alt_6 = c$o_partcontrol_case_alt_7;
    else
      c$o_partcontrol_case_alt_6 = c$o_partcontrol_case_alt_8;
  end

  // register begin
  reg [3:0] dt_121_reg = {1'b0,1'b0,1'b0,1'b0};
  always @(posedge \$d(%,%) [1:1] or posedge \$d(%,%) [0:0]) begin : dt_121_register
    if (\$d(%,%) [0:0]) begin
      dt_121_reg <= {1'b0,1'b0,1'b0,1'b0};
    end else begin
      dt_121_reg <= result_190;
    end
  end
  assign dt_121 = dt_121_reg;
  // register end

  assign result_191 = {((result_192[(64'sd0)])),({((result_192[(64'sd1)])),({((result_192[(64'sd2)])),({((result_192[(64'sd3)])),({((result_192[(64'sd4)])),((result_192[(64'sd5)]))})})})})};

  assign c$vecflat_243 = {dt_121
                         ,{1'b1,1'b0,1'b0,1'b0}
                         ,{1'b0,1'b1,1'b0,1'b0}
                         ,{1'b0,1'b0,1'b1,1'b0}
                         ,{1'b0,1'b0,1'b0,1'b1}
                         ,{1'b0,1'b0,1'b0,1'b0}};

  // index begin
  wire [3:0] vec_250 [0:6-1];

  genvar i_252;
  generate
  for (i_252=0; i_252 < 6; i_252=i_252+1) begin : mk_array_250
    assign vec_250[(6-1)-i_252] = c$vecflat_243[i_252*4+:4];
  end
  endgenerate

  assign c$o_partcontrol_case_alt_7 = vec_250[(64'sd1)];
  // index end

  assign c$vecflat_244 = {dt_121
                         ,{1'b1,1'b0,1'b0,1'b0}
                         ,{1'b0,1'b1,1'b0,1'b0}
                         ,{1'b0,1'b0,1'b1,1'b0}
                         ,{1'b0,1'b0,1'b0,1'b1}
                         ,{1'b0,1'b0,1'b0,1'b0}};

  // index begin
  wire [3:0] vec_251 [0:6-1];

  genvar i_253;
  generate
  for (i_253=0; i_253 < 6; i_253=i_253+1) begin : mk_array_251
    assign vec_251[(6-1)-i_253] = c$vecflat_244[i_253*4+:4];
  end
  endgenerate

  assign c$o_partcontrol_case_alt_8 = vec_251[(64'sd0)];
  // index end

  assign result_192 = {((~ ((~ ((~ ((~ (w12_5 & \c$_INTERNAL_.w7_1 )) & c$cout_app_arg_52)) & c$cout_app_arg_50)) & (~ ((~ w16_5) & w6_3))))),({(\_INTERNAL_.w37 ),({(((c$cout_app_arg_50 & c$cout_app_arg_49) & c$cout_app_arg_47)),({((w33_1 & c$cout_app_arg_48)),({(((~ ((~ (w18_3 & \c$_INTERNAL_.w5_4 )) & w6_3)) & c$cout_app_arg_51)),((w21_1 & w16_5))})})})})};

  assign \_INTERNAL_.w37  = w19_4 & w17_4;

  assign w19_4 = w6_3 & \c$_INTERNAL_.w5_4 ;

  assign w17_4 = c$cout_app_arg_47 & c$w17_app_arg;

  // register begin
  reg  w6_3_reg = (1'b0);
  always @(posedge \$d(%,%) [1:1] or posedge \$d(%,%) [0:0]) begin : w6_3_register
    if (\$d(%,%) [0:0]) begin
      w6_3_reg <= (1'b0);
    end else begin
      w6_3_reg <= (c$w6_app_arg & c$cout_app_arg_51);
    end
  end
  assign w6_3 = w6_3_reg;
  // register end

  // register begin
  reg  c$_INTERNAL_w5_4_reg = (1'b0);
  always @(posedge \$d(%,%) [1:1] or posedge \$d(%,%) [0:0]) begin : c$_INTERNAL_w5_4_register
    if (\$d(%,%) [0:0]) begin
      c$_INTERNAL_w5_4_reg <= (1'b0);
    end else begin
      c$_INTERNAL_w5_4_reg <= (~ (((~ w33_1) & (~ w21_1)) & c$cout_app_arg_51));
    end
  end
  assign \c$_INTERNAL_.w5_4  = c$_INTERNAL_w5_4_reg;
  // register end

  assign c$cout_app_arg_47 = ~ \c$_INTERNAL_.w7_1 ;

  assign c$w17_app_arg = cin_16[(64'sd1)];

  assign cin_16 = {c$cin_app_arg_15,({c$cin_app_arg_16,({c$cin_app_arg_18,c$cin_app_arg_17})})};

  // register begin
  reg  c$_INTERNAL_w7_1_reg = (1'b0);
  always @(posedge \$d(%,%) [1:1] or posedge \$d(%,%) [0:0]) begin : c$_INTERNAL_w7_1_register
    if (\$d(%,%) [0:0]) begin
      c$_INTERNAL_w7_1_reg <= (1'b0);
    end else begin
      c$_INTERNAL_w7_1_reg <= (~ (c$w6_app_arg & c$cout_app_arg_48));
    end
  end
  assign \c$_INTERNAL_.w7_1  = c$_INTERNAL_w7_1_reg;
  // register end

  assign w33_1 = w9_7 & w6_3;

  assign c$cout_app_arg_48 = ~ \c$_INTERNAL_.w8_0 ;

  assign c$cout_app_arg_49 = ~ \c$_INTERNAL_.w5_4 ;

  assign c$cout_app_arg_50 = ~ w6_3;

  assign w9_7 = c$cout_app_arg_49 & c$w9_app_arg_6;

  assign \c$_INTERNAL_.w8_0  = \c$_INTERNAL_.w7_1  & c$w12_app_arg_0;

  assign w21_1 = (c$w21_app_arg_1 & (~ w17_4)) & w19_4;

  assign w16_5 = (~ ((~ ((~ (w12_5 & c$cout_app_arg_47)) & \c$_INTERNAL_.w5_4 )) & (~ w9_7))) & c$cout_app_arg_48;

  assign c$cout_app_arg_51 = ~ \c$_INTERNAL_.w29_0 ;

  assign c$w6_app_arg = ~ \_INTERNAL_.w37 ;

  always @(*) begin
    if(c$tup_app_arg_2)
      c$cin_app_arg_15 = 1'b1;
    else
      c$cin_app_arg_15 = 1'b0;
  end

  assign \c$_INTERNAL_.w29_0  = (~ (c$cout_app_arg_52 & (~ ((~ ((~ w12_5) & \c$_INTERNAL_.w7_1 )) & c$cout_app_arg_49)))) & c$cout_app_arg_50;

  assign c$cout_app_arg_52 = ~ w27_2;

  assign c$w9_app_arg_6 = cin_16[(64'sd0)];

  always @(*) begin
    if(c$tup_app_arg_1)
      c$cin_app_arg_16 = 1'b1;
    else
      c$cin_app_arg_16 = 1'b0;
  end

  assign w27_2 = (c$w21_app_arg_1 & \c$_INTERNAL_.w5_4 ) & (~ (c$cout_app_arg_47 & c$w27_app_arg_1));

  assign c$w21_app_arg_1 = ~ w18_3;

  assign \c$_INTERNAL_.w8_app_arg  = cin_16[(64'sd3)];

  always @(*) begin
    if(c$tup_app_arg)
      c$cin_app_arg_17 = 1'b1;
    else
      c$cin_app_arg_17 = 1'b0;
  end

  always @(*) begin
    if(c$tup_app_arg_0)
      c$cin_app_arg_18 = 1'b1;
    else
      c$cin_app_arg_18 = 1'b0;
  end

  assign w12_5 = (c$w12_app_arg_0 & (~ c$w27_app_arg_1)) & ((~ c$w17_app_arg) & (~ c$w9_app_arg_6));

  assign w18_3 = \c$_INTERNAL_.w7_1  & \c$_INTERNAL_.w8_app_arg ;

  assign c$w27_app_arg_1 = cin_16[(64'sd2)];

  assign c$w12_app_arg_0 = ~ \c$_INTERNAL_.w8_app_arg ;

  assign counter = result_227[33:26];

  assign b_45 = counter == 8'd2;

  assign b_46 = counter == 8'd3;

  assign b_47 = counter >= 8'd4;

  always @(*) begin
    if(b_45)
      result_193 = 1'b1;
    else
      result_193 = 1'b0;
  end

  always @(*) begin
    if(b_46)
      result_194 = 1'b1;
    else
      result_194 = 1'b0;
  end

  assign b_48 = counter >= 8'd24;

  always @(*) begin
    if(b_47)
      result_195 = 1'b1;
    else
      result_195 = 1'b0;
  end

  assign b_49 = counter <= 8'd17;

  always @(*) begin
    if(b_48)
      result_196 = 1'b1;
    else
      result_196 = 1'b0;
  end

  assign b_50 = counter <= 8'd39;

  always @(*) begin
    if(b_49)
      result_197 = 1'b1;
    else
      result_197 = 1'b0;
  end

  always @(*) begin
    if(b_50)
      result_198 = 1'b1;
    else
      result_198 = 1'b0;
  end

  assign cin_17 = {result_198,({result_197,({result_196,({result_195,({result_193,result_194})})})})};

  assign c$w8_app_arg = cin_17[(64'sd4)];

  assign w7_5 = ((cin_17[(64'sd3)]) & (~ c$w8_app_arg)) & (cin_17[(64'sd5)]);

  assign w8_6 = c$w8_app_arg & (cin_17[(64'sd2)]);

  // register begin
  reg  dt_122_reg = (1'b0);
  always @(posedge \$d(%,%) [1:1] or posedge \$d(%,%) [0:0]) begin : dt_122_register
    if (\$d(%,%) [0:0]) begin
      dt_122_reg <= (1'b0);
    end else begin
      dt_122_reg <= result_202;
    end
  end
  assign dt_122 = dt_122_reg;
  // register end

  assign c$bv_10 = result_227[7:0];

  assign c$dt_case_alt_3_selection_res = (c$bv_10[(64'sd0)]) == (1'b1);

  always @(*) begin
    if(c$dt_case_alt_3_selection_res)
      c$dt_case_alt_3 = 1'b1;
    else
      c$dt_case_alt_3 = 1'b0;
  end

  assign c$bv_11 = result_227[7:0];

  assign c$dt_case_alt_4_selection_res = (c$bv_11[(64'sd1)]) == (1'b1);

  always @(*) begin
    if(c$dt_case_alt_4_selection_res)
      c$dt_case_alt_4 = 1'b1;
    else
      c$dt_case_alt_4 = 1'b0;
  end

  assign c$bv_12 = result_227[7:0];

  assign c$dt_case_alt_5_selection_res = (c$bv_12[(64'sd2)]) == (1'b1);

  always @(*) begin
    if(c$dt_case_alt_5_selection_res)
      c$dt_case_alt_5 = 1'b1;
    else
      c$dt_case_alt_5 = 1'b0;
  end

  assign c$bv_13 = result_227[7:0];

  assign c$dt_case_alt_6_selection_res = (c$bv_13[(64'sd3)]) == (1'b1);

  always @(*) begin
    if(c$dt_case_alt_6_selection_res)
      c$dt_case_alt_6 = 1'b1;
    else
      c$dt_case_alt_6 = 1'b0;
  end

  assign c$bv_14 = result_227[7:0];

  assign c$dt_case_alt_7_selection_res = (c$bv_14[(64'sd4)]) == (1'b1);

  always @(*) begin
    if(c$dt_case_alt_7_selection_res)
      c$dt_case_alt_7 = 1'b1;
    else
      c$dt_case_alt_7 = 1'b0;
  end

  assign c$bv_15 = result_227[7:0];

  assign c$dt_case_alt_8_selection_res = (c$bv_15[(64'sd5)]) == (1'b1);

  always @(*) begin
    if(c$dt_case_alt_8_selection_res)
      c$dt_case_alt_8 = 1'b1;
    else
      c$dt_case_alt_8 = 1'b0;
  end

  assign c$bv_16 = result_227[7:0];

  assign c$dt_case_alt_9_selection_res = (c$bv_16[(64'sd6)]) == (1'b1);

  always @(*) begin
    if(c$dt_case_alt_9_selection_res)
      c$dt_case_alt_9 = 1'b1;
    else
      c$dt_case_alt_9 = 1'b0;
  end

  assign c$bv_17 = result_227[7:0];

  assign c$dt_case_alt_10_selection_res = (c$bv_17[(64'sd7)]) == (1'b1);

  always @(*) begin
    if(c$dt_case_alt_10_selection_res)
      c$dt_case_alt_10 = 1'b1;
    else
      c$dt_case_alt_10 = 1'b0;
  end

  assign ds_0 = 8'd19 - w13_3;

  assign cout_0 = {1'b0,({(((~ w7_5) & (~ w8_6))),({(w7_5),(w8_6)})})};

  always @(*) begin
    case(ds_0)
      8'd0 : result_199 = c$dt_case_alt_3;
      8'd1 : result_199 = c$dt_case_alt_4;
      8'd2 : result_199 = c$dt_case_alt_5;
      8'd3 : result_199 = c$dt_case_alt_6;
      8'd4 : result_199 = c$dt_case_alt_7;
      8'd5 : result_199 = c$dt_case_alt_8;
      8'd6 : result_199 = c$dt_case_alt_9;
      8'd7 : result_199 = c$dt_case_alt_10;
      default : result_199 = 1'b0;
    endcase
  end

  assign w13_3 = counter / 8'd2;

  assign c$bv_18 = result_227[15:8];

  assign c$dt_case_alt_11_selection_res = (c$bv_18[(64'sd0)]) == (1'b1);

  always @(*) begin
    if(c$dt_case_alt_11_selection_res)
      c$dt_case_alt_11 = 1'b1;
    else
      c$dt_case_alt_11 = 1'b0;
  end

  assign c$bv_19 = result_227[15:8];

  assign c$dt_case_alt_12_selection_res = (c$bv_19[(64'sd1)]) == (1'b1);

  always @(*) begin
    if(c$dt_case_alt_12_selection_res)
      c$dt_case_alt_12 = 1'b1;
    else
      c$dt_case_alt_12 = 1'b0;
  end

  assign c$bv_20 = result_227[15:8];

  assign c$dt_case_alt_13_selection_res = (c$bv_20[(64'sd2)]) == (1'b1);

  always @(*) begin
    if(c$dt_case_alt_13_selection_res)
      c$dt_case_alt_13 = 1'b1;
    else
      c$dt_case_alt_13 = 1'b0;
  end

  assign c$bv_21 = result_227[15:8];

  assign c$dt_case_alt_14_selection_res = (c$bv_21[(64'sd3)]) == (1'b1);

  always @(*) begin
    if(c$dt_case_alt_14_selection_res)
      c$dt_case_alt_14 = 1'b1;
    else
      c$dt_case_alt_14 = 1'b0;
  end

  assign c$bv_22 = result_227[15:8];

  assign c$dt_case_alt_15_selection_res = (c$bv_22[(64'sd4)]) == (1'b1);

  always @(*) begin
    if(c$dt_case_alt_15_selection_res)
      c$dt_case_alt_15 = 1'b1;
    else
      c$dt_case_alt_15 = 1'b0;
  end

  assign c$bv_23 = result_227[15:8];

  assign c$dt_case_alt_16_selection_res = (c$bv_23[(64'sd5)]) == (1'b1);

  always @(*) begin
    if(c$dt_case_alt_16_selection_res)
      c$dt_case_alt_16 = 1'b1;
    else
      c$dt_case_alt_16 = 1'b0;
  end

  assign c$bv_24 = result_227[15:8];

  assign c$dt_case_alt_17_selection_res = (c$bv_24[(64'sd6)]) == (1'b1);

  always @(*) begin
    if(c$dt_case_alt_17_selection_res)
      c$dt_case_alt_17 = 1'b1;
    else
      c$dt_case_alt_17 = 1'b0;
  end

  assign c$bv_25 = result_227[15:8];

  assign c$dt_case_alt_18_selection_res = (c$bv_25[(64'sd7)]) == (1'b1);

  always @(*) begin
    if(c$dt_case_alt_18_selection_res)
      c$dt_case_alt_18 = 1'b1;
    else
      c$dt_case_alt_18 = 1'b0;
  end

  assign ds_1 = 8'd8 - w13_3;

  always @(*) begin
    case(ds_1)
      8'd0 : result_200 = c$dt_case_alt_11;
      8'd1 : result_200 = c$dt_case_alt_12;
      8'd2 : result_200 = c$dt_case_alt_13;
      8'd3 : result_200 = c$dt_case_alt_14;
      8'd4 : result_200 = c$dt_case_alt_15;
      8'd5 : result_200 = c$dt_case_alt_16;
      8'd6 : result_200 = c$dt_case_alt_17;
      8'd7 : result_200 = c$dt_case_alt_18;
      default : result_200 = 1'b0;
    endcase
  end

  assign result_201 = {((cout_0[(64'sd0)])),({((cout_0[(64'sd1)])),({((cout_0[(64'sd2)])),((cout_0[(64'sd3)]))})})};

  assign c$vecflat_245 = {result_200
                         ,result_199
                         ,1'b0
                         ,dt_122};

  // index begin
  wire  vec_252 [0:4-1];

  genvar i_254;
  generate
  for (i_254=0; i_254 < 4; i_254=i_254+1) begin : mk_array_252
    assign vec_252[(4-1)-i_254] = c$vecflat_245[i_254*1+:1];
  end
  endgenerate

  assign c$o_sdi_case_alt = vec_252[(64'sd0)];
  // index end

  assign c$vecflat_246 = {result_200
                         ,result_199
                         ,1'b0
                         ,dt_122};

  // index begin
  wire  vec_253 [0:4-1];

  genvar i_255;
  generate
  for (i_255=0; i_255 < 4; i_255=i_255+1) begin : mk_array_253
    assign vec_253[(4-1)-i_255] = c$vecflat_246[i_255*1+:1];
  end
  endgenerate

  assign c$o_sdi_case_alt_0 = vec_253[(64'sd1)];
  // index end

  assign c$o_sdi_case_alt_1_selection_res = (result_201[(64'sd2)]) == (1'b1);

  always @(*) begin
    if(c$o_sdi_case_alt_1_selection_res)
      c$o_sdi_case_alt_1 = c$o_sdi_case_alt_0;
    else
      c$o_sdi_case_alt_1 = c$o_sdi_case_alt;
  end

  assign c$vecflat_247 = {result_200
                         ,result_199
                         ,1'b0
                         ,dt_122};

  // index begin
  wire  vec_254 [0:4-1];

  genvar i_256;
  generate
  for (i_256=0; i_256 < 4; i_256=i_256+1) begin : mk_array_254
    assign vec_254[(4-1)-i_256] = c$vecflat_247[i_256*1+:1];
  end
  endgenerate

  assign c$o_sdi_case_alt_2 = vec_254[(64'sd2)];
  // index end

  assign c$o_sdi_case_alt_3_selection_res = (result_201[(64'sd1)]) == (1'b1);

  always @(*) begin
    if(c$o_sdi_case_alt_3_selection_res)
      c$o_sdi_case_alt_3 = c$o_sdi_case_alt_2;
    else
      c$o_sdi_case_alt_3 = c$o_sdi_case_alt_1;
  end

  assign c$vecflat_248 = {result_200
                         ,result_199
                         ,1'b0
                         ,dt_122};

  // index begin
  wire  vec_255 [0:4-1];

  genvar i_257;
  generate
  for (i_257=0; i_257 < 4; i_257=i_257+1) begin : mk_array_255
    assign vec_255[(4-1)-i_257] = c$vecflat_248[i_257*1+:1];
  end
  endgenerate

  assign c$o_sdi_case_alt_4 = vec_255[(64'sd3)];
  // index end

  assign result_202_selection_res = (result_201[(64'sd0)]) == (1'b1);

  always @(*) begin
    if(result_202_selection_res)
      result_202 = c$o_sdi_case_alt_4;
    else
      result_202 = c$o_sdi_case_alt_3;
  end

  assign result_203_selection_res = (result_204[(64'sd0)]) == (1'b1);

  always @(*) begin
    if(result_203_selection_res)
      result_203 = c$o_spc_case_alt;
    else
      result_203 = c$o_spc_case_alt_0;
  end

  assign c$vecflat_249 = {1'b1,1'b0,dt_123};

  // index begin
  wire  vec_256 [0:3-1];

  genvar i_258;
  generate
  for (i_258=0; i_258 < 3; i_258=i_258+1) begin : mk_array_256
    assign vec_256[(3-1)-i_258] = c$vecflat_249[i_258*1+:1];
  end
  endgenerate

  assign c$o_spc_case_alt = vec_256[(64'sd2)];
  // index end

  assign c$o_spc_case_alt_0_selection_res = (result_204[(64'sd1)]) == (1'b1);

  always @(*) begin
    if(c$o_spc_case_alt_0_selection_res)
      c$o_spc_case_alt_0 = c$o_spc_case_alt_1;
    else
      c$o_spc_case_alt_0 = c$o_spc_case_alt_2;
  end

  assign c$vecflat_250 = {1'b1,1'b0,dt_123};

  // index begin
  wire  vec_257 [0:3-1];

  genvar i_259;
  generate
  for (i_259=0; i_259 < 3; i_259=i_259+1) begin : mk_array_257
    assign vec_257[(3-1)-i_259] = c$vecflat_250[i_259*1+:1];
  end
  endgenerate

  assign c$o_spc_case_alt_1 = vec_257[(64'sd1)];
  // index end

  assign c$vecflat_251 = {1'b1,1'b0,dt_123};

  // index begin
  wire  vec_258 [0:3-1];

  genvar i_260;
  generate
  for (i_260=0; i_260 < 3; i_260=i_260+1) begin : mk_array_258
    assign vec_258[(3-1)-i_260] = c$vecflat_251[i_260*1+:1];
  end
  endgenerate

  assign c$o_spc_case_alt_2 = vec_258[(64'sd0)];
  // index end

  assign result_204 = {((cout_1[(64'sd0)])),({((cout_1[(64'sd1)])),((cout_1[(64'sd2)]))})};

  assign cout_1 = {1'b0,({(result_205),((~ result_205))})};

  // register begin
  reg  dt_123_reg = (1'b1);
  always @(posedge \$d(%,%) [1:1] or posedge \$d(%,%) [0:0]) begin : dt_123_register
    if (\$d(%,%) [0:0]) begin
      dt_123_reg <= (1'b1);
    end else begin
      dt_123_reg <= result_203;
    end
  end
  assign dt_123 = dt_123_reg;
  // register end

  assign result_205 = ((~ (cin_18[(64'sd0)])) & (~ ((cin_18[(64'sd1)]) & (cin_18[(64'sd4)])))) & (~ ((cin_18[(64'sd3)]) & (~ (cin_18[(64'sd2)]))));

  assign cin_18 = {result_206,({result_207,({result_208,({result_210,result_209})})})};

  always @(*) begin
    if(b_51)
      result_206 = 1'b1;
    else
      result_206 = 1'b0;
  end

  always @(*) begin
    if(b_52)
      result_207 = 1'b1;
    else
      result_207 = 1'b0;
  end

  assign b_51 = counter < 8'd24;

  always @(*) begin
    if(b_53)
      result_208 = 1'b1;
    else
      result_208 = 1'b0;
  end

  assign b_52 = counter < 8'd40;

  always @(*) begin
    if(b_54)
      result_209 = 1'b1;
    else
      result_209 = 1'b0;
  end

  always @(*) begin
    if(b_55)
      result_210 = 1'b1;
    else
      result_210 = 1'b0;
  end

  assign b_53 = (counter % 8'd2) == 8'd0;

  assign b_54 = counter == 8'd0;

  assign b_55 = counter > 8'd16;

  assign w12_6 = c$w32_app_arg_0 & (~ c$w13_app_arg_1);

  assign b_56 = c_counter_2 == 8'd0;

  assign b_57_selection = result_261[16:0];

  always @(*) begin
    case(b_57_selection[16:16])
      1'b0 : b_57 = 1'b0;
      default : b_57 = 1'b1;
    endcase
  end

  assign b_58 = c_prescaler_1 == 8'd0;

  always @(*) begin
    if(b_56)
      result_211 = 1'b1;
    else
      result_211 = 1'b0;
  end

  always @(*) begin
    if(b_57)
      result_212 = 1'b1;
    else
      result_212 = 1'b0;
  end

  assign b_59 = c_counter_2 == 8'd40;

  always @(*) begin
    if(b_58)
      result_213 = 1'b1;
    else
      result_213 = 1'b0;
  end

  assign b_60 = c_counter_2 == 8'd41;

  always @(*) begin
    if(b_59)
      result_214 = 1'b1;
    else
      result_214 = 1'b0;
  end

  assign c$cout_app_arg_53 = ~ \c$_INTERNAL_.w23_0 ;

  assign b_61 = c_counter_2 == 8'd2;

  always @(*) begin
    if(b_60)
      result_215 = 1'b1;
    else
      result_215 = 1'b0;
  end

  assign c$w32_app_arg_0 = cin_19[(64'sd2)];

  assign b_62 = c_counter_2 >= 8'd4;

  always @(*) begin
    if(b_61)
      result_216 = 1'b1;
    else
      result_216 = 1'b0;
  end

  assign b_63 = c_counter_2 >= 8'd24;

  always @(*) begin
    if(b_62)
      result_217 = 1'b1;
    else
      result_217 = 1'b0;
  end

  assign \c$_INTERNAL_.w18_app_arg_0  = cin_19[(64'sd5)];

  assign b_64 = c_counter_2 <= 8'd16;

  always @(*) begin
    if(b_63)
      result_218 = 1'b1;
    else
      result_218 = 1'b0;
  end

  assign w32_2 = (~ ((cin_19[(64'sd4)]) & c$w32_app_arg_0)) & \c$_INTERNAL_.w18_1 ;

  always @(*) begin
    if(b_64)
      result_219 = 1'b1;
    else
      result_219 = 1'b0;
  end

  assign \_INTERNAL_.w27  = (~ (c$w19_app_arg & (~ w10_7))) & (~ (cin_19[(64'sd3)]));

  assign cin_19 = {result_219,({result_218,({result_217,({result_216,({result_215,({result_214,({result_213,({result_211,result_212})})})})})})})};

  assign c$w13_app_arg_1 = cin_19[(64'sd1)];

  assign \c$_INTERNAL_.w23_0  = c$w34_app_arg & (~ \c$_INTERNAL_.w18_1 );

  assign w29_1 = \_INTERNAL_.w27  & \c$_INTERNAL_.w18_1 ;

  assign \c$_INTERNAL_.w18_app_arg_1  = ~ w11_7;

  // register begin
  reg  w11_7_reg = (1'b0);
  always @(posedge \$d(%,%) [1:1] or posedge \$d(%,%) [0:0]) begin : w11_7_register
    if (\$d(%,%) [0:0]) begin
      w11_7_reg <= (1'b0);
    end else begin
      w11_7_reg <= \c$_INTERNAL_.w23_0 ;
    end
  end
  assign w11_7 = w11_7_reg;
  // register end

  // register begin
  reg  w10_7_reg = (1'b0);
  always @(posedge \$d(%,%) [1:1] or posedge \$d(%,%) [0:0]) begin : w10_7_register
    if (\$d(%,%) [0:0]) begin
      w10_7_reg <= (1'b0);
    end else begin
      w10_7_reg <= w29_1;
    end
  end
  assign w10_7 = w10_7_reg;
  // register end

  assign w13_4 = c$w13_app_arg_1 & (cin_19[(64'sd0)]);

  assign c$w19_app_arg = ~ w13_4;

  assign \c$_INTERNAL_.w18_1  = (~ ((~ ((~ ((cin_19[(64'sd6)]) & \c$_INTERNAL_.w18_app_arg_0 )) & (~ (cin_19[(64'sd7)])))) & (~ ((~ (cin_19[(64'sd8)])) & (~ \c$_INTERNAL_.w18_app_arg_0 ))))) & \c$_INTERNAL_.w18_app_arg_1 ;

  assign w22_0 = w11_7 & w10_7;

  assign c$w34_app_arg = ~ w22_0;

  assign w19_5 = \c$_INTERNAL_.w18_1  & c$w19_app_arg;

  assign c$cout_app_arg_54 = w19_5;

  assign w34_0 = c$w34_app_arg & (~ w19_5);

  assign c$cout_app_arg_55 = w34_0;

  assign dt_124 = (c_counter_2 + 8'd1) % 8'd42;

  assign ds1_1 = result_261[15:0];

  assign result_220 = {c$cout_app_arg_55,({c$cout_app_arg_54,({c$cout_app_arg_55,({c$cout_app_arg_54,({(c$w34_app_arg),({1'b0,({(((~ w32_2) & c$w34_app_arg)),({(w32_2),({1'b0,({((~ ((~ w29_1) & c$cout_app_arg_53))),({(((~ \_INTERNAL_.w27 ) & \c$_INTERNAL_.w18_1 )),({1'b0,({((~ ((~ (w12_6 & \c$_INTERNAL_.w18_app_arg_1 )) & c$cout_app_arg_53))),({((\c$_INTERNAL_.w18_1  & w13_4)),((w19_5 & (~ w12_6)))})})})})})})})})})})})})})};

  assign dt_125 = (c_prescaler_1 + 8'd1) % 8'd255;

  assign dt_126_selection = result_261[16:0];

  always @(*) begin
    case(dt_126_selection[16:16])
      1'b0 : dt_126 = 8'b00000000;
      default : dt_126 = ds1_1[15:8];
    endcase
  end

  assign dt_127_selection = result_261[16:0];

  always @(*) begin
    case(dt_127_selection[16:16])
      1'b0 : dt_127 = 8'b00000000;
      default : dt_127 = ds1_1[7:0];
    endcase
  end

  // register begin
  reg  dt_128_reg = (1'b1);
  always @(posedge \$d(%,%) [1:1] or posedge \$d(%,%) [0:0]) begin : dt_128_register
    if (\$d(%,%) [0:0]) begin
      dt_128_reg <= (1'b1);
    end else begin
      dt_128_reg <= result_223;
    end
  end
  assign dt_128 = dt_128_reg;
  // register end

  // register begin
  reg  dt_129_reg = 1'b0;
  always @(posedge \$d(%,%) [1:1] or posedge \$d(%,%) [0:0]) begin : dt_129_register
    if (\$d(%,%) [0:0]) begin
      dt_129_reg <= 1'b0;
    end else begin
      dt_129_reg <= result_224;
    end
  end
  assign dt_129 = dt_129_reg;
  // register end

  // register begin
  reg [7:0] dt_130_reg = 8'b00000000;
  always @(posedge \$d(%,%) [1:1] or posedge \$d(%,%) [0:0]) begin : dt_130_register
    if (\$d(%,%) [0:0]) begin
      dt_130_reg <= 8'b00000000;
    end else begin
      dt_130_reg <= result_225;
    end
  end
  assign dt_130 = dt_130_reg;
  // register end

  // register begin
  reg [7:0] dt_131_reg = 8'b00000000;
  always @(posedge \$d(%,%) [1:1] or posedge \$d(%,%) [0:0]) begin : dt_131_register
    if (\$d(%,%) [0:0]) begin
      dt_131_reg <= 8'b00000000;
    end else begin
      dt_131_reg <= result_226;
    end
  end
  assign dt_131 = dt_131_reg;
  // register end

  // register begin
  reg [7:0] c_prescaler_1_reg = 8'd0;
  always @(posedge \$d(%,%) [1:1] or posedge \$d(%,%) [0:0]) begin : c_prescaler_1_register
    if (\$d(%,%) [0:0]) begin
      c_prescaler_1_reg <= 8'd0;
    end else begin
      c_prescaler_1_reg <= result_221;
    end
  end
  assign c_prescaler_1 = c_prescaler_1_reg;
  // register end

  // register begin
  reg [7:0] c_counter_2_reg = 8'd0;
  always @(posedge \$d(%,%) [1:1] or posedge \$d(%,%) [0:0]) begin : c_counter_2_register
    if (\$d(%,%) [0:0]) begin
      c_counter_2_reg <= 8'd0;
    end else begin
      c_counter_2_reg <= result_222;
    end
  end
  assign c_counter_2 = c_counter_2_reg;
  // register end

  assign bs_80 = {((result_220[(64'sd9)])),((result_220[(64'sd10)]))};

  assign bs_81 = {((result_220[(64'sd0)])),({((result_220[(64'sd1)])),((result_220[(64'sd2)]))})};

  assign bs_82 = {((result_220[(64'sd3)])),({((result_220[(64'sd4)])),((result_220[(64'sd5)]))})};

  assign bs_83 = {((result_220[(64'sd6)])),({((result_220[(64'sd7)])),((result_220[(64'sd8)]))})};

  assign bs_84 = {((result_220[(64'sd11)])),((result_220[(64'sd12)]))};

  assign bs_85 = {((result_220[(64'sd13)])),((result_220[(64'sd14)]))};

  assign c$vecflat_252 = {c_counter_2
                         ,8'd1
                         ,dt_124};

  // index begin
  wire [7:0] vec_259 [0:3-1];

  genvar i_261;
  generate
  for (i_261=0; i_261 < 3; i_261=i_261+1) begin : mk_array_259
    assign vec_259[(3-1)-i_261] = c$vecflat_252[i_261*8+:8];
  end
  endgenerate

  assign \c$_INTERNAL_.o_counter_case_alt_5  = vec_259[(64'sd0)];
  // index end

  assign c$vecflat_253 = {c_counter_2
                         ,8'd1
                         ,dt_124};

  // index begin
  wire [7:0] vec_260 [0:3-1];

  genvar i_262;
  generate
  for (i_262=0; i_262 < 3; i_262=i_262+1) begin : mk_array_260
    assign vec_260[(3-1)-i_262] = c$vecflat_253[i_262*8+:8];
  end
  endgenerate

  assign \c$_INTERNAL_.o_counter_case_alt_6  = vec_260[(64'sd1)];
  // index end

  assign c$vecflat_254 = {dt_128,1'b1,1'b0};

  // index begin
  wire  vec_261 [0:3-1];

  genvar i_263;
  generate
  for (i_263=0; i_263 < 3; i_263=i_263+1) begin : mk_array_261
    assign vec_261[(3-1)-i_263] = c$vecflat_254[i_263*1+:1];
  end
  endgenerate

  assign c$o_cs_case_alt = vec_261[(64'sd0)];
  // index end

  assign c$vecflat_255 = {dt_128,1'b1,1'b0};

  // index begin
  wire  vec_262 [0:3-1];

  genvar i_264;
  generate
  for (i_264=0; i_264 < 3; i_264=i_264+1) begin : mk_array_262
    assign vec_262[(3-1)-i_264] = c$vecflat_255[i_264*1+:1];
  end
  endgenerate

  assign c$o_cs_case_alt_0 = vec_262[(64'sd1)];
  // index end

  assign c$vecflat_256 = {dt_129,1'b0,1'b1};

  // index begin
  wire  vec_263 [0:3-1];

  genvar i_265;
  generate
  for (i_265=0; i_265 < 3; i_265=i_265+1) begin : mk_array_263
    assign vec_263[(3-1)-i_265] = c$vecflat_256[i_265*1+:1];
  end
  endgenerate

  assign c$o_finished_case_alt = vec_263[(64'sd0)];
  // index end

  assign c$vecflat_257 = {dt_129,1'b0,1'b1};

  // index begin
  wire  vec_264 [0:3-1];

  genvar i_266;
  generate
  for (i_266=0; i_266 < 3; i_266=i_266+1) begin : mk_array_264
    assign vec_264[(3-1)-i_266] = c$vecflat_257[i_266*1+:1];
  end
  endgenerate

  assign c$o_finished_case_alt_0 = vec_264[(64'sd1)];
  // index end

  assign c$vecflat_258 = {c_prescaler_1,dt_125};

  // index begin
  wire [7:0] vec_265 [0:2-1];

  genvar i_267;
  generate
  for (i_267=0; i_267 < 2; i_267=i_267+1) begin : mk_array_265
    assign vec_265[(2-1)-i_267] = c$vecflat_258[i_267*8+:8];
  end
  endgenerate

  assign \c$_INTERNAL_.o_prescaler_case_alt_3  = vec_265[(64'sd0)];
  // index end

  assign c$vecflat_259 = {c_prescaler_1,dt_125};

  // index begin
  wire [7:0] vec_266 [0:2-1];

  genvar i_268;
  generate
  for (i_268=0; i_268 < 2; i_268=i_268+1) begin : mk_array_266
    assign vec_266[(2-1)-i_268] = c$vecflat_259[i_268*8+:8];
  end
  endgenerate

  assign \c$_INTERNAL_.o_prescaler_case_alt_4  = vec_266[(64'sd1)];
  // index end

  assign \c$_INTERNAL_.o_counter_case_alt_7_selection_res  = (bs_81[(64'sd1)]) == (1'b1);

  always @(*) begin
    if(\c$_INTERNAL_.o_counter_case_alt_7_selection_res )
      \c$_INTERNAL_.o_counter_case_alt_7  = \c$_INTERNAL_.o_counter_case_alt_6 ;
    else
      \c$_INTERNAL_.o_counter_case_alt_7  = \c$_INTERNAL_.o_counter_case_alt_5 ;
  end

  assign c$vecflat_260 = {c_counter_2
                         ,8'd1
                         ,dt_124};

  // index begin
  wire [7:0] vec_267 [0:3-1];

  genvar i_269;
  generate
  for (i_269=0; i_269 < 3; i_269=i_269+1) begin : mk_array_267
    assign vec_267[(3-1)-i_269] = c$vecflat_260[i_269*8+:8];
  end
  endgenerate

  assign \c$_INTERNAL_.o_counter_case_alt_8  = vec_267[(64'sd2)];
  // index end

  assign c$o_cs_case_alt_1_selection_res = (bs_82[(64'sd1)]) == (1'b1);

  always @(*) begin
    if(c$o_cs_case_alt_1_selection_res)
      c$o_cs_case_alt_1 = c$o_cs_case_alt_0;
    else
      c$o_cs_case_alt_1 = c$o_cs_case_alt;
  end

  assign c$vecflat_261 = {dt_128,1'b1,1'b0};

  // index begin
  wire  vec_268 [0:3-1];

  genvar i_270;
  generate
  for (i_270=0; i_270 < 3; i_270=i_270+1) begin : mk_array_268
    assign vec_268[(3-1)-i_270] = c$vecflat_261[i_270*1+:1];
  end
  endgenerate

  assign c$o_cs_case_alt_2 = vec_268[(64'sd2)];
  // index end

  assign c$o_finished_case_alt_1_selection_res = (bs_83[(64'sd1)]) == (1'b1);

  always @(*) begin
    if(c$o_finished_case_alt_1_selection_res)
      c$o_finished_case_alt_1 = c$o_finished_case_alt_0;
    else
      c$o_finished_case_alt_1 = c$o_finished_case_alt;
  end

  assign c$vecflat_262 = {dt_129,1'b0,1'b1};

  // index begin
  wire  vec_269 [0:3-1];

  genvar i_271;
  generate
  for (i_271=0; i_271 < 3; i_271=i_271+1) begin : mk_array_269
    assign vec_269[(3-1)-i_271] = c$vecflat_262[i_271*1+:1];
  end
  endgenerate

  assign c$o_finished_case_alt_2 = vec_269[(64'sd2)];
  // index end

  assign c$vecflat_263 = {dt_130,dt_126};

  // index begin
  wire [7:0] vec_270 [0:2-1];

  genvar i_272;
  generate
  for (i_272=0; i_272 < 2; i_272=i_272+1) begin : mk_array_270
    assign vec_270[(2-1)-i_272] = c$vecflat_263[i_272*8+:8];
  end
  endgenerate

  assign c$o_writeaddress_case_alt = vec_270[(64'sd0)];
  // index end

  assign c$vecflat_264 = {dt_130,dt_126};

  // index begin
  wire [7:0] vec_271 [0:2-1];

  genvar i_273;
  generate
  for (i_273=0; i_273 < 2; i_273=i_273+1) begin : mk_array_271
    assign vec_271[(2-1)-i_273] = c$vecflat_264[i_273*8+:8];
  end
  endgenerate

  assign c$o_writeaddress_case_alt_0 = vec_271[(64'sd1)];
  // index end

  assign c$vecflat_265 = {dt_131,dt_127};

  // index begin
  wire [7:0] vec_272 [0:2-1];

  genvar i_274;
  generate
  for (i_274=0; i_274 < 2; i_274=i_274+1) begin : mk_array_272
    assign vec_272[(2-1)-i_274] = c$vecflat_265[i_274*8+:8];
  end
  endgenerate

  assign c$o_writedata_case_alt = vec_272[(64'sd0)];
  // index end

  assign c$vecflat_266 = {dt_131,dt_127};

  // index begin
  wire [7:0] vec_273 [0:2-1];

  genvar i_275;
  generate
  for (i_275=0; i_275 < 2; i_275=i_275+1) begin : mk_array_273
    assign vec_273[(2-1)-i_275] = c$vecflat_266[i_275*8+:8];
  end
  endgenerate

  assign c$o_writedata_case_alt_0 = vec_273[(64'sd1)];
  // index end

  assign result_221_selection_res = (bs_80[(64'sd0)]) == (1'b1);

  always @(*) begin
    if(result_221_selection_res)
      result_221 = \c$_INTERNAL_.o_prescaler_case_alt_4 ;
    else
      result_221 = \c$_INTERNAL_.o_prescaler_case_alt_3 ;
  end

  assign result_222_selection_res = (bs_81[(64'sd0)]) == (1'b1);

  always @(*) begin
    if(result_222_selection_res)
      result_222 = \c$_INTERNAL_.o_counter_case_alt_8 ;
    else
      result_222 = \c$_INTERNAL_.o_counter_case_alt_7 ;
  end

  assign result_223_selection_res = (bs_82[(64'sd0)]) == (1'b1);

  always @(*) begin
    if(result_223_selection_res)
      result_223 = c$o_cs_case_alt_2;
    else
      result_223 = c$o_cs_case_alt_1;
  end

  assign result_224_selection_res = (bs_83[(64'sd0)]) == (1'b1);

  always @(*) begin
    if(result_224_selection_res)
      result_224 = c$o_finished_case_alt_2;
    else
      result_224 = c$o_finished_case_alt_1;
  end

  assign result_225_selection_res = (bs_84[(64'sd0)]) == (1'b1);

  always @(*) begin
    if(result_225_selection_res)
      result_225 = c$o_writeaddress_case_alt_0;
    else
      result_225 = c$o_writeaddress_case_alt;
  end

  assign result_226_selection_res = (bs_85[(64'sd0)]) == (1'b1);

  always @(*) begin
    if(result_226_selection_res)
      result_226 = c$o_writedata_case_alt_0;
    else
      result_226 = c$o_writedata_case_alt;
  end

  assign result_227 = {result_222
                      ,result_223
                      ,result_224
                      ,result_221
                      ,result_225
                      ,result_226};

  assign result_228 = {{result_202
                       ,result_227[25:25]
                       ,result_203}
                      ,result_227[24:24]};

  assign counter_0 = result_244[41:34];

  assign result_229_selection_res = (result_230[(64'sd0)]) == (1'b1);

  always @(*) begin
    if(result_229_selection_res)
      result_229 = c$o_sdi_case_alt_5;
    else
      result_229 = c$o_sdi_case_alt_6;
  end

  assign c$vecflat_267 = {result_231,1'b1,dt_132};

  // index begin
  wire  vec_274 [0:3-1];

  genvar i_276;
  generate
  for (i_276=0; i_276 < 3; i_276=i_276+1) begin : mk_array_274
    assign vec_274[(3-1)-i_276] = c$vecflat_267[i_276*1+:1];
  end
  endgenerate

  assign c$o_sdi_case_alt_5 = vec_274[(64'sd2)];
  // index end

  assign c$o_sdi_case_alt_6_selection_res = (result_230[(64'sd1)]) == (1'b1);

  always @(*) begin
    if(c$o_sdi_case_alt_6_selection_res)
      c$o_sdi_case_alt_6 = c$o_sdi_case_alt_7;
    else
      c$o_sdi_case_alt_6 = c$o_sdi_case_alt_8;
  end

  assign c$vecflat_268 = {result_231,1'b1,dt_132};

  // index begin
  wire  vec_275 [0:3-1];

  genvar i_277;
  generate
  for (i_277=0; i_277 < 3; i_277=i_277+1) begin : mk_array_275
    assign vec_275[(3-1)-i_277] = c$vecflat_268[i_277*1+:1];
  end
  endgenerate

  assign c$o_sdi_case_alt_7 = vec_275[(64'sd1)];
  // index end

  assign c$vecflat_269 = {result_231,1'b1,dt_132};

  // index begin
  wire  vec_276 [0:3-1];

  genvar i_278;
  generate
  for (i_278=0; i_278 < 3; i_278=i_278+1) begin : mk_array_276
    assign vec_276[(3-1)-i_278] = c$vecflat_269[i_278*1+:1];
  end
  endgenerate

  assign c$o_sdi_case_alt_8 = vec_276[(64'sd0)];
  // index end

  assign result_230 = {((cout_2[(64'sd0)])),({((cout_2[(64'sd1)])),((cout_2[(64'sd2)]))})};

  always @(*) begin
    case(ds_2)
      8'd0 : result_231 = c$dt_case_alt_26;
      8'd1 : result_231 = c$dt_case_alt_25;
      8'd2 : result_231 = c$dt_case_alt_24;
      8'd3 : result_231 = c$dt_case_alt_23;
      8'd4 : result_231 = c$dt_case_alt_22;
      8'd5 : result_231 = c$dt_case_alt_21;
      8'd6 : result_231 = c$dt_case_alt_20;
      8'd7 : result_231 = c$dt_case_alt_19;
      default : result_231 = 1'b0;
    endcase
  end

  assign ds_2 = 8'd8 - (counter_0 / 8'd2);

  assign c$bv_26 = result_244[24:17];

  assign c$dt_case_alt_19_selection_res = (c$bv_26[(64'sd7)]) == (1'b1);

  always @(*) begin
    if(c$dt_case_alt_19_selection_res)
      c$dt_case_alt_19 = 1'b1;
    else
      c$dt_case_alt_19 = 1'b0;
  end

  assign c$bv_27 = result_244[24:17];

  assign c$dt_case_alt_20_selection_res = (c$bv_27[(64'sd6)]) == (1'b1);

  always @(*) begin
    if(c$dt_case_alt_20_selection_res)
      c$dt_case_alt_20 = 1'b1;
    else
      c$dt_case_alt_20 = 1'b0;
  end

  assign c$bv_28 = result_244[24:17];

  assign c$dt_case_alt_21_selection_res = (c$bv_28[(64'sd5)]) == (1'b1);

  always @(*) begin
    if(c$dt_case_alt_21_selection_res)
      c$dt_case_alt_21 = 1'b1;
    else
      c$dt_case_alt_21 = 1'b0;
  end

  assign c$bv_29 = result_244[24:17];

  assign c$dt_case_alt_22_selection_res = (c$bv_29[(64'sd4)]) == (1'b1);

  always @(*) begin
    if(c$dt_case_alt_22_selection_res)
      c$dt_case_alt_22 = 1'b1;
    else
      c$dt_case_alt_22 = 1'b0;
  end

  assign c$bv_30 = result_244[24:17];

  assign c$dt_case_alt_23_selection_res = (c$bv_30[(64'sd3)]) == (1'b1);

  always @(*) begin
    if(c$dt_case_alt_23_selection_res)
      c$dt_case_alt_23 = 1'b1;
    else
      c$dt_case_alt_23 = 1'b0;
  end

  assign c$bv_31 = result_244[24:17];

  assign c$dt_case_alt_24_selection_res = (c$bv_31[(64'sd2)]) == (1'b1);

  always @(*) begin
    if(c$dt_case_alt_24_selection_res)
      c$dt_case_alt_24 = 1'b1;
    else
      c$dt_case_alt_24 = 1'b0;
  end

  assign c$bv_32 = result_244[24:17];

  assign c$dt_case_alt_25_selection_res = (c$bv_32[(64'sd1)]) == (1'b1);

  always @(*) begin
    if(c$dt_case_alt_25_selection_res)
      c$dt_case_alt_25 = 1'b1;
    else
      c$dt_case_alt_25 = 1'b0;
  end

  assign c$bv_33 = result_244[24:17];

  assign c$dt_case_alt_26_selection_res = (c$bv_33[(64'sd0)]) == (1'b1);

  always @(*) begin
    if(c$dt_case_alt_26_selection_res)
      c$dt_case_alt_26 = 1'b1;
    else
      c$dt_case_alt_26 = 1'b0;
  end

  assign cout_2 = {1'b0,({((~ result_232)),(result_232)})};

  // register begin
  reg  dt_132_reg = (1'b0);
  always @(posedge \$d(%,%) [1:1] or posedge \$d(%,%) [0:0]) begin : dt_132_register
    if (\$d(%,%) [0:0]) begin
      dt_132_reg <= (1'b0);
    end else begin
      dt_132_reg <= result_229;
    end
  end
  assign dt_132 = dt_132_reg;
  // register end

  assign result_232 = (cin_20[(64'sd4)]) & (cin_20[(64'sd2)]);

  assign cin_20 = {result_233,({result_234,({result_235,({result_237,result_236})})})};

  always @(*) begin
    if(b_65)
      result_233 = 1'b1;
    else
      result_233 = 1'b0;
  end

  always @(*) begin
    if(b_66)
      result_234 = 1'b1;
    else
      result_234 = 1'b0;
  end

  assign b_65 = counter_0 <= 8'd17;

  always @(*) begin
    if(b_67)
      result_235 = 1'b1;
    else
      result_235 = 1'b0;
  end

  assign b_66 = counter_0 >= 8'd24;

  always @(*) begin
    if(b_68)
      result_236 = 1'b1;
    else
      result_236 = 1'b0;
  end

  always @(*) begin
    if(b_69)
      result_237 = 1'b1;
    else
      result_237 = 1'b0;
  end

  assign b_67 = counter_0 >= 8'd4;

  assign b_68 = counter_0 == 8'd3;

  assign b_69 = counter_0 == 8'd2;

  assign result_238_selection_res = (result_239[(64'sd0)]) == (1'b1);

  always @(*) begin
    if(result_238_selection_res)
      result_238 = c$o_spc_case_alt_3;
    else
      result_238 = c$o_spc_case_alt_4;
  end

  assign c$vecflat_270 = {1'b1,1'b0,dt_133};

  // index begin
  wire  vec_277 [0:3-1];

  genvar i_279;
  generate
  for (i_279=0; i_279 < 3; i_279=i_279+1) begin : mk_array_277
    assign vec_277[(3-1)-i_279] = c$vecflat_270[i_279*1+:1];
  end
  endgenerate

  assign c$o_spc_case_alt_3 = vec_277[(64'sd2)];
  // index end

  assign c$o_spc_case_alt_4_selection_res = (result_239[(64'sd1)]) == (1'b1);

  always @(*) begin
    if(c$o_spc_case_alt_4_selection_res)
      c$o_spc_case_alt_4 = c$o_spc_case_alt_5;
    else
      c$o_spc_case_alt_4 = c$o_spc_case_alt_6;
  end

  assign c$vecflat_271 = {1'b1,1'b0,dt_133};

  // index begin
  wire  vec_278 [0:3-1];

  genvar i_280;
  generate
  for (i_280=0; i_280 < 3; i_280=i_280+1) begin : mk_array_278
    assign vec_278[(3-1)-i_280] = c$vecflat_271[i_280*1+:1];
  end
  endgenerate

  assign c$o_spc_case_alt_5 = vec_278[(64'sd1)];
  // index end

  assign c$vecflat_272 = {1'b1,1'b0,dt_133};

  // index begin
  wire  vec_279 [0:3-1];

  genvar i_281;
  generate
  for (i_281=0; i_281 < 3; i_281=i_281+1) begin : mk_array_279
    assign vec_279[(3-1)-i_281] = c$vecflat_272[i_281*1+:1];
  end
  endgenerate

  assign c$o_spc_case_alt_6 = vec_279[(64'sd0)];
  // index end

  assign result_239 = {((cout_3[(64'sd0)])),({((cout_3[(64'sd1)])),((cout_3[(64'sd2)]))})};

  assign cout_3 = {1'b0,({(result_240),((~ result_240))})};

  // register begin
  reg  dt_133_reg = (1'b1);
  always @(posedge \$d(%,%) [1:1] or posedge \$d(%,%) [0:0]) begin : dt_133_register
    if (\$d(%,%) [0:0]) begin
      dt_133_reg <= (1'b1);
    end else begin
      dt_133_reg <= result_238;
    end
  end
  assign dt_133 = dt_133_reg;
  // register end

  assign result_240 = (~ (cin_21[(64'sd0)])) & (~ ((~ (cin_21[(64'sd1)])) & (cin_21[(64'sd2)])));

  assign cin_21 = {result_241,({result_243,result_242})};

  always @(*) begin
    if(b_70)
      result_241 = 1'b1;
    else
      result_241 = 1'b0;
  end

  always @(*) begin
    if(b_71)
      result_242 = 1'b1;
    else
      result_242 = 1'b0;
  end

  always @(*) begin
    if(b_72)
      result_243 = 1'b1;
    else
      result_243 = 1'b0;
  end

  assign b_70 = counter_0 < 8'd34;

  assign b_71 = counter_0 == 8'd0;

  assign b_72 = (counter_0 % 8'd2) == 8'd0;

  assign result_244 = {result_249
                      ,result_248
                      ,result_250
                      ,result_247
                      ,result_245
                      ,result_246};

  assign result_245_selection_res = (bs_86[(64'sd0)]) == (1'b1);

  always @(*) begin
    if(result_245_selection_res)
      result_245 = c$o_readdata_case_alt;
    else
      result_245 = c$o_readdata_case_alt_0;
  end

  assign result_246_selection_res = (bs_87[(64'sd0)]) == (1'b1);

  always @(*) begin
    if(result_246_selection_res)
      result_246 = \c$_INTERNAL_.o_readdatatemp_case_alt ;
    else
      result_246 = \c$_INTERNAL_.o_readdatatemp_case_alt_0 ;
  end

  assign result_247_selection_res = (bs_88[(64'sd0)]) == (1'b1);

  always @(*) begin
    if(result_247_selection_res)
      result_247 = c$o_readaddress_case_alt;
    else
      result_247 = c$o_readaddress_case_alt_0;
  end

  assign result_248_selection_res = (bs_89[(64'sd0)]) == (1'b1);

  always @(*) begin
    if(result_248_selection_res)
      result_248 = c$o_cs_case_alt_3;
    else
      result_248 = c$o_cs_case_alt_4;
  end

  assign result_249_selection_res = (bs_90[(64'sd0)]) == (1'b1);

  always @(*) begin
    if(result_249_selection_res)
      result_249 = \c$_INTERNAL_.o_counter_case_alt_9 ;
    else
      result_249 = \c$_INTERNAL_.o_counter_case_alt_10 ;
  end

  assign result_250_selection_res = (bs_91[(64'sd0)]) == (1'b1);

  always @(*) begin
    if(result_250_selection_res)
      result_250 = \c$_INTERNAL_.o_prescaler_case_alt_5 ;
    else
      result_250 = \c$_INTERNAL_.o_prescaler_case_alt_6 ;
  end

  assign c$vecflat_273 = {dt_134
                         ,{1'b0,8'bxxxxxxxx}
                         ,dt_139};

  // index begin
  wire [8:0] vec_280 [0:3-1];

  genvar i_282;
  generate
  for (i_282=0; i_282 < 3; i_282=i_282+1) begin : mk_array_280
    assign vec_280[(3-1)-i_282] = c$vecflat_273[i_282*9+:9];
  end
  endgenerate

  assign c$o_readdata_case_alt = vec_280[(64'sd2)];
  // index end

  assign c$o_readdata_case_alt_0_selection_res = (bs_86[(64'sd1)]) == (1'b1);

  always @(*) begin
    if(c$o_readdata_case_alt_0_selection_res)
      c$o_readdata_case_alt_0 = c$o_readdata_case_alt_1;
    else
      c$o_readdata_case_alt_0 = c$o_readdata_case_alt_2;
  end

  assign c$vecflat_274 = {c_readdatatemp
                         ,8'b00000000
                         ,dt_140};

  // index begin
  wire [7:0] vec_281 [0:3-1];

  genvar i_283;
  generate
  for (i_283=0; i_283 < 3; i_283=i_283+1) begin : mk_array_281
    assign vec_281[(3-1)-i_283] = c$vecflat_274[i_283*8+:8];
  end
  endgenerate

  assign \c$_INTERNAL_.o_readdatatemp_case_alt  = vec_281[(64'sd2)];
  // index end

  assign \c$_INTERNAL_.o_readdatatemp_case_alt_0_selection_res  = (bs_87[(64'sd1)]) == (1'b1);

  always @(*) begin
    if(\c$_INTERNAL_.o_readdatatemp_case_alt_0_selection_res )
      \c$_INTERNAL_.o_readdatatemp_case_alt_0  = \c$_INTERNAL_.o_readdatatemp_case_alt_1 ;
    else
      \c$_INTERNAL_.o_readdatatemp_case_alt_0  = \c$_INTERNAL_.o_readdatatemp_case_alt_2 ;
  end

  assign c$vecflat_275 = {dt_135,dt_137};

  // index begin
  wire [7:0] vec_282 [0:2-1];

  genvar i_284;
  generate
  for (i_284=0; i_284 < 2; i_284=i_284+1) begin : mk_array_282
    assign vec_282[(2-1)-i_284] = c$vecflat_275[i_284*8+:8];
  end
  endgenerate

  assign c$o_readaddress_case_alt = vec_282[(64'sd1)];
  // index end

  assign c$vecflat_276 = {dt_135,dt_137};

  // index begin
  wire [7:0] vec_283 [0:2-1];

  genvar i_285;
  generate
  for (i_285=0; i_285 < 2; i_285=i_285+1) begin : mk_array_283
    assign vec_283[(2-1)-i_285] = c$vecflat_276[i_285*8+:8];
  end
  endgenerate

  assign c$o_readaddress_case_alt_0 = vec_283[(64'sd0)];
  // index end

  assign c$vecflat_277 = {dt_136,1'b1,1'b0};

  // index begin
  wire  vec_284 [0:3-1];

  genvar i_286;
  generate
  for (i_286=0; i_286 < 3; i_286=i_286+1) begin : mk_array_284
    assign vec_284[(3-1)-i_286] = c$vecflat_277[i_286*1+:1];
  end
  endgenerate

  assign c$o_cs_case_alt_3 = vec_284[(64'sd2)];
  // index end

  assign c$o_cs_case_alt_4_selection_res = (bs_89[(64'sd1)]) == (1'b1);

  always @(*) begin
    if(c$o_cs_case_alt_4_selection_res)
      c$o_cs_case_alt_4 = c$o_cs_case_alt_5;
    else
      c$o_cs_case_alt_4 = c$o_cs_case_alt_6;
  end

  assign c$vecflat_278 = {c_counter_3
                         ,8'd1
                         ,dt_141};

  // index begin
  wire [7:0] vec_285 [0:3-1];

  genvar i_287;
  generate
  for (i_287=0; i_287 < 3; i_287=i_287+1) begin : mk_array_285
    assign vec_285[(3-1)-i_287] = c$vecflat_278[i_287*8+:8];
  end
  endgenerate

  assign \c$_INTERNAL_.o_counter_case_alt_9  = vec_285[(64'sd2)];
  // index end

  assign \c$_INTERNAL_.o_counter_case_alt_10_selection_res  = (bs_90[(64'sd1)]) == (1'b1);

  always @(*) begin
    if(\c$_INTERNAL_.o_counter_case_alt_10_selection_res )
      \c$_INTERNAL_.o_counter_case_alt_10  = \c$_INTERNAL_.o_counter_case_alt_11 ;
    else
      \c$_INTERNAL_.o_counter_case_alt_10  = \c$_INTERNAL_.o_counter_case_alt_12 ;
  end

  assign c$vecflat_279 = {c_prescaler_2,dt_138};

  // index begin
  wire [7:0] vec_286 [0:2-1];

  genvar i_288;
  generate
  for (i_288=0; i_288 < 2; i_288=i_288+1) begin : mk_array_286
    assign vec_286[(2-1)-i_288] = c$vecflat_279[i_288*8+:8];
  end
  endgenerate

  assign \c$_INTERNAL_.o_prescaler_case_alt_5  = vec_286[(64'sd1)];
  // index end

  assign c$vecflat_280 = {c_prescaler_2,dt_138};

  // index begin
  wire [7:0] vec_287 [0:2-1];

  genvar i_289;
  generate
  for (i_289=0; i_289 < 2; i_289=i_289+1) begin : mk_array_287
    assign vec_287[(2-1)-i_289] = c$vecflat_280[i_289*8+:8];
  end
  endgenerate

  assign \c$_INTERNAL_.o_prescaler_case_alt_6  = vec_287[(64'sd0)];
  // index end

  assign c$vecflat_281 = {dt_134
                         ,{1'b0,8'bxxxxxxxx}
                         ,dt_139};

  // index begin
  wire [8:0] vec_288 [0:3-1];

  genvar i_290;
  generate
  for (i_290=0; i_290 < 3; i_290=i_290+1) begin : mk_array_288
    assign vec_288[(3-1)-i_290] = c$vecflat_281[i_290*9+:9];
  end
  endgenerate

  assign c$o_readdata_case_alt_1 = vec_288[(64'sd1)];
  // index end

  assign c$vecflat_282 = {dt_134
                         ,{1'b0,8'bxxxxxxxx}
                         ,dt_139};

  // index begin
  wire [8:0] vec_289 [0:3-1];

  genvar i_291;
  generate
  for (i_291=0; i_291 < 3; i_291=i_291+1) begin : mk_array_289
    assign vec_289[(3-1)-i_291] = c$vecflat_282[i_291*9+:9];
  end
  endgenerate

  assign c$o_readdata_case_alt_2 = vec_289[(64'sd0)];
  // index end

  assign c$vecflat_283 = {c_readdatatemp
                         ,8'b00000000
                         ,dt_140};

  // index begin
  wire [7:0] vec_290 [0:3-1];

  genvar i_292;
  generate
  for (i_292=0; i_292 < 3; i_292=i_292+1) begin : mk_array_290
    assign vec_290[(3-1)-i_292] = c$vecflat_283[i_292*8+:8];
  end
  endgenerate

  assign \c$_INTERNAL_.o_readdatatemp_case_alt_1  = vec_290[(64'sd1)];
  // index end

  assign c$vecflat_284 = {c_readdatatemp
                         ,8'b00000000
                         ,dt_140};

  // index begin
  wire [7:0] vec_291 [0:3-1];

  genvar i_293;
  generate
  for (i_293=0; i_293 < 3; i_293=i_293+1) begin : mk_array_291
    assign vec_291[(3-1)-i_293] = c$vecflat_284[i_293*8+:8];
  end
  endgenerate

  assign \c$_INTERNAL_.o_readdatatemp_case_alt_2  = vec_291[(64'sd0)];
  // index end

  assign c$vecflat_285 = {dt_136,1'b1,1'b0};

  // index begin
  wire  vec_292 [0:3-1];

  genvar i_294;
  generate
  for (i_294=0; i_294 < 3; i_294=i_294+1) begin : mk_array_292
    assign vec_292[(3-1)-i_294] = c$vecflat_285[i_294*1+:1];
  end
  endgenerate

  assign c$o_cs_case_alt_5 = vec_292[(64'sd1)];
  // index end

  assign c$vecflat_286 = {dt_136,1'b1,1'b0};

  // index begin
  wire  vec_293 [0:3-1];

  genvar i_295;
  generate
  for (i_295=0; i_295 < 3; i_295=i_295+1) begin : mk_array_293
    assign vec_293[(3-1)-i_295] = c$vecflat_286[i_295*1+:1];
  end
  endgenerate

  assign c$o_cs_case_alt_6 = vec_293[(64'sd0)];
  // index end

  assign c$vecflat_287 = {c_counter_3
                         ,8'd1
                         ,dt_141};

  // index begin
  wire [7:0] vec_294 [0:3-1];

  genvar i_296;
  generate
  for (i_296=0; i_296 < 3; i_296=i_296+1) begin : mk_array_294
    assign vec_294[(3-1)-i_296] = c$vecflat_287[i_296*8+:8];
  end
  endgenerate

  assign \c$_INTERNAL_.o_counter_case_alt_11  = vec_294[(64'sd1)];
  // index end

  assign c$vecflat_288 = {c_counter_3
                         ,8'd1
                         ,dt_141};

  // index begin
  wire [7:0] vec_295 [0:3-1];

  genvar i_297;
  generate
  for (i_297=0; i_297 < 3; i_297=i_297+1) begin : mk_array_295
    assign vec_295[(3-1)-i_297] = c$vecflat_288[i_297*8+:8];
  end
  endgenerate

  assign \c$_INTERNAL_.o_counter_case_alt_12  = vec_295[(64'sd0)];
  // index end

  assign bs_86 = {((result_251[(64'sd10)])),({((result_251[(64'sd11)])),((result_251[(64'sd12)]))})};

  assign bs_87 = {((result_251[(64'sd13)])),({((result_251[(64'sd14)])),((result_251[(64'sd15)]))})};

  assign bs_88 = {((result_251[(64'sd8)])),((result_251[(64'sd9)]))};

  assign bs_89 = {((result_251[(64'sd3)])),({((result_251[(64'sd4)])),((result_251[(64'sd5)]))})};

  assign bs_90 = {((result_251[(64'sd0)])),({((result_251[(64'sd1)])),((result_251[(64'sd2)]))})};

  assign bs_91 = {((result_251[(64'sd6)])),((result_251[(64'sd7)]))};

  // register begin
  reg [7:0] c_counter_3_reg = 8'd0;
  always @(posedge \$d(%,%) [1:1] or posedge \$d(%,%) [0:0]) begin : c_counter_3_register
    if (\$d(%,%) [0:0]) begin
      c_counter_3_reg <= 8'd0;
    end else begin
      c_counter_3_reg <= result_249;
    end
  end
  assign c_counter_3 = c_counter_3_reg;
  // register end

  // register begin
  reg [7:0] c_prescaler_2_reg = 8'd0;
  always @(posedge \$d(%,%) [1:1] or posedge \$d(%,%) [0:0]) begin : c_prescaler_2_register
    if (\$d(%,%) [0:0]) begin
      c_prescaler_2_reg <= 8'd0;
    end else begin
      c_prescaler_2_reg <= result_250;
    end
  end
  assign c_prescaler_2 = c_prescaler_2_reg;
  // register end

  // register begin
  reg [7:0] c_readdatatemp_reg = 8'b00000000;
  always @(posedge \$d(%,%) [1:1] or posedge \$d(%,%) [0:0]) begin : c_readdatatemp_register
    if (\$d(%,%) [0:0]) begin
      c_readdatatemp_reg <= 8'b00000000;
    end else begin
      c_readdatatemp_reg <= result_246;
    end
  end
  assign c_readdatatemp = c_readdatatemp_reg;
  // register end

  // register begin
  reg [8:0] dt_134_reg = {1'b0,8'bxxxxxxxx};
  always @(posedge \$d(%,%) [1:1] or posedge \$d(%,%) [0:0]) begin : dt_134_register
    if (\$d(%,%) [0:0]) begin
      dt_134_reg <= {1'b0,8'bxxxxxxxx};
    end else begin
      dt_134_reg <= result_245;
    end
  end
  assign dt_134 = dt_134_reg;
  // register end

  // register begin
  reg [7:0] dt_135_reg = 8'b00000000;
  always @(posedge \$d(%,%) [1:1] or posedge \$d(%,%) [0:0]) begin : dt_135_register
    if (\$d(%,%) [0:0]) begin
      dt_135_reg <= 8'b00000000;
    end else begin
      dt_135_reg <= result_247;
    end
  end
  assign dt_135 = dt_135_reg;
  // register end

  // register begin
  reg  dt_136_reg = (1'b1);
  always @(posedge \$d(%,%) [1:1] or posedge \$d(%,%) [0:0]) begin : dt_136_register
    if (\$d(%,%) [0:0]) begin
      dt_136_reg <= (1'b1);
    end else begin
      dt_136_reg <= result_248;
    end
  end
  assign dt_136 = dt_136_reg;
  // register end

  assign dt_137_selection = result_261[25:17];

  always @(*) begin
    case(dt_137_selection[8:8])
      1'b0 : dt_137 = 8'b00000000;
      default : dt_137 = x_5;
    endcase
  end

  assign dt_138 = (c_prescaler_2 + 8'd1) % 8'd255;

  assign result_251 = {((~ ((~ (w30_1 & c$cout_app_arg_56)) & (~ \c$_INTERNAL_.w35_0 )))),({((((~ c$cout_app_arg_59) & c$cout_app_arg_57) & c$cout_app_arg_56)),({(((c$cout_app_arg_56 & c$w11_app_arg_5) & (~ w30_1))),({(((~ w25) & c$cout_app_arg_58)),({(w25),({1'b0,({c$cout_app_arg_60,({(w15_3),({(c$cout_app_arg_58),({1'b0,({(\c$_INTERNAL_.w22_0 ),({(((~ \c$_INTERNAL_.w22_0 ) & c$cout_app_arg_58)),({1'b0,({((w11_8 & c$cout_app_arg_56)),({c$cout_app_arg_60,((w15_3 & (~ w11_8)))})})})})})})})})})})})})})})};

  assign dt_139 = {1'b1,c_readdatatemp};

  assign dt_140 = (c_readdatatemp << (64'sd1)) | ({7'b0000000,(SDO)});

  assign x_5 = result_261[24:17];

  assign dt_141 = (c_counter_3 + 8'd1) % 8'd36;

  assign c$cout_app_arg_56 = ~ w10_8;

  // register begin
  reg  w10_8_reg = (1'b0);
  always @(posedge \$d(%,%) [1:1] or posedge \$d(%,%) [0:0]) begin : w10_8_register
    if (\$d(%,%) [0:0]) begin
      w10_8_reg <= (1'b0);
    end else begin
      w10_8_reg <= \c$_INTERNAL_.w35_0 ;
    end
  end
  assign w10_8 = w10_8_reg;
  // register end

  assign \c$_INTERNAL_.w35_0  = c$cout_app_arg_58 & (~ \c$_INTERNAL_.w14_0 );

  assign c$cout_app_arg_57 = cin_22[(64'sd1)];

  assign cin_22 = {result_252,({result_253,({result_254,({result_255,({result_256,({result_257,({result_259,result_258})})})})})})};

  assign w30_1 = (~ ((~ (((~ (cin_22[(64'sd3)])) & c$w25_app_arg) & (cin_22[(64'sd7)]))) & c$w11_app_arg_5)) & c$cout_app_arg_59;

  assign w25 = (~ ((cin_22[(64'sd4)]) & c$w25_app_arg)) & \c$_INTERNAL_.w14_0 ;

  assign c$cout_app_arg_58 = ~ w17_5;

  assign c$cout_app_arg_59 = cin_22[(64'sd6)];

  assign w17_5 = w10_8 & w9_8;

  assign \c$_INTERNAL_.w14_0  = (~ (c$cout_app_arg_59 & c$cout_app_arg_57)) & c$cout_app_arg_56;

  assign c$cout_app_arg_60 = w18_4;

  always @(*) begin
    if(b_73)
      result_252 = 1'b1;
    else
      result_252 = 1'b0;
  end

  // register begin
  reg  w9_8_reg = (1'b0);
  always @(posedge \$d(%,%) [1:1] or posedge \$d(%,%) [0:0]) begin : w9_8_register
    if (\$d(%,%) [0:0]) begin
      w9_8_reg <= (1'b0);
    end else begin
      w9_8_reg <= \c$_INTERNAL_.w22_0 ;
    end
  end
  assign w9_8 = w9_8_reg;
  // register end

  assign w18_4 = c$cout_app_arg_58 & (~ w15_3);

  always @(*) begin
    if(b_74)
      result_253 = 1'b1;
    else
      result_253 = 1'b0;
  end

  assign b_73 = c_counter_3 < 8'd34;

  assign \c$_INTERNAL_.w22_0  = (\c$_INTERNAL_.w14_0  & (~ (cin_22[(64'sd5)]))) & (~ (c$w15_app_arg & (~ w9_8)));

  assign w15_3 = \c$_INTERNAL_.w14_0  & c$w15_app_arg;

  assign c$w25_app_arg = cin_22[(64'sd2)];

  always @(*) begin
    if(b_75)
      result_254 = 1'b1;
    else
      result_254 = 1'b0;
  end

  assign b_74 = c_counter_3 > 8'd18;

  assign c$w15_app_arg = ~ w12_7;

  always @(*) begin
    if(b_76)
      result_255 = 1'b1;
    else
      result_255 = 1'b0;
  end

  assign b_75 = c_counter_3 == 8'd34;

  assign w12_7 = c$cout_app_arg_57 & (cin_22[(64'sd0)]);

  always @(*) begin
    if(b_77)
      result_256 = 1'b1;
    else
      result_256 = 1'b0;
  end

  assign b_76 = c_counter_3 == 8'd35;

  always @(*) begin
    if(b_78)
      result_257 = 1'b1;
    else
      result_257 = 1'b0;
  end

  assign b_77 = (c_counter_3 % 8'd2) == 8'd0;

  always @(*) begin
    if(b_79)
      result_258 = 1'b1;
    else
      result_258 = 1'b0;
  end

  always @(*) begin
    if(b_80)
      result_259 = 1'b1;
    else
      result_259 = 1'b0;
  end

  assign b_78 = c_prescaler_2 == 8'd0;

  assign b_79_selection = result_261[25:17];

  always @(*) begin
    case(b_79_selection[8:8])
      1'b0 : b_79 = 1'b0;
      default : b_79 = 1'b1;
    endcase
  end

  assign b_80 = c_counter_3 == 8'd0;

  assign w11_8 = c$w25_app_arg & c$w11_app_arg_5;

  assign c$w11_app_arg_5 = ~ c$cout_app_arg_57;

  assign result_260 = {{result_229
                       ,result_244[33:33]
                       ,result_238}
                      ,result_244[16:8]};

  // register begin
  reg [8:0] c$_INTERNAL_ds2_app_arg_reg = {1'b0,8'bxxxxxxxx};
  always @(posedge \$d(%,%) [1:1] or posedge \$d(%,%) [0:0]) begin : c$_INTERNAL_ds2_app_arg_register
    if (\$d(%,%) [0:0]) begin
      c$_INTERNAL_ds2_app_arg_reg <= {1'b0,8'bxxxxxxxx};
    end else begin
      c$_INTERNAL_ds2_app_arg_reg <= result_260[8:0];
    end
  end
  assign \c$_INTERNAL_.ds2_app_arg  = c$_INTERNAL_ds2_app_arg_reg;
  // register end

  // register begin
  reg  c$_INTERNAL_ds2_app_arg_0_reg = 1'b0;
  always @(posedge \$d(%,%) [1:1] or posedge \$d(%,%) [0:0]) begin : c$_INTERNAL_ds2_app_arg_0_register
    if (\$d(%,%) [0:0]) begin
      c$_INTERNAL_ds2_app_arg_0_reg <= 1'b0;
    end else begin
      c$_INTERNAL_ds2_app_arg_0_reg <= result_228[0:0];
    end
  end
  assign \c$_INTERNAL_.ds2_app_arg_0  = c$_INTERNAL_ds2_app_arg_0_reg;
  // register end

  assign result_261 = {result_265
                      ,result_262
                      ,result_266
                      ,result_264
                      ,result_263};

  assign result_262_selection_res = (bs_92[(64'sd0)]) == (1'b1);

  always @(*) begin
    if(result_262_selection_res)
      result_262 = c$o_output_case_alt;
    else
      result_262 = c$o_output_case_alt_0;
  end

  assign result_263_selection_res = (bs_93[(64'sd0)]) == (1'b1);

  always @(*) begin
    if(result_263_selection_res)
      result_263 = c$o_spiWriteCtrl_case_alt;
    else
      result_263 = c$o_spiWriteCtrl_case_alt_0;
  end

  assign result_264_selection_res = (bs_94[(64'sd0)]) == (1'b1);

  always @(*) begin
    if(result_264_selection_res)
      result_264 = c$o_spiReadCtrl_case_alt;
    else
      result_264 = c$o_spiReadCtrl_case_alt_0;
  end

  assign result_265_selection_res = (bs_95[(64'sd0)]) == (1'b1);

  always @(*) begin
    if(result_265_selection_res)
      result_265 = \c$_INTERNAL_.o_lastCmd_case_alt ;
    else
      result_265 = \c$_INTERNAL_.o_lastCmd_case_alt_0 ;
  end

  assign result_266_selection_res = (bs_96[(64'sd0)]) == (1'b1);

  always @(*) begin
    if(result_266_selection_res)
      result_266 = c$o_sensorOut_case_alt;
    else
      result_266 = c$o_sensorOut_case_alt_0;
  end

  assign c$vecflat_289 = {dt_142
                         ,{2'b00,16'bxxxxxxxxxxxxxxxx}
                         ,dt_148
                         ,dt_151};

  // index begin
  wire [17:0] vec_296 [0:4-1];

  genvar i_298;
  generate
  for (i_298=0; i_298 < 4; i_298=i_298+1) begin : mk_array_296
    assign vec_296[(4-1)-i_298] = c$vecflat_289[i_298*18+:18];
  end
  endgenerate

  assign c$o_output_case_alt = vec_296[(64'sd3)];
  // index end

  assign c$o_output_case_alt_0_selection_res = (bs_92[(64'sd1)]) == (1'b1);

  always @(*) begin
    if(c$o_output_case_alt_0_selection_res)
      c$o_output_case_alt_0 = c$o_output_case_alt_1;
    else
      c$o_output_case_alt_0 = c$o_output_case_alt_2;
  end

  assign c$vecflat_290 = {dt_143
                         ,{1'b0,16'bxxxxxxxxxxxxxxxx}
                         ,dt_149};

  // index begin
  wire [16:0] vec_297 [0:3-1];

  genvar i_299;
  generate
  for (i_299=0; i_299 < 3; i_299=i_299+1) begin : mk_array_297
    assign vec_297[(3-1)-i_299] = c$vecflat_290[i_299*17+:17];
  end
  endgenerate

  assign c$o_spiWriteCtrl_case_alt = vec_297[(64'sd2)];
  // index end

  assign c$o_spiWriteCtrl_case_alt_0_selection_res = (bs_93[(64'sd1)]) == (1'b1);

  always @(*) begin
    if(c$o_spiWriteCtrl_case_alt_0_selection_res)
      c$o_spiWriteCtrl_case_alt_0 = c$o_spiWriteCtrl_case_alt_1;
    else
      c$o_spiWriteCtrl_case_alt_0 = c$o_spiWriteCtrl_case_alt_2;
  end

  assign c$vecflat_291 = {dt_144
                         ,{1'b0,8'bxxxxxxxx}
                         ,dt_150};

  // index begin
  wire [8:0] vec_298 [0:3-1];

  genvar i_300;
  generate
  for (i_300=0; i_300 < 3; i_300=i_300+1) begin : mk_array_298
    assign vec_298[(3-1)-i_300] = c$vecflat_291[i_300*9+:9];
  end
  endgenerate

  assign c$o_spiReadCtrl_case_alt = vec_298[(64'sd2)];
  // index end

  assign c$o_spiReadCtrl_case_alt_0_selection_res = (bs_94[(64'sd1)]) == (1'b1);

  always @(*) begin
    if(c$o_spiReadCtrl_case_alt_0_selection_res)
      c$o_spiReadCtrl_case_alt_0 = c$o_spiReadCtrl_case_alt_1;
    else
      c$o_spiReadCtrl_case_alt_0 = c$o_spiReadCtrl_case_alt_2;
  end

  assign c$vecflat_292 = {c$ds1_app_arg_0,dt_145};

  // index begin
  wire [17:0] vec_299 [0:2-1];

  genvar i_301;
  generate
  for (i_301=0; i_301 < 2; i_301=i_301+1) begin : mk_array_299
    assign vec_299[(2-1)-i_301] = c$vecflat_292[i_301*18+:18];
  end
  endgenerate

  assign \c$_INTERNAL_.o_lastCmd_case_alt  = vec_299[(64'sd1)];
  // index end

  assign c$vecflat_293 = {c$ds1_app_arg_0,dt_145};

  // index begin
  wire [17:0] vec_300 [0:2-1];

  genvar i_302;
  generate
  for (i_302=0; i_302 < 2; i_302=i_302+1) begin : mk_array_300
    assign vec_300[(2-1)-i_302] = c$vecflat_293[i_302*18+:18];
  end
  endgenerate

  assign \c$_INTERNAL_.o_lastCmd_case_alt_0  = vec_300[(64'sd0)];
  // index end

  assign c$vecflat_294 = {result_260[11:9]
                         ,{dt_146,dt_147}};

  // index begin
  wire [2:0] vec_301 [0:4-1];

  genvar i_303;
  generate
  for (i_303=0; i_303 < 4; i_303=i_303+1) begin : mk_array_301
    assign vec_301[(4-1)-i_303] = c$vecflat_294[i_303*3+:3];
  end
  endgenerate

  assign c$o_sensorOut_case_alt = vec_301[(64'sd3)];
  // index end

  assign c$o_sensorOut_case_alt_0_selection_res = (bs_96[(64'sd1)]) == (1'b1);

  always @(*) begin
    if(c$o_sensorOut_case_alt_0_selection_res)
      c$o_sensorOut_case_alt_0 = c$o_sensorOut_case_alt_1;
    else
      c$o_sensorOut_case_alt_0 = c$o_sensorOut_case_alt_2;
  end

  assign c$vecflat_295 = {dt_142
                         ,{2'b00,16'bxxxxxxxxxxxxxxxx}
                         ,dt_148
                         ,dt_151};

  // index begin
  wire [17:0] vec_302 [0:4-1];

  genvar i_304;
  generate
  for (i_304=0; i_304 < 4; i_304=i_304+1) begin : mk_array_302
    assign vec_302[(4-1)-i_304] = c$vecflat_295[i_304*18+:18];
  end
  endgenerate

  assign c$o_output_case_alt_1 = vec_302[(64'sd2)];
  // index end

  assign c$o_output_case_alt_2_selection_res = (bs_92[(64'sd2)]) == (1'b1);

  always @(*) begin
    if(c$o_output_case_alt_2_selection_res)
      c$o_output_case_alt_2 = c$o_output_case_alt_3;
    else
      c$o_output_case_alt_2 = c$o_output_case_alt_4;
  end

  assign c$vecflat_296 = {dt_143
                         ,{1'b0,16'bxxxxxxxxxxxxxxxx}
                         ,dt_149};

  // index begin
  wire [16:0] vec_303 [0:3-1];

  genvar i_305;
  generate
  for (i_305=0; i_305 < 3; i_305=i_305+1) begin : mk_array_303
    assign vec_303[(3-1)-i_305] = c$vecflat_296[i_305*17+:17];
  end
  endgenerate

  assign c$o_spiWriteCtrl_case_alt_1 = vec_303[(64'sd1)];
  // index end

  assign c$vecflat_297 = {dt_143
                         ,{1'b0,16'bxxxxxxxxxxxxxxxx}
                         ,dt_149};

  // index begin
  wire [16:0] vec_304 [0:3-1];

  genvar i_306;
  generate
  for (i_306=0; i_306 < 3; i_306=i_306+1) begin : mk_array_304
    assign vec_304[(3-1)-i_306] = c$vecflat_297[i_306*17+:17];
  end
  endgenerate

  assign c$o_spiWriteCtrl_case_alt_2 = vec_304[(64'sd0)];
  // index end

  assign c$vecflat_298 = {dt_144
                         ,{1'b0,8'bxxxxxxxx}
                         ,dt_150};

  // index begin
  wire [8:0] vec_305 [0:3-1];

  genvar i_307;
  generate
  for (i_307=0; i_307 < 3; i_307=i_307+1) begin : mk_array_305
    assign vec_305[(3-1)-i_307] = c$vecflat_298[i_307*9+:9];
  end
  endgenerate

  assign c$o_spiReadCtrl_case_alt_1 = vec_305[(64'sd1)];
  // index end

  assign c$vecflat_299 = {dt_144
                         ,{1'b0,8'bxxxxxxxx}
                         ,dt_150};

  // index begin
  wire [8:0] vec_306 [0:3-1];

  genvar i_308;
  generate
  for (i_308=0; i_308 < 3; i_308=i_308+1) begin : mk_array_306
    assign vec_306[(3-1)-i_308] = c$vecflat_299[i_308*9+:9];
  end
  endgenerate

  assign c$o_spiReadCtrl_case_alt_2 = vec_306[(64'sd0)];
  // index end

  assign c$vecflat_300 = {result_260[11:9]
                         ,{dt_146,dt_147}};

  // index begin
  wire [2:0] vec_307 [0:4-1];

  genvar i_309;
  generate
  for (i_309=0; i_309 < 4; i_309=i_309+1) begin : mk_array_307
    assign vec_307[(4-1)-i_309] = c$vecflat_300[i_309*3+:3];
  end
  endgenerate

  assign c$o_sensorOut_case_alt_1 = vec_307[(64'sd2)];
  // index end

  assign c$o_sensorOut_case_alt_2_selection_res = (bs_96[(64'sd2)]) == (1'b1);

  always @(*) begin
    if(c$o_sensorOut_case_alt_2_selection_res)
      c$o_sensorOut_case_alt_2 = c$o_sensorOut_case_alt_3;
    else
      c$o_sensorOut_case_alt_2 = c$o_sensorOut_case_alt_4;
  end

  assign bs_92 = {((result_267[(64'sd2)])),({((result_267[(64'sd3)])),({((result_267[(64'sd4)])),((result_267[(64'sd5)]))})})};

  assign c$vecflat_301 = {dt_142
                         ,{2'b00,16'bxxxxxxxxxxxxxxxx}
                         ,dt_148
                         ,dt_151};

  // index begin
  wire [17:0] vec_308 [0:4-1];

  genvar i_310;
  generate
  for (i_310=0; i_310 < 4; i_310=i_310+1) begin : mk_array_308
    assign vec_308[(4-1)-i_310] = c$vecflat_301[i_310*18+:18];
  end
  endgenerate

  assign c$o_output_case_alt_3 = vec_308[(64'sd1)];
  // index end

  assign c$vecflat_302 = {dt_142
                         ,{2'b00,16'bxxxxxxxxxxxxxxxx}
                         ,dt_148
                         ,dt_151};

  // index begin
  wire [17:0] vec_309 [0:4-1];

  genvar i_311;
  generate
  for (i_311=0; i_311 < 4; i_311=i_311+1) begin : mk_array_309
    assign vec_309[(4-1)-i_311] = c$vecflat_302[i_311*18+:18];
  end
  endgenerate

  assign c$o_output_case_alt_4 = vec_309[(64'sd0)];
  // index end

  assign bs_93 = {((result_267[(64'sd13)])),({((result_267[(64'sd14)])),((result_267[(64'sd15)]))})};

  assign bs_94 = {((result_267[(64'sd10)])),({((result_267[(64'sd11)])),((result_267[(64'sd12)]))})};

  assign bs_95 = {((result_267[(64'sd0)])),((result_267[(64'sd1)]))};

  assign bs_96 = {((result_267[(64'sd6)])),({((result_267[(64'sd7)])),({((result_267[(64'sd8)])),((result_267[(64'sd9)]))})})};

  assign c$vecflat_303 = {result_260[11:9]
                         ,{dt_146,dt_147}};

  // index begin
  wire [2:0] vec_310 [0:4-1];

  genvar i_312;
  generate
  for (i_312=0; i_312 < 4; i_312=i_312+1) begin : mk_array_310
    assign vec_310[(4-1)-i_312] = c$vecflat_303[i_312*3+:3];
  end
  endgenerate

  assign c$o_sensorOut_case_alt_3 = vec_310[(64'sd1)];
  // index end

  assign c$vecflat_304 = {result_260[11:9]
                         ,{dt_146,dt_147}};

  // index begin
  wire [2:0] vec_311 [0:4-1];

  genvar i_313;
  generate
  for (i_313=0; i_313 < 4; i_313=i_313+1) begin : mk_array_311
    assign vec_311[(4-1)-i_313] = c$vecflat_304[i_313*3+:3];
  end
  endgenerate

  assign c$o_sensorOut_case_alt_4 = vec_311[(64'sd0)];
  // index end

  // register begin
  reg [17:0] dt_142_reg = {2'b00,16'bxxxxxxxxxxxxxxxx};
  always @(posedge \$d(%,%) [1:1] or posedge \$d(%,%) [0:0]) begin : dt_142_register
    if (\$d(%,%) [0:0]) begin
      dt_142_reg <= {2'b00,16'bxxxxxxxxxxxxxxxx};
    end else begin
      dt_142_reg <= result_262;
    end
  end
  assign dt_142 = dt_142_reg;
  // register end

  // register begin
  reg [16:0] dt_143_reg = {1'b0,16'bxxxxxxxxxxxxxxxx};
  always @(posedge \$d(%,%) [1:1] or posedge \$d(%,%) [0:0]) begin : dt_143_register
    if (\$d(%,%) [0:0]) begin
      dt_143_reg <= {1'b0,16'bxxxxxxxxxxxxxxxx};
    end else begin
      dt_143_reg <= result_263;
    end
  end
  assign dt_143 = dt_143_reg;
  // register end

  // register begin
  reg [8:0] dt_144_reg = {1'b0,8'bxxxxxxxx};
  always @(posedge \$d(%,%) [1:1] or posedge \$d(%,%) [0:0]) begin : dt_144_register
    if (\$d(%,%) [0:0]) begin
      dt_144_reg <= {1'b0,8'bxxxxxxxx};
    end else begin
      dt_144_reg <= result_264;
    end
  end
  assign dt_144 = dt_144_reg;
  // register end

  assign dt_145 = c_lastCmd;

  // register begin
  reg [17:0] c_lastCmd_reg = {2'b00,16'bxxxxxxxxxxxxxxxx};
  always @(posedge \$d(%,%) [1:1] or posedge \$d(%,%) [0:0]) begin : c_lastCmd_register
    if (\$d(%,%) [0:0]) begin
      c_lastCmd_reg <= {2'b00,16'bxxxxxxxxxxxxxxxx};
    end else begin
      c_lastCmd_reg <= result_265;
    end
  end
  assign c_lastCmd = c_lastCmd_reg;
  // register end

  // register begin
  reg [2:0] dt_146_reg = {1'b0,1'b1,1'b1};
  always @(posedge \$d(%,%) [1:1] or posedge \$d(%,%) [0:0]) begin : dt_146_register
    if (\$d(%,%) [0:0]) begin
      dt_146_reg <= {1'b0,1'b1,1'b1};
    end else begin
      dt_146_reg <= result_266;
    end
  end
  assign dt_146 = dt_146_reg;
  // register end

  assign dt_147 = {result_228[3:1]
                  ,{1'b0,1'b1,1'b1}};

  assign result_267 = {(((~ w27_3) & c$cout_app_arg_61)),({(w27_3),({1'b0,({(w39_1),({(\c$_INTERNAL_.w37_0 ),({1'b0,({(((~ ((~ w39_1) & \c$_INTERNAL_.w6_2 )) & w34_1)),({(w38_0),({1'b0,({((~ w34_1)),({((~ (\c$_INTERNAL_.w5_app_arg  & (~ (w25_0 & \c$_INTERNAL_.w37_app_arg_0 ))))),({(((~ w22_1) & c$cout_app_arg_61)),({((w22_1 & c$w44_app_arg)),({1'b0,({((c$cout_app_arg_61 & \c$_INTERNAL_.w6_app_arg_1 )),(w14_3)})})})})})})})})})})})})})})};

  always @(*) begin
    case(\c$_INTERNAL_.ds2_app_arg [8:8])
      1'b0 : dt_148 = {2'b00,16'bxxxxxxxxxxxxxxxx};
      default : dt_148 = c$dt_case_alt_27;
    endcase
  end

  always @(*) begin
    case(c_lastCmd[17:16])
      2'b01 : dt_149 = {1'b1,ds1_2};
      default : dt_149 = {1'b0,16'bxxxxxxxxxxxxxxxx};
    endcase
  end

  always @(*) begin
    case(c_lastCmd[17:16])
      2'b10 : dt_150 = {1'b1,a_2};
      default : dt_150 = {1'b0,8'bxxxxxxxx};
    endcase
  end

  always @(*) begin
    case(c_lastCmd[17:16])
      2'b10 : c$dt_case_alt_27 = {2'b10,{a_2,x_6}};
      default : c$dt_case_alt_27 = {2'b00,16'bxxxxxxxxxxxxxxxx};
    endcase
  end

  always @(*) begin
    if(\c$_INTERNAL_.ds2_app_arg_0 )
      dt_151 = c$dt_case_alt_28;
    else
      dt_151 = {2'b00,16'bxxxxxxxxxxxxxxxx};
  end

  assign ds1_2 = c_lastCmd[15:0];

  assign a_2 = c_lastCmd[15:8];

  assign w27_3 = w20_3 & w11_9;

  assign c$cout_app_arg_61 = ~ w16_6;

  always @(*) begin
    case(c_lastCmd[17:16])
      2'b01 : c$dt_case_alt_28 = {2'b01,x_7,8'bxxxxxxxx};
      default : c$dt_case_alt_28 = {2'b00,16'bxxxxxxxxxxxxxxxx};
    endcase
  end

  assign w11_9 = c$w11_app_arg_7 & c$w11_app_arg_6;

  assign w20_3 = (~ (c$w20_app_arg_0 & c$w20_app_arg)) & (~ w15_4);

  assign w16_6 = w15_4 & \c$_INTERNAL_.w7_2 ;

  assign x_6 = \c$_INTERNAL_.ds2_app_arg [7:0];

  assign w15_4 = \c$_INTERNAL_.w6_2  & \c$_INTERNAL_.w5_5 ;

  // register begin
  reg  c$_INTERNAL_w7_2_reg = (1'b0);
  always @(posedge \$d(%,%) [1:1] or posedge \$d(%,%) [0:0]) begin : c$_INTERNAL_w7_2_register
    if (\$d(%,%) [0:0]) begin
      c$_INTERNAL_w7_2_reg <= (1'b0);
    end else begin
      c$_INTERNAL_w7_2_reg <= (~ ((~ (((~ w12_8) & \c$_INTERNAL_.w37_app_arg_0 ) & \c$_INTERNAL_.w7_app_arg_1 )) & (~ (((~ (w44_0 & \c$_INTERNAL_.w5_5 )) & \c$_INTERNAL_.w7_2 ) & (~ ((~ (\c$_INTERNAL_.w7_app_arg_2  & c$w20_app_arg)) & \c$_INTERNAL_.w6_2 ))))));
    end
  end
  assign \c$_INTERNAL_.w7_2  = c$_INTERNAL_w7_2_reg;
  // register end

  assign w39_1 = (~ \c$_INTERNAL_.w37_0 ) & c$cout_app_arg_61;

  assign c$w11_app_arg_6 = ~ w9_9;

  assign c$w11_app_arg_7 = ~ w10_9;

  assign x_7 = ds1_2[15:8];

  assign w10_9 = c$w10_app_arg_1 & c$w10_app_arg_0;

  assign w9_9 = c$w9_app_arg_8 & c$w9_app_arg_7;

  // register begin
  reg  c$_INTERNAL_w6_2_reg = (1'b0);
  always @(posedge \$d(%,%) [1:1] or posedge \$d(%,%) [0:0]) begin : c$_INTERNAL_w6_2_register
    if (\$d(%,%) [0:0]) begin
      c$_INTERNAL_w6_2_reg <= (1'b0);
    end else begin
      c$_INTERNAL_w6_2_reg <= (~ ((~ (w38_0 & c$w44_app_arg)) & \c$_INTERNAL_.w6_app_arg_1 ));
    end
  end
  assign \c$_INTERNAL_.w6_2  = c$_INTERNAL_w6_2_reg;
  // register end

  assign \c$_INTERNAL_.w37_0  = ((~ (\c$_INTERNAL_.w37_app_arg_0  & c$w20_app_arg)) & w11_9) & \c$_INTERNAL_.w37_app_arg ;

  // register begin
  reg  c$_INTERNAL_w5_5_reg = (1'b0);
  always @(posedge \$d(%,%) [1:1] or posedge \$d(%,%) [0:0]) begin : c$_INTERNAL_w5_5_register
    if (\$d(%,%) [0:0]) begin
      c$_INTERNAL_w5_5_reg <= (1'b0);
    end else begin
      c$_INTERNAL_w5_5_reg <= (~ ((c$w34_app_arg_0 & \c$_INTERNAL_.w5_app_arg ) & (~ ((~ (((~ ((c$w20_app_arg_0 & \c$_INTERNAL_.w5_app_arg_0 ) & c$w11_app_arg_7)) & (~ w31_0)) & \c$_INTERNAL_.w7_app_arg_1 )) & \c$_INTERNAL_.w37_app_arg_0 ))));
    end
  end
  assign \c$_INTERNAL_.w5_5  = c$_INTERNAL_w5_5_reg;
  // register end

  assign \c$_INTERNAL_.w37_app_arg  = ~ w21_2;

  assign c$w20_app_arg = ~ \c$_INTERNAL_.w5_5 ;

  assign c$w20_app_arg_0 = ~ \c$_INTERNAL_.w6_2 ;

  assign c$w9_app_arg_7 = cin_23[(64'sd0)];

  assign c$w9_app_arg_8 = cin_23[(64'sd1)];

  assign c$w10_app_arg_0 = cin_23[(64'sd2)];

  assign c$w10_app_arg_1 = cin_23[(64'sd3)];

  assign cin_23 = {c$cin_app_arg_19,({result_268,({result_270,result_269})})};

  assign w21_2 = (~ w20_3) & \c$_INTERNAL_.w7_2 ;

  assign w38_0 = \c$_INTERNAL_.w37_0  & \c$_INTERNAL_.w6_2 ;

  assign w34_1 = c$w34_app_arg_0 & (~ (w31_0 & \c$_INTERNAL_.w37_app_arg_0 ));

  assign \c$_INTERNAL_.w6_app_arg_1  = ~ w14_3;

  always @(*) begin
    if(\c$_INTERNAL_.ds2_app_arg_0 )
      c$cin_app_arg_19 = 1'b1;
    else
      c$cin_app_arg_19 = 1'b0;
  end

  assign w14_3 = ((~ ((~ c$w9_app_arg_8) & \c$_INTERNAL_.w5_app_arg_0 )) & \c$_INTERNAL_.w37_app_arg_0 ) & w12_8;

  assign c$w34_app_arg_0 = ~ w33_2;

  assign \c$_INTERNAL_.w7_app_arg_1  = ~ w48_0;

  assign \c$_INTERNAL_.w5_app_arg  = ~ w29_2;

  assign \c$_INTERNAL_.w37_app_arg_0  = ~ \c$_INTERNAL_.w7_2 ;

  always @(*) begin
    if(b_81)
      result_268 = 1'b1;
    else
      result_268 = 1'b0;
  end

  assign w12_8 = w11_9 & c$w20_app_arg_0;

  assign w29_2 = w28_0 & c$w10_app_arg_1;

  assign w48_0 = ((~ ((~ w44_0) & c$w20_app_arg)) & \c$_INTERNAL_.w6_2 ) & (~ (\c$_INTERNAL_.w7_app_arg_2  & \c$_INTERNAL_.w5_5 ));

  assign w33_2 = w28_0 & \c$_INTERNAL_.w5_5 ;

  always @(*) begin
    if(b_82)
      result_269 = 1'b1;
    else
      result_269 = 1'b0;
  end

  always @(*) begin
    if(b_83)
      result_270 = 1'b1;
    else
      result_270 = 1'b0;
  end

  always @(*) begin
    case(\c$_INTERNAL_.ds2_app_arg [8:8])
      1'b0 : b_81 = 1'b0;
      default : b_81 = 1'b1;
    endcase
  end

  assign w31_0 = w27_3 & \c$_INTERNAL_.w6_2 ;

  assign w28_0 = w27_3 & \c$_INTERNAL_.w7_2 ;

  always @(*) begin
    case(c$ds1_app_arg_0[17:16])
      2'b10 : b_82 = 1'b1;
      default : b_82 = 1'b0;
    endcase
  end

  always @(*) begin
    case(c$ds1_app_arg_0[17:16])
      2'b01 : b_83 = 1'b1;
      default : b_83 = 1'b0;
    endcase
  end

  assign w44_0 = (c$w44_app_arg & c$w10_app_arg_0) & c$w11_app_arg_6;

  assign \c$_INTERNAL_.w7_app_arg_2  = ~ w25_0;

  assign w25_0 = w18_5 & c$w10_app_arg_1;

  assign w22_1 = \c$_INTERNAL_.w37_app_arg  & w18_5;

  assign c$w44_app_arg = ~ c$w10_app_arg_1;

  assign w18_5 = c$w11_app_arg_6 & (~ c$w10_app_arg_0);

  assign \c$_INTERNAL_.w5_app_arg_0  = ~ c$w9_app_arg_7;

  // register begin
  reg [17:0] c$app_arg_10_reg = {2'b00,16'bxxxxxxxxxxxxxxxx};
  always @(posedge \$d(%,%) [1:1] or posedge \$d(%,%) [0:0]) begin : c$app_arg_10_register
    if (\$d(%,%) [0:0]) begin
      c$app_arg_10_reg <= {2'b00,16'bxxxxxxxxxxxxxxxx};
    end else begin
      c$app_arg_10_reg <= result_261[46:29];
    end
  end
  assign c$app_arg_10 = c$app_arg_10_reg;
  // register end

  assign result_271 = {result_261[28:26]
                      ,c$app_arg_10};

  assign startGyr = result_190[2:2];

  assign startMag = result_190[0:0];

  assign startAcc = result_190[3:3];

  assign startInit = result_190[1:1];

  assign result_272 = {result_273
                      ,result_274
                      ,result_275};

  assign result_273_selection_res = (bs_97[(64'sd0)]) == (1'b1);

  always @(*) begin
    if(result_273_selection_res)
      result_273 = c$o_command_case_alt;
    else
      result_273 = c$o_command_case_alt_0;
  end

  assign result_274_selection_res = (bs_98[(64'sd0)]) == (1'b1);

  always @(*) begin
    if(result_274_selection_res)
      result_274 = c$o_managerctrl_case_alt;
    else
      result_274 = c$o_managerctrl_case_alt_0;
  end

  assign result_275_selection_res = (bs_99[(64'sd0)]) == (1'b1);

  always @(*) begin
    if(result_275_selection_res)
      result_275 = c$o_sensorType_case_alt_9;
    else
      result_275 = c$o_sensorType_case_alt_10;
  end

  assign c$vecflat_305 = {dt_152
                         ,{result_162[18:1]
                          ,{result_183[18:1],{result_176[18:1],dt_154}}}};

  // index begin
  wire [17:0] vec_312 [0:5-1];

  genvar i_314;
  generate
  for (i_314=0; i_314 < 5; i_314=i_314+1) begin : mk_array_312
    assign vec_312[(5-1)-i_314] = c$vecflat_305[i_314*18+:18];
  end
  endgenerate

  assign c$o_command_case_alt = vec_312[(64'sd4)];
  // index end

  assign c$o_command_case_alt_0_selection_res = (bs_97[(64'sd1)]) == (1'b1);

  always @(*) begin
    if(c$o_command_case_alt_0_selection_res)
      c$o_command_case_alt_0 = c$o_command_case_alt_1;
    else
      c$o_command_case_alt_0 = c$o_command_case_alt_2;
  end

  assign c$vecflat_306 = {dt_153
                         ,{result_162[34:21]
                          ,{result_183[34:21]
                           ,{result_169[34:21],dt_155}}}};

  // index begin
  wire [13:0] vec_313 [0:5-1];

  genvar i_315;
  generate
  for (i_315=0; i_315 < 5; i_315=i_315+1) begin : mk_array_313
    assign vec_313[(5-1)-i_315] = c$vecflat_306[i_315*14+:14];
  end
  endgenerate

  assign c$o_managerctrl_case_alt = vec_313[(64'sd4)];
  // index end

  assign c$o_managerctrl_case_alt_0_selection_res = (bs_98[(64'sd1)]) == (1'b1);

  always @(*) begin
    if(c$o_managerctrl_case_alt_0_selection_res)
      c$o_managerctrl_case_alt_0 = c$o_managerctrl_case_alt_1;
    else
      c$o_managerctrl_case_alt_0 = c$o_managerctrl_case_alt_2;
  end

  assign c$vecflat_307 = {result_162[20:19]
                         ,result_183[20:19]
                         ,result_169[20:19]
                         ,result_176[20:19]
                         ,dt_156};

  // index begin
  wire [1:0] vec_314 [0:5-1];

  genvar i_316;
  generate
  for (i_316=0; i_316 < 5; i_316=i_316+1) begin : mk_array_314
    assign vec_314[(5-1)-i_316] = c$vecflat_307[i_316*2+:2];
  end
  endgenerate

  assign c$o_sensorType_case_alt_9 = vec_314[(64'sd4)];
  // index end

  assign c$o_sensorType_case_alt_10_selection_res = (bs_99[(64'sd1)]) == (1'b1);

  always @(*) begin
    if(c$o_sensorType_case_alt_10_selection_res)
      c$o_sensorType_case_alt_10 = c$o_sensorType_case_alt_11;
    else
      c$o_sensorType_case_alt_10 = c$o_sensorType_case_alt_12;
  end

  assign c$vecflat_308 = {dt_152
                         ,{result_162[18:1]
                          ,{result_183[18:1],{result_176[18:1],dt_154}}}};

  // index begin
  wire [17:0] vec_315 [0:5-1];

  genvar i_317;
  generate
  for (i_317=0; i_317 < 5; i_317=i_317+1) begin : mk_array_315
    assign vec_315[(5-1)-i_317] = c$vecflat_308[i_317*18+:18];
  end
  endgenerate

  assign c$o_command_case_alt_1 = vec_315[(64'sd3)];
  // index end

  assign c$o_command_case_alt_2_selection_res = (bs_97[(64'sd2)]) == (1'b1);

  always @(*) begin
    if(c$o_command_case_alt_2_selection_res)
      c$o_command_case_alt_2 = c$o_command_case_alt_3;
    else
      c$o_command_case_alt_2 = c$o_command_case_alt_4;
  end

  assign c$vecflat_309 = {dt_153
                         ,{result_162[34:21]
                          ,{result_183[34:21]
                           ,{result_169[34:21],dt_155}}}};

  // index begin
  wire [13:0] vec_316 [0:5-1];

  genvar i_318;
  generate
  for (i_318=0; i_318 < 5; i_318=i_318+1) begin : mk_array_316
    assign vec_316[(5-1)-i_318] = c$vecflat_309[i_318*14+:14];
  end
  endgenerate

  assign c$o_managerctrl_case_alt_1 = vec_316[(64'sd3)];
  // index end

  assign c$o_managerctrl_case_alt_2_selection_res = (bs_98[(64'sd2)]) == (1'b1);

  always @(*) begin
    if(c$o_managerctrl_case_alt_2_selection_res)
      c$o_managerctrl_case_alt_2 = c$o_managerctrl_case_alt_3;
    else
      c$o_managerctrl_case_alt_2 = c$o_managerctrl_case_alt_4;
  end

  assign c$vecflat_310 = {result_162[20:19]
                         ,result_183[20:19]
                         ,result_169[20:19]
                         ,result_176[20:19]
                         ,dt_156};

  // index begin
  wire [1:0] vec_317 [0:5-1];

  genvar i_319;
  generate
  for (i_319=0; i_319 < 5; i_319=i_319+1) begin : mk_array_317
    assign vec_317[(5-1)-i_319] = c$vecflat_310[i_319*2+:2];
  end
  endgenerate

  assign c$o_sensorType_case_alt_11 = vec_317[(64'sd3)];
  // index end

  assign c$o_sensorType_case_alt_12_selection_res = (bs_99[(64'sd2)]) == (1'b1);

  always @(*) begin
    if(c$o_sensorType_case_alt_12_selection_res)
      c$o_sensorType_case_alt_12 = c$o_sensorType_case_alt_13;
    else
      c$o_sensorType_case_alt_12 = c$o_sensorType_case_alt_14;
  end

  assign bs_97 = {((result_276[(64'sd0)])),({((result_276[(64'sd1)])),({((result_276[(64'sd2)])),({((result_276[(64'sd3)])),((result_276[(64'sd4)]))})})})};

  assign c$vecflat_311 = {dt_152
                         ,{result_162[18:1]
                          ,{result_183[18:1],{result_176[18:1],dt_154}}}};

  // index begin
  wire [17:0] vec_318 [0:5-1];

  genvar i_320;
  generate
  for (i_320=0; i_320 < 5; i_320=i_320+1) begin : mk_array_318
    assign vec_318[(5-1)-i_320] = c$vecflat_311[i_320*18+:18];
  end
  endgenerate

  assign c$o_command_case_alt_3 = vec_318[(64'sd2)];
  // index end

  assign c$o_command_case_alt_4_selection_res = (bs_97[(64'sd3)]) == (1'b1);

  always @(*) begin
    if(c$o_command_case_alt_4_selection_res)
      c$o_command_case_alt_4 = c$o_command_case_alt_5;
    else
      c$o_command_case_alt_4 = c$o_command_case_alt_6;
  end

  assign bs_98 = {((result_276[(64'sd5)])),({((result_276[(64'sd6)])),({((result_276[(64'sd7)])),({((result_276[(64'sd8)])),((result_276[(64'sd9)]))})})})};

  assign c$vecflat_312 = {dt_153
                         ,{result_162[34:21]
                          ,{result_183[34:21]
                           ,{result_169[34:21],dt_155}}}};

  // index begin
  wire [13:0] vec_319 [0:5-1];

  genvar i_321;
  generate
  for (i_321=0; i_321 < 5; i_321=i_321+1) begin : mk_array_319
    assign vec_319[(5-1)-i_321] = c$vecflat_312[i_321*14+:14];
  end
  endgenerate

  assign c$o_managerctrl_case_alt_3 = vec_319[(64'sd2)];
  // index end

  assign c$o_managerctrl_case_alt_4_selection_res = (bs_98[(64'sd3)]) == (1'b1);

  always @(*) begin
    if(c$o_managerctrl_case_alt_4_selection_res)
      c$o_managerctrl_case_alt_4 = c$o_managerctrl_case_alt_5;
    else
      c$o_managerctrl_case_alt_4 = c$o_managerctrl_case_alt_6;
  end

  assign bs_99 = {((result_276[(64'sd10)])),({((result_276[(64'sd11)])),({((result_276[(64'sd12)])),({((result_276[(64'sd13)])),((result_276[(64'sd14)]))})})})};

  assign c$vecflat_313 = {result_162[20:19]
                         ,result_183[20:19]
                         ,result_169[20:19]
                         ,result_176[20:19]
                         ,dt_156};

  // index begin
  wire [1:0] vec_320 [0:5-1];

  genvar i_322;
  generate
  for (i_322=0; i_322 < 5; i_322=i_322+1) begin : mk_array_320
    assign vec_320[(5-1)-i_322] = c$vecflat_313[i_322*2+:2];
  end
  endgenerate

  assign c$o_sensorType_case_alt_13 = vec_320[(64'sd2)];
  // index end

  assign c$o_sensorType_case_alt_14_selection_res = (bs_99[(64'sd3)]) == (1'b1);

  always @(*) begin
    if(c$o_sensorType_case_alt_14_selection_res)
      c$o_sensorType_case_alt_14 = c$o_sensorType_case_alt_15;
    else
      c$o_sensorType_case_alt_14 = c$o_sensorType_case_alt_16;
  end

  assign c$vecflat_314 = {dt_152
                         ,{result_162[18:1]
                          ,{result_183[18:1],{result_176[18:1],dt_154}}}};

  // index begin
  wire [17:0] vec_321 [0:5-1];

  genvar i_323;
  generate
  for (i_323=0; i_323 < 5; i_323=i_323+1) begin : mk_array_321
    assign vec_321[(5-1)-i_323] = c$vecflat_314[i_323*18+:18];
  end
  endgenerate

  assign c$o_command_case_alt_5 = vec_321[(64'sd1)];
  // index end

  assign c$vecflat_315 = {dt_152
                         ,{result_162[18:1]
                          ,{result_183[18:1],{result_176[18:1],dt_154}}}};

  // index begin
  wire [17:0] vec_322 [0:5-1];

  genvar i_324;
  generate
  for (i_324=0; i_324 < 5; i_324=i_324+1) begin : mk_array_322
    assign vec_322[(5-1)-i_324] = c$vecflat_315[i_324*18+:18];
  end
  endgenerate

  assign c$o_command_case_alt_6 = vec_322[(64'sd0)];
  // index end

  // register begin
  reg [17:0] dt_152_reg = {2'b00,16'bxxxxxxxxxxxxxxxx};
  always @(posedge \$d(%,%) [1:1] or posedge \$d(%,%) [0:0]) begin : dt_152_register
    if (\$d(%,%) [0:0]) begin
      dt_152_reg <= {2'b00,16'bxxxxxxxxxxxxxxxx};
    end else begin
      dt_152_reg <= result_273;
    end
  end
  assign dt_152 = dt_152_reg;
  // register end

  assign c$vecflat_316 = {dt_153
                         ,{result_162[34:21]
                          ,{result_183[34:21]
                           ,{result_169[34:21],dt_155}}}};

  // index begin
  wire [13:0] vec_323 [0:5-1];

  genvar i_325;
  generate
  for (i_325=0; i_325 < 5; i_325=i_325+1) begin : mk_array_323
    assign vec_323[(5-1)-i_325] = c$vecflat_316[i_325*14+:14];
  end
  endgenerate

  assign c$o_managerctrl_case_alt_5 = vec_323[(64'sd1)];
  // index end

  assign c$vecflat_317 = {dt_153
                         ,{result_162[34:21]
                          ,{result_183[34:21]
                           ,{result_169[34:21],dt_155}}}};

  // index begin
  wire [13:0] vec_324 [0:5-1];

  genvar i_326;
  generate
  for (i_326=0; i_326 < 5; i_326=i_326+1) begin : mk_array_324
    assign vec_324[(5-1)-i_326] = c$vecflat_317[i_326*14+:14];
  end
  endgenerate

  assign c$o_managerctrl_case_alt_6 = vec_324[(64'sd0)];
  // index end

  // register begin
  reg [13:0] dt_153_reg = {1'b0,13'bxxxxxxxxxxxxx};
  always @(posedge \$d(%,%) [1:1] or posedge \$d(%,%) [0:0]) begin : dt_153_register
    if (\$d(%,%) [0:0]) begin
      dt_153_reg <= {1'b0,13'bxxxxxxxxxxxxx};
    end else begin
      dt_153_reg <= result_274;
    end
  end
  assign dt_153 = dt_153_reg;
  // register end

  assign c$vecflat_318 = {result_162[20:19]
                         ,result_183[20:19]
                         ,result_169[20:19]
                         ,result_176[20:19]
                         ,dt_156};

  // index begin
  wire [1:0] vec_325 [0:5-1];

  genvar i_327;
  generate
  for (i_327=0; i_327 < 5; i_327=i_327+1) begin : mk_array_325
    assign vec_325[(5-1)-i_327] = c$vecflat_318[i_327*2+:2];
  end
  endgenerate

  assign c$o_sensorType_case_alt_15 = vec_325[(64'sd1)];
  // index end

  assign c$vecflat_319 = {result_162[20:19]
                         ,result_183[20:19]
                         ,result_169[20:19]
                         ,result_176[20:19]
                         ,dt_156};

  // index begin
  wire [1:0] vec_326 [0:5-1];

  genvar i_328;
  generate
  for (i_328=0; i_328 < 5; i_328=i_328+1) begin : mk_array_326
    assign vec_326[(5-1)-i_328] = c$vecflat_319[i_328*2+:2];
  end
  endgenerate

  assign c$o_sensorType_case_alt_16 = vec_326[(64'sd0)];
  // index end

  assign result_276 = {(w39_2),({c$cout_app_arg_62,({c$cout_app_arg_63,({c$cout_app_arg_64,({c$cout_app_arg_65,({(c$w41_app_arg),({c$cout_app_arg_63,({c$cout_app_arg_64,({c$cout_app_arg_65,({1'b0,({c$cout_app_arg_63,({c$cout_app_arg_62,({((~ (c$w41_app_arg_0 & c$w30_app_arg))),({c$cout_app_arg_65,1'b0})})})})})})})})})})})})})};

  assign w39_2 = result_277 & c$w39_app_arg;

  assign c$cout_app_arg_62 = w41;

  assign dt_154 = result_169[18:1];

  assign dt_155 = result_176[34:21];

  assign w41 = c$w41_app_arg_0 & c$w41_app_arg;

  assign c$cout_app_arg_63 = w42;

  assign c$w39_app_arg = ~ w30_2;

  assign w30_2 = (~ (c$w41_app_arg & (~ w23_2))) & c$w30_app_arg;

  assign w42 = w25_1 & c$w42_app_arg;

  assign c$cout_app_arg_64 = w17_6;

  assign c$w41_app_arg = ~ \c$_INTERNAL_.w28_0 ;

  assign c$w41_app_arg_0 = ~ w39_2;

  assign result_277 = (~ (\c$_INTERNAL_.w38_app_arg  & w15_5)) & (~ ((~ ((~ (((~ w9_10) & w5_0) & \c$_INTERNAL_.w38_app_arg )) & c$w42_app_arg)) & (~ \c$_INTERNAL_.w14_1 )));

  // register begin
  reg [1:0] dt_156_reg = 2'd3;
  always @(posedge \$d(%,%) [1:1] or posedge \$d(%,%) [0:0]) begin : dt_156_register
    if (\$d(%,%) [0:0]) begin
      dt_156_reg <= 2'd3;
    end else begin
      dt_156_reg <= result_275;
    end
  end
  assign dt_156 = dt_156_reg;
  // register end

  assign w25_1 = w16_7 & \c$_INTERNAL_.w7_3 ;

  assign w17_6 = w16_7 & \c$_INTERNAL_.w14_1 ;

  assign \c$_INTERNAL_.w28_0  = (~ (((~ w12_9) & c$w42_app_arg) & (~ w25_1))) & (~ ((~ w16_7) & \c$_INTERNAL_.w14_1 ));

  assign c$cout_app_arg_65 = w13_5;

  assign c$w42_app_arg = ~ \c$_INTERNAL_.w6_3 ;

  assign c$w30_app_arg = ~ w17_6;

  assign w16_7 = w15_5 & w9_10;

  // register begin
  reg  c$_INTERNAL_w6_3_reg = (1'b0);
  always @(posedge \$d(%,%) [1:1] or posedge \$d(%,%) [0:0]) begin : c$_INTERNAL_w6_3_register
    if (\$d(%,%) [0:0]) begin
      c$_INTERNAL_w6_3_reg <= (1'b0);
    end else begin
      c$_INTERNAL_w6_3_reg <= c$w39_app_arg;
    end
  end
  assign \c$_INTERNAL_.w6_3  = c$_INTERNAL_w6_3_reg;
  // register end

  assign \c$_INTERNAL_.w14_1  = \c$_INTERNAL_.w14_app_arg_1  & \c$_INTERNAL_.w6_3 ;

  // register begin
  reg  c$_INTERNAL_w7_3_reg = (1'b0);
  always @(posedge \$d(%,%) [1:1] or posedge \$d(%,%) [0:0]) begin : c$_INTERNAL_w7_3_register
    if (\$d(%,%) [0:0]) begin
      c$_INTERNAL_w7_3_reg <= (1'b0);
    end else begin
      c$_INTERNAL_w7_3_reg <= (((~ ((~ (c$w42_app_arg & \c$_INTERNAL_.w7_app_arg_5 )) & \c$_INTERNAL_.w7_3 )) & (~ ((\c$_INTERNAL_.w7_app_arg_4  & \c$_INTERNAL_.w7_app_arg_3 ) & \c$_INTERNAL_.w14_app_arg_1 ))) & w23_2);
    end
  end
  assign \c$_INTERNAL_.w7_3  = c$_INTERNAL_w7_3_reg;
  // register end

  assign w13_5 = w12_9 & c$w42_app_arg;

  assign w9_10 = \c$_INTERNAL_.w7_app_arg_3  & c$w22_app_arg;

  assign w15_5 = w8_7 & (~ w5_0);

  assign w12_9 = ((\c$_INTERNAL_.w14_app_arg_1  & w5_0) & w8_7) & w9_10;

  assign \c$_INTERNAL_.w38_app_arg  = ~ w32_3;

  assign \c$_INTERNAL_.w14_app_arg_1  = ~ \c$_INTERNAL_.w7_3 ;

  assign w8_7 = \c$_INTERNAL_.w7_app_arg_4  & \c$_INTERNAL_.w7_app_arg_5 ;

  assign w23_2 = w22_2 & (~ (\c$_INTERNAL_.w6_3  & w5_0));

  assign w32_3 = (~ (w8_7 & \c$_INTERNAL_.w7_app_arg_3 )) & (~ w22_2);

  assign w22_2 = ((~ (c$w8_app_arg_1 & c$w8_app_arg_0)) & c$w22_app_arg) & (~ ((~ w8_7) & c$w9_app_arg_9));

  // register begin
  reg  w5_0_reg = (1'b0);
  always @(posedge \$d(%,%) [1:1] or posedge \$d(%,%) [0:0]) begin : w5_0_register
    if (\$d(%,%) [0:0]) begin
      w5_0_reg <= (1'b0);
    end else begin
      w5_0_reg <= result_277;
    end
  end
  assign w5_0 = w5_0_reg;
  // register end

  assign c$w9_app_arg_9 = cin_24[(64'sd2)];

  assign cin_24 = {c$cin_app_arg_20,({c$cin_app_arg_21,({c$cin_app_arg_23,c$cin_app_arg_22})})};

  assign c$w8_app_arg_0 = cin_24[(64'sd0)];

  assign c$w8_app_arg_1 = cin_24[(64'sd3)];

  assign c$w22_app_arg = ~ (cin_24[(64'sd1)]);

  always @(*) begin
    if(startMag)
      c$cin_app_arg_20 = 1'b1;
    else
      c$cin_app_arg_20 = 1'b0;
  end

  assign \c$_INTERNAL_.w7_app_arg_3  = ~ c$w9_app_arg_9;

  assign \c$_INTERNAL_.w7_app_arg_4  = ~ c$w8_app_arg_1;

  always @(*) begin
    if(startInit)
      c$cin_app_arg_21 = 1'b1;
    else
      c$cin_app_arg_21 = 1'b0;
  end

  assign \c$_INTERNAL_.w7_app_arg_5  = ~ c$w8_app_arg_0;

  always @(*) begin
    if(startAcc)
      c$cin_app_arg_22 = 1'b1;
    else
      c$cin_app_arg_22 = 1'b0;
  end

  always @(*) begin
    if(startGyr)
      c$cin_app_arg_23 = 1'b1;
    else
      c$cin_app_arg_23 = 1'b0;
  end

  assign c$case_alt_10 = {a4_0,a5,a6,a7};

  assign a4_0 = ds_3[3:3];

  assign a5 = ds_3[2:2];

  assign a6 = ds_3[1:1];

  assign a7 = ds_3[0:0];

  assign ds_3 = {result_278[2:2]
                ,result_278[8:8]
                ,result_278[4:4]
                ,result_278[0:0]};

  assign result_278 = {result_280
                      ,result_279
                      ,result_282
                      ,result_281
                      ,result_284
                      ,result_283
                      ,result_286
                      ,result_285
                      ,result_288
                      ,result_287};

  assign result_279_selection_res = (bs_100[(64'sd0)]) == (1'b1);

  always @(*) begin
    if(result_279_selection_res)
      result_279 = c$o_csAGOut_case_alt;
    else
      result_279 = c$o_csAGOut_case_alt_0;
  end

  assign result_280_selection_res = (bs_101[(64'sd0)]) == (1'b1);

  always @(*) begin
    if(result_280_selection_res)
      result_280 = \c$_INTERNAL_.o_csAG_case_alt ;
    else
      result_280 = \c$_INTERNAL_.o_csAG_case_alt_0 ;
  end

  assign result_281_selection_res = (bs_102[(64'sd0)]) == (1'b1);

  always @(*) begin
    if(result_281_selection_res)
      result_281 = c$o_csAltOut_case_alt;
    else
      result_281 = c$o_csAltOut_case_alt_0;
  end

  assign result_282_selection_res = (bs_103[(64'sd0)]) == (1'b1);

  always @(*) begin
    if(result_282_selection_res)
      result_282 = \c$_INTERNAL_.o_csAlt_case_alt ;
    else
      result_282 = \c$_INTERNAL_.o_csAlt_case_alt_0 ;
  end

  assign result_283_selection_res = (bs_104[(64'sd0)]) == (1'b1);

  always @(*) begin
    if(result_283_selection_res)
      result_283 = c$o_csMagOut_case_alt;
    else
      result_283 = c$o_csMagOut_case_alt_0;
  end

  assign result_284_selection_res = (bs_105[(64'sd0)]) == (1'b1);

  always @(*) begin
    if(result_284_selection_res)
      result_284 = \c$_INTERNAL_.o_csMag_case_alt ;
    else
      result_284 = \c$_INTERNAL_.o_csMag_case_alt_0 ;
  end

  assign result_285_selection_res = (bs_106[(64'sd0)]) == (1'b1);

  always @(*) begin
    if(result_285_selection_res)
      result_285 = c$o_sdiOut_case_alt;
    else
      result_285 = c$o_sdiOut_case_alt_0;
  end

  assign result_286_selection_res = (bs_107[(64'sd0)]) == (1'b1);

  always @(*) begin
    if(result_286_selection_res)
      result_286 = \c$_INTERNAL_.o_sdi_case_alt ;
    else
      result_286 = \c$_INTERNAL_.o_sdi_case_alt_0 ;
  end

  assign result_287_selection_res = (bs_108[(64'sd0)]) == (1'b1);

  always @(*) begin
    if(result_287_selection_res)
      result_287 = c$o_spcOut_case_alt;
    else
      result_287 = c$o_spcOut_case_alt_0;
  end

  assign result_288_selection_res = (bs_109[(64'sd0)]) == (1'b1);

  always @(*) begin
    if(result_288_selection_res)
      result_288 = \c$_INTERNAL_.o_spc_case_alt ;
    else
      result_288 = \c$_INTERNAL_.o_spc_case_alt_0 ;
  end

  assign c$vecflat_320 = {c_csAG,dt_160};

  // index begin
  wire  vec_327 [0:2-1];

  genvar i_329;
  generate
  for (i_329=0; i_329 < 2; i_329=i_329+1) begin : mk_array_327
    assign vec_327[(2-1)-i_329] = c$vecflat_320[i_329*1+:1];
  end
  endgenerate

  assign c$o_csAGOut_case_alt = vec_327[(64'sd1)];
  // index end

  assign c$vecflat_321 = {c_csAG,dt_160};

  // index begin
  wire  vec_328 [0:2-1];

  genvar i_330;
  generate
  for (i_330=0; i_330 < 2; i_330=i_330+1) begin : mk_array_328
    assign vec_328[(2-1)-i_330] = c$vecflat_321[i_330*1+:1];
  end
  endgenerate

  assign c$o_csAGOut_case_alt_0 = vec_328[(64'sd0)];
  // index end

  assign c$vecflat_322 = {inPins[1:1],dt_157};

  // index begin
  wire  vec_329 [0:3-1];

  genvar i_331;
  generate
  for (i_331=0; i_331 < 3; i_331=i_331+1) begin : mk_array_329
    assign vec_329[(3-1)-i_331] = c$vecflat_322[i_331*1+:1];
  end
  endgenerate

  assign \c$_INTERNAL_.o_csAG_case_alt  = vec_329[(64'sd2)];
  // index end

  assign \c$_INTERNAL_.o_csAG_case_alt_0_selection_res  = (bs_101[(64'sd1)]) == (1'b1);

  always @(*) begin
    if(\c$_INTERNAL_.o_csAG_case_alt_0_selection_res )
      \c$_INTERNAL_.o_csAG_case_alt_0  = \c$_INTERNAL_.o_csAG_case_alt_1 ;
    else
      \c$_INTERNAL_.o_csAG_case_alt_0  = \c$_INTERNAL_.o_csAG_case_alt_2 ;
  end

  assign c$vecflat_323 = {c_csAlt,dt_161};

  // index begin
  wire  vec_330 [0:2-1];

  genvar i_332;
  generate
  for (i_332=0; i_332 < 2; i_332=i_332+1) begin : mk_array_330
    assign vec_330[(2-1)-i_332] = c$vecflat_323[i_332*1+:1];
  end
  endgenerate

  assign c$o_csAltOut_case_alt = vec_330[(64'sd1)];
  // index end

  assign c$vecflat_324 = {c_csAlt,dt_161};

  // index begin
  wire  vec_331 [0:2-1];

  genvar i_333;
  generate
  for (i_333=0; i_333 < 2; i_333=i_333+1) begin : mk_array_331
    assign vec_331[(2-1)-i_333] = c$vecflat_324[i_333*1+:1];
  end
  endgenerate

  assign c$o_csAltOut_case_alt_0 = vec_331[(64'sd0)];
  // index end

  assign c$vecflat_325 = {inPins[1:1],dt_158};

  // index begin
  wire  vec_332 [0:3-1];

  genvar i_334;
  generate
  for (i_334=0; i_334 < 3; i_334=i_334+1) begin : mk_array_332
    assign vec_332[(3-1)-i_334] = c$vecflat_325[i_334*1+:1];
  end
  endgenerate

  assign \c$_INTERNAL_.o_csAlt_case_alt  = vec_332[(64'sd2)];
  // index end

  assign \c$_INTERNAL_.o_csAlt_case_alt_0_selection_res  = (bs_103[(64'sd1)]) == (1'b1);

  always @(*) begin
    if(\c$_INTERNAL_.o_csAlt_case_alt_0_selection_res )
      \c$_INTERNAL_.o_csAlt_case_alt_0  = \c$_INTERNAL_.o_csAlt_case_alt_1 ;
    else
      \c$_INTERNAL_.o_csAlt_case_alt_0  = \c$_INTERNAL_.o_csAlt_case_alt_2 ;
  end

  assign c$vecflat_326 = {c_csMag,dt_162};

  // index begin
  wire  vec_333 [0:2-1];

  genvar i_335;
  generate
  for (i_335=0; i_335 < 2; i_335=i_335+1) begin : mk_array_333
    assign vec_333[(2-1)-i_335] = c$vecflat_326[i_335*1+:1];
  end
  endgenerate

  assign c$o_csMagOut_case_alt = vec_333[(64'sd1)];
  // index end

  assign c$vecflat_327 = {c_csMag,dt_162};

  // index begin
  wire  vec_334 [0:2-1];

  genvar i_336;
  generate
  for (i_336=0; i_336 < 2; i_336=i_336+1) begin : mk_array_334
    assign vec_334[(2-1)-i_336] = c$vecflat_327[i_336*1+:1];
  end
  endgenerate

  assign c$o_csMagOut_case_alt_0 = vec_334[(64'sd0)];
  // index end

  assign c$vecflat_328 = {inPins[1:1],dt_159};

  // index begin
  wire  vec_335 [0:3-1];

  genvar i_337;
  generate
  for (i_337=0; i_337 < 3; i_337=i_337+1) begin : mk_array_335
    assign vec_335[(3-1)-i_337] = c$vecflat_328[i_337*1+:1];
  end
  endgenerate

  assign \c$_INTERNAL_.o_csMag_case_alt  = vec_335[(64'sd2)];
  // index end

  assign \c$_INTERNAL_.o_csMag_case_alt_0_selection_res  = (bs_105[(64'sd1)]) == (1'b1);

  always @(*) begin
    if(\c$_INTERNAL_.o_csMag_case_alt_0_selection_res )
      \c$_INTERNAL_.o_csMag_case_alt_0  = \c$_INTERNAL_.o_csMag_case_alt_1 ;
    else
      \c$_INTERNAL_.o_csMag_case_alt_0  = \c$_INTERNAL_.o_csMag_case_alt_2 ;
  end

  assign c$vecflat_329 = {c_sdi,dt_163};

  // index begin
  wire  vec_336 [0:2-1];

  genvar i_338;
  generate
  for (i_338=0; i_338 < 2; i_338=i_338+1) begin : mk_array_336
    assign vec_336[(2-1)-i_338] = c$vecflat_329[i_338*1+:1];
  end
  endgenerate

  assign c$o_sdiOut_case_alt = vec_336[(64'sd1)];
  // index end

  assign c$vecflat_330 = {c_sdi,dt_163};

  // index begin
  wire  vec_337 [0:2-1];

  genvar i_339;
  generate
  for (i_339=0; i_339 < 2; i_339=i_339+1) begin : mk_array_337
    assign vec_337[(2-1)-i_339] = c$vecflat_330[i_339*1+:1];
  end
  endgenerate

  assign c$o_sdiOut_case_alt_0 = vec_337[(64'sd0)];
  // index end

  assign c$vecflat_331 = {1'b1,{c_sdi,dt_164}};

  // index begin
  wire  vec_338 [0:3-1];

  genvar i_340;
  generate
  for (i_340=0; i_340 < 3; i_340=i_340+1) begin : mk_array_338
    assign vec_338[(3-1)-i_340] = c$vecflat_331[i_340*1+:1];
  end
  endgenerate

  assign \c$_INTERNAL_.o_sdi_case_alt  = vec_338[(64'sd2)];
  // index end

  assign \c$_INTERNAL_.o_sdi_case_alt_0_selection_res  = (bs_107[(64'sd1)]) == (1'b1);

  always @(*) begin
    if(\c$_INTERNAL_.o_sdi_case_alt_0_selection_res )
      \c$_INTERNAL_.o_sdi_case_alt_0  = \c$_INTERNAL_.o_sdi_case_alt_1 ;
    else
      \c$_INTERNAL_.o_sdi_case_alt_0  = \c$_INTERNAL_.o_sdi_case_alt_2 ;
  end

  assign c$vecflat_332 = {c_spc,dt_165};

  // index begin
  wire  vec_339 [0:2-1];

  genvar i_341;
  generate
  for (i_341=0; i_341 < 2; i_341=i_341+1) begin : mk_array_339
    assign vec_339[(2-1)-i_341] = c$vecflat_332[i_341*1+:1];
  end
  endgenerate

  assign c$o_spcOut_case_alt = vec_339[(64'sd1)];
  // index end

  assign c$vecflat_333 = {c_spc,dt_165};

  // index begin
  wire  vec_340 [0:2-1];

  genvar i_342;
  generate
  for (i_342=0; i_342 < 2; i_342=i_342+1) begin : mk_array_340
    assign vec_340[(2-1)-i_342] = c$vecflat_333[i_342*1+:1];
  end
  endgenerate

  assign c$o_spcOut_case_alt_0 = vec_340[(64'sd0)];
  // index end

  assign c$vecflat_334 = {1'b1,{c_spc,dt_166}};

  // index begin
  wire  vec_341 [0:3-1];

  genvar i_343;
  generate
  for (i_343=0; i_343 < 3; i_343=i_343+1) begin : mk_array_341
    assign vec_341[(3-1)-i_343] = c$vecflat_334[i_343*1+:1];
  end
  endgenerate

  assign \c$_INTERNAL_.o_spc_case_alt  = vec_341[(64'sd2)];
  // index end

  assign \c$_INTERNAL_.o_spc_case_alt_0_selection_res  = (bs_109[(64'sd1)]) == (1'b1);

  always @(*) begin
    if(\c$_INTERNAL_.o_spc_case_alt_0_selection_res )
      \c$_INTERNAL_.o_spc_case_alt_0  = \c$_INTERNAL_.o_spc_case_alt_1 ;
    else
      \c$_INTERNAL_.o_spc_case_alt_0  = \c$_INTERNAL_.o_spc_case_alt_2 ;
  end

  assign c$vecflat_335 = {inPins[1:1],dt_157};

  // index begin
  wire  vec_342 [0:3-1];

  genvar i_344;
  generate
  for (i_344=0; i_344 < 3; i_344=i_344+1) begin : mk_array_342
    assign vec_342[(3-1)-i_344] = c$vecflat_335[i_344*1+:1];
  end
  endgenerate

  assign \c$_INTERNAL_.o_csAG_case_alt_1  = vec_342[(64'sd1)];
  // index end

  assign c$vecflat_336 = {inPins[1:1],dt_157};

  // index begin
  wire  vec_343 [0:3-1];

  genvar i_345;
  generate
  for (i_345=0; i_345 < 3; i_345=i_345+1) begin : mk_array_343
    assign vec_343[(3-1)-i_345] = c$vecflat_336[i_345*1+:1];
  end
  endgenerate

  assign \c$_INTERNAL_.o_csAG_case_alt_2  = vec_343[(64'sd0)];
  // index end

  assign c$vecflat_337 = {inPins[1:1],dt_158};

  // index begin
  wire  vec_344 [0:3-1];

  genvar i_346;
  generate
  for (i_346=0; i_346 < 3; i_346=i_346+1) begin : mk_array_344
    assign vec_344[(3-1)-i_346] = c$vecflat_337[i_346*1+:1];
  end
  endgenerate

  assign \c$_INTERNAL_.o_csAlt_case_alt_1  = vec_344[(64'sd1)];
  // index end

  assign c$vecflat_338 = {inPins[1:1],dt_158};

  // index begin
  wire  vec_345 [0:3-1];

  genvar i_347;
  generate
  for (i_347=0; i_347 < 3; i_347=i_347+1) begin : mk_array_345
    assign vec_345[(3-1)-i_347] = c$vecflat_338[i_347*1+:1];
  end
  endgenerate

  assign \c$_INTERNAL_.o_csAlt_case_alt_2  = vec_345[(64'sd0)];
  // index end

  assign c$vecflat_339 = {inPins[1:1],dt_159};

  // index begin
  wire  vec_346 [0:3-1];

  genvar i_348;
  generate
  for (i_348=0; i_348 < 3; i_348=i_348+1) begin : mk_array_346
    assign vec_346[(3-1)-i_348] = c$vecflat_339[i_348*1+:1];
  end
  endgenerate

  assign \c$_INTERNAL_.o_csMag_case_alt_1  = vec_346[(64'sd1)];
  // index end

  assign c$vecflat_340 = {inPins[1:1],dt_159};

  // index begin
  wire  vec_347 [0:3-1];

  genvar i_349;
  generate
  for (i_349=0; i_349 < 3; i_349=i_349+1) begin : mk_array_347
    assign vec_347[(3-1)-i_349] = c$vecflat_340[i_349*1+:1];
  end
  endgenerate

  assign \c$_INTERNAL_.o_csMag_case_alt_2  = vec_347[(64'sd0)];
  // index end

  assign c$vecflat_341 = {1'b1,{c_sdi,dt_164}};

  // index begin
  wire  vec_348 [0:3-1];

  genvar i_350;
  generate
  for (i_350=0; i_350 < 3; i_350=i_350+1) begin : mk_array_348
    assign vec_348[(3-1)-i_350] = c$vecflat_341[i_350*1+:1];
  end
  endgenerate

  assign \c$_INTERNAL_.o_sdi_case_alt_1  = vec_348[(64'sd1)];
  // index end

  assign c$vecflat_342 = {1'b1,{c_sdi,dt_164}};

  // index begin
  wire  vec_349 [0:3-1];

  genvar i_351;
  generate
  for (i_351=0; i_351 < 3; i_351=i_351+1) begin : mk_array_349
    assign vec_349[(3-1)-i_351] = c$vecflat_342[i_351*1+:1];
  end
  endgenerate

  assign \c$_INTERNAL_.o_sdi_case_alt_2  = vec_349[(64'sd0)];
  // index end

  assign c$vecflat_343 = {1'b1,{c_spc,dt_166}};

  // index begin
  wire  vec_350 [0:3-1];

  genvar i_352;
  generate
  for (i_352=0; i_352 < 3; i_352=i_352+1) begin : mk_array_350
    assign vec_350[(3-1)-i_352] = c$vecflat_343[i_352*1+:1];
  end
  endgenerate

  assign \c$_INTERNAL_.o_spc_case_alt_1  = vec_350[(64'sd1)];
  // index end

  assign c$vecflat_344 = {1'b1,{c_spc,dt_166}};

  // index begin
  wire  vec_351 [0:3-1];

  genvar i_353;
  generate
  for (i_353=0; i_353 < 3; i_353=i_353+1) begin : mk_array_351
    assign vec_351[(3-1)-i_353] = c$vecflat_344[i_353*1+:1];
  end
  endgenerate

  assign \c$_INTERNAL_.o_spc_case_alt_2  = vec_351[(64'sd0)];
  // index end

  assign bs_100 = {((cout_4[(64'sd3)])),((cout_4[(64'sd4)]))};

  assign bs_101 = {((cout_4[(64'sd0)])),({((cout_4[(64'sd1)])),((cout_4[(64'sd2)]))})};

  assign bs_102 = {((cout_4[(64'sd8)])),((cout_4[(64'sd9)]))};

  assign bs_103 = {((cout_4[(64'sd5)])),({((cout_4[(64'sd6)])),((cout_4[(64'sd7)]))})};

  assign bs_104 = {((cout_4[(64'sd13)])),((cout_4[(64'sd14)]))};

  assign bs_105 = {((cout_4[(64'sd10)])),({((cout_4[(64'sd11)])),((cout_4[(64'sd12)]))})};

  assign bs_106 = {((cout_4[(64'sd18)])),((cout_4[(64'sd19)]))};

  assign bs_107 = {((cout_4[(64'sd15)])),({((cout_4[(64'sd16)])),((cout_4[(64'sd17)]))})};

  assign bs_108 = {((cout_4[(64'sd23)])),((cout_4[(64'sd24)]))};

  assign bs_109 = {((cout_4[(64'sd20)])),({((cout_4[(64'sd21)])),((cout_4[(64'sd22)]))})};

  // register begin
  reg  c_spc_reg = (1'b1);
  always @(posedge \$d(%,%) [1:1] or posedge \$d(%,%) [0:0]) begin : c_spc_register
    if (\$d(%,%) [0:0]) begin
      c_spc_reg <= (1'b1);
    end else begin
      c_spc_reg <= result_288;
    end
  end
  assign c_spc = c_spc_reg;
  // register end

  // register begin
  reg  c_sdi_reg = (1'b0);
  always @(posedge \$d(%,%) [1:1] or posedge \$d(%,%) [0:0]) begin : c_sdi_register
    if (\$d(%,%) [0:0]) begin
      c_sdi_reg <= (1'b0);
    end else begin
      c_sdi_reg <= result_286;
    end
  end
  assign c_sdi = c_sdi_reg;
  // register end

  // register begin
  reg  c_csMag_reg = (1'b1);
  always @(posedge \$d(%,%) [1:1] or posedge \$d(%,%) [0:0]) begin : c_csMag_register
    if (\$d(%,%) [0:0]) begin
      c_csMag_reg <= (1'b1);
    end else begin
      c_csMag_reg <= result_284;
    end
  end
  assign c_csMag = c_csMag_reg;
  // register end

  // register begin
  reg  c_csAlt_reg = (1'b1);
  always @(posedge \$d(%,%) [1:1] or posedge \$d(%,%) [0:0]) begin : c_csAlt_register
    if (\$d(%,%) [0:0]) begin
      c_csAlt_reg <= (1'b1);
    end else begin
      c_csAlt_reg <= result_282;
    end
  end
  assign c_csAlt = c_csAlt_reg;
  // register end

  // register begin
  reg  c_csAG_reg = (1'b1);
  always @(posedge \$d(%,%) [1:1] or posedge \$d(%,%) [0:0]) begin : c_csAG_register
    if (\$d(%,%) [0:0]) begin
      c_csAG_reg <= (1'b1);
    end else begin
      c_csAG_reg <= result_280;
    end
  end
  assign c_csAG = c_csAG_reg;
  // register end

  assign dt_157 = {c_csAG,1'b1};

  assign dt_158 = {c_csAlt,1'b1};

  assign dt_159 = {c_csMag,1'b1};

  assign cout_4 = {1'b0,({1'b1,({c$cout_app_arg_67,({1'b0,({c$cout_app_arg_68,({1'b0,({1'b1,({c$cout_app_arg_67,({1'b0,({c$cout_app_arg_68,({1'b0,({1'b1,({((~ c$cout_app_arg_69)),({1'b0,({(c$cout_app_arg_69),({1'b0,({1'b1,({((~ c$cout_app_arg_70)),({1'b0,({(c$cout_app_arg_70),({1'b0,({1'b1,({((~ c$cout_app_arg_71)),({1'b0,(c$cout_app_arg_71)})})})})})})})})})})})})})})})})})})})})})})})};

  // register begin
  reg  dt_160_reg = (1'b1);
  always @(posedge \$d(%,%) [1:1] or posedge \$d(%,%) [0:0]) begin : dt_160_register
    if (\$d(%,%) [0:0]) begin
      dt_160_reg <= (1'b1);
    end else begin
      dt_160_reg <= result_279;
    end
  end
  assign dt_160 = dt_160_reg;
  // register end

  // register begin
  reg  dt_161_reg = (1'b1);
  always @(posedge \$d(%,%) [1:1] or posedge \$d(%,%) [0:0]) begin : dt_161_register
    if (\$d(%,%) [0:0]) begin
      dt_161_reg <= (1'b1);
    end else begin
      dt_161_reg <= result_281;
    end
  end
  assign dt_161 = dt_161_reg;
  // register end

  // register begin
  reg  dt_162_reg = (1'b1);
  always @(posedge \$d(%,%) [1:1] or posedge \$d(%,%) [0:0]) begin : dt_162_register
    if (\$d(%,%) [0:0]) begin
      dt_162_reg <= (1'b1);
    end else begin
      dt_162_reg <= result_283;
    end
  end
  assign dt_162 = dt_162_reg;
  // register end

  // register begin
  reg  dt_163_reg = (1'b0);
  always @(posedge \$d(%,%) [1:1] or posedge \$d(%,%) [0:0]) begin : dt_163_register
    if (\$d(%,%) [0:0]) begin
      dt_163_reg <= (1'b0);
    end else begin
      dt_163_reg <= result_285;
    end
  end
  assign dt_163 = dt_163_reg;
  // register end

  assign dt_164 = inPins[2:2];

  // register begin
  reg  dt_165_reg = (1'b1);
  always @(posedge \$d(%,%) [1:1] or posedge \$d(%,%) [0:0]) begin : dt_165_register
    if (\$d(%,%) [0:0]) begin
      dt_165_reg <= (1'b1);
    end else begin
      dt_165_reg <= result_287;
    end
  end
  assign dt_165 = dt_165_reg;
  // register end

  assign dt_166 = inPins[0:0];

  assign c$cout_app_arg_66 = cin_25[(64'sd3)];

  assign cin_25 = {result_289,({result_290,({result_292,result_291})})};

  always @(*) begin
    if(b_84)
      result_289 = 1'b1;
    else
      result_289 = 1'b0;
  end

  assign c$cout_app_arg_67 = (~ c$cout_app_arg_66);

  always @(*) begin
    if(b_85)
      result_290 = 1'b1;
    else
      result_290 = 1'b0;
  end

  always @(*) begin
    case(sensorType)
      2'b11 : b_84 = 1'b1;
      default : b_84 = 1'b0;
    endcase
  end

  always @(*) begin
    if(b_86)
      result_291 = 1'b1;
    else
      result_291 = 1'b0;
  end

  always @(*) begin
    if(b_87)
      result_292 = 1'b1;
    else
      result_292 = 1'b0;
  end

  always @(*) begin
    case(sensorType)
      2'b01 : b_85 = 1'b1;
      default : b_85 = 1'b0;
    endcase
  end

  assign c$cout_app_arg_68 = c$cout_app_arg_66;

  always @(*) begin
    case(sensorType)
      2'b00 : b_86 = 1'b1;
      default : b_86 = 1'b0;
    endcase
  end

  always @(*) begin
    case(sensorType)
      2'b10 : b_87 = 1'b1;
      default : b_87 = 1'b0;
    endcase
  end

  assign c$cout_app_arg_69 = cin_25[(64'sd2)];

  assign c$cout_app_arg_70 = cin_25[(64'sd1)];

  assign c$cout_app_arg_71 = cin_25[(64'sd0)];

  assign sensorType = result_272[1:0];

  assign inPins = result_271[20:18];

  always @(*) begin
    case(internRegister1)
      4'b1001 : b_88 = 1'b1;
      default : b_88 = 1'b0;
    endcase
  end

  always @(*) begin
    if(b_88)
      result_293 = 1'b1;
    else
      result_293 = 1'b0;
  end

  assign c$cout_app_arg_72 = result_293[(64'sd0)];

  assign result_294 = {((~ c$cout_app_arg_72)),(c$cout_app_arg_72)};

  // register begin
  reg signed [15:0] dt_167_reg = 16'sd0;
  always @(posedge \c$$d(%,%)1_0 [1:1] or posedge \c$$d(%,%)1_0 [0:0]) begin : dt_167_register
    if (\c$$d(%,%)1_0 [0:0]) begin
      dt_167_reg <= 16'sd0;
    end else begin
      dt_167_reg <= result_295;
    end
  end
  assign dt_167 = dt_167_reg;
  // register end

  assign c$vecflat_345 = {internRegister,dt_167};

  // index begin
  wire signed [15:0] vec_352 [0:2-1];

  genvar i_354;
  generate
  for (i_354=0; i_354 < 2; i_354=i_354+1) begin : mk_array_352
    assign vec_352[(2-1)-i_354] = c$vecflat_345[i_354*16+:16];
  end
  endgenerate

  assign c$o_regVal_case_alt = vec_352[(64'sd0)];
  // index end

  assign c$vecflat_346 = {internRegister,dt_167};

  // index begin
  wire signed [15:0] vec_353 [0:2-1];

  genvar i_355;
  generate
  for (i_355=0; i_355 < 2; i_355=i_355+1) begin : mk_array_353
    assign vec_353[(2-1)-i_355] = c$vecflat_346[i_355*16+:16];
  end
  endgenerate

  assign c$o_regVal_case_alt_0 = vec_353[(64'sd1)];
  // index end

  assign c$bv_34 = ({((result_294[(64'sd0)])),((result_294[(64'sd1)]))});

  assign result_295_selection_res = (c$bv_34[(64'sd0)]) == (1'b1);

  always @(*) begin
    if(result_295_selection_res)
      result_295 = c$o_regVal_case_alt_0;
    else
      result_295 = c$o_regVal_case_alt;
  end

  always @(*) begin
    case(internRegister1)
      4'b1000 : b_89 = 1'b1;
      default : b_89 = 1'b0;
    endcase
  end

  always @(*) begin
    if(b_89)
      result_296 = 1'b1;
    else
      result_296 = 1'b0;
  end

  assign c$cout_app_arg_73 = result_296[(64'sd0)];

  assign result_297 = {((~ c$cout_app_arg_73)),(c$cout_app_arg_73)};

  // register begin
  reg signed [15:0] dt_168_reg = 16'sd0;
  always @(posedge \c$$d(%,%)1_0 [1:1] or posedge \c$$d(%,%)1_0 [0:0]) begin : dt_168_register
    if (\c$$d(%,%)1_0 [0:0]) begin
      dt_168_reg <= 16'sd0;
    end else begin
      dt_168_reg <= result_298;
    end
  end
  assign dt_168 = dt_168_reg;
  // register end

  assign c$vecflat_347 = {internRegister,dt_168};

  // index begin
  wire signed [15:0] vec_354 [0:2-1];

  genvar i_356;
  generate
  for (i_356=0; i_356 < 2; i_356=i_356+1) begin : mk_array_354
    assign vec_354[(2-1)-i_356] = c$vecflat_347[i_356*16+:16];
  end
  endgenerate

  assign c$o_regVal_case_alt_1 = vec_354[(64'sd0)];
  // index end

  assign c$vecflat_348 = {internRegister,dt_168};

  // index begin
  wire signed [15:0] vec_355 [0:2-1];

  genvar i_357;
  generate
  for (i_357=0; i_357 < 2; i_357=i_357+1) begin : mk_array_355
    assign vec_355[(2-1)-i_357] = c$vecflat_348[i_357*16+:16];
  end
  endgenerate

  assign c$o_regVal_case_alt_2 = vec_355[(64'sd1)];
  // index end

  assign c$bv_35 = ({((result_297[(64'sd0)])),((result_297[(64'sd1)]))});

  assign result_298_selection_res = (c$bv_35[(64'sd0)]) == (1'b1);

  always @(*) begin
    if(result_298_selection_res)
      result_298 = c$o_regVal_case_alt_2;
    else
      result_298 = c$o_regVal_case_alt_1;
  end

  always @(*) begin
    case(internRegister1)
      4'b0111 : b_90 = 1'b1;
      default : b_90 = 1'b0;
    endcase
  end

  always @(*) begin
    if(b_90)
      result_299 = 1'b1;
    else
      result_299 = 1'b0;
  end

  assign c$cout_app_arg_74 = result_299[(64'sd0)];

  assign result_300 = {((~ c$cout_app_arg_74)),(c$cout_app_arg_74)};

  // register begin
  reg signed [15:0] dt_169_reg = 16'sd0;
  always @(posedge \c$$d(%,%)1_0 [1:1] or posedge \c$$d(%,%)1_0 [0:0]) begin : dt_169_register
    if (\c$$d(%,%)1_0 [0:0]) begin
      dt_169_reg <= 16'sd0;
    end else begin
      dt_169_reg <= result_301;
    end
  end
  assign dt_169 = dt_169_reg;
  // register end

  assign c$vecflat_349 = {internRegister,dt_169};

  // index begin
  wire signed [15:0] vec_356 [0:2-1];

  genvar i_358;
  generate
  for (i_358=0; i_358 < 2; i_358=i_358+1) begin : mk_array_356
    assign vec_356[(2-1)-i_358] = c$vecflat_349[i_358*16+:16];
  end
  endgenerate

  assign c$o_regVal_case_alt_3 = vec_356[(64'sd0)];
  // index end

  assign c$vecflat_350 = {internRegister,dt_169};

  // index begin
  wire signed [15:0] vec_357 [0:2-1];

  genvar i_359;
  generate
  for (i_359=0; i_359 < 2; i_359=i_359+1) begin : mk_array_357
    assign vec_357[(2-1)-i_359] = c$vecflat_350[i_359*16+:16];
  end
  endgenerate

  assign c$o_regVal_case_alt_4 = vec_357[(64'sd1)];
  // index end

  assign c$bv_36 = ({((result_300[(64'sd0)])),((result_300[(64'sd1)]))});

  assign result_301_selection_res = (c$bv_36[(64'sd0)]) == (1'b1);

  always @(*) begin
    if(result_301_selection_res)
      result_301 = c$o_regVal_case_alt_4;
    else
      result_301 = c$o_regVal_case_alt_3;
  end

  always @(*) begin
    case(internRegister1)
      4'b0110 : b_91 = 1'b1;
      default : b_91 = 1'b0;
    endcase
  end

  always @(*) begin
    if(b_91)
      result_302 = 1'b1;
    else
      result_302 = 1'b0;
  end

  assign c$cout_app_arg_75 = result_302[(64'sd0)];

  assign result_303 = {((~ c$cout_app_arg_75)),(c$cout_app_arg_75)};

  // register begin
  reg signed [15:0] dt_170_reg = 16'sd0;
  always @(posedge \c$$d(%,%)1_0 [1:1] or posedge \c$$d(%,%)1_0 [0:0]) begin : dt_170_register
    if (\c$$d(%,%)1_0 [0:0]) begin
      dt_170_reg <= 16'sd0;
    end else begin
      dt_170_reg <= result_304;
    end
  end
  assign dt_170 = dt_170_reg;
  // register end

  assign c$vecflat_351 = {internRegister,dt_170};

  // index begin
  wire signed [15:0] vec_358 [0:2-1];

  genvar i_360;
  generate
  for (i_360=0; i_360 < 2; i_360=i_360+1) begin : mk_array_358
    assign vec_358[(2-1)-i_360] = c$vecflat_351[i_360*16+:16];
  end
  endgenerate

  assign c$o_regVal_case_alt_5 = vec_358[(64'sd0)];
  // index end

  assign c$vecflat_352 = {internRegister,dt_170};

  // index begin
  wire signed [15:0] vec_359 [0:2-1];

  genvar i_361;
  generate
  for (i_361=0; i_361 < 2; i_361=i_361+1) begin : mk_array_359
    assign vec_359[(2-1)-i_361] = c$vecflat_352[i_361*16+:16];
  end
  endgenerate

  assign c$o_regVal_case_alt_6 = vec_359[(64'sd1)];
  // index end

  assign c$bv_37 = ({((result_303[(64'sd0)])),((result_303[(64'sd1)]))});

  assign result_304_selection_res = (c$bv_37[(64'sd0)]) == (1'b1);

  always @(*) begin
    if(result_304_selection_res)
      result_304 = c$o_regVal_case_alt_6;
    else
      result_304 = c$o_regVal_case_alt_5;
  end

  always @(*) begin
    case(internRegister1)
      4'b0101 : b_92 = 1'b1;
      default : b_92 = 1'b0;
    endcase
  end

  always @(*) begin
    if(b_92)
      result_305 = 1'b1;
    else
      result_305 = 1'b0;
  end

  assign c$cout_app_arg_76 = result_305[(64'sd0)];

  assign result_306 = {((~ c$cout_app_arg_76)),(c$cout_app_arg_76)};

  // register begin
  reg signed [15:0] dt_171_reg = 16'sd0;
  always @(posedge \c$$d(%,%)1_0 [1:1] or posedge \c$$d(%,%)1_0 [0:0]) begin : dt_171_register
    if (\c$$d(%,%)1_0 [0:0]) begin
      dt_171_reg <= 16'sd0;
    end else begin
      dt_171_reg <= result_307;
    end
  end
  assign dt_171 = dt_171_reg;
  // register end

  assign c$vecflat_353 = {internRegister,dt_171};

  // index begin
  wire signed [15:0] vec_360 [0:2-1];

  genvar i_362;
  generate
  for (i_362=0; i_362 < 2; i_362=i_362+1) begin : mk_array_360
    assign vec_360[(2-1)-i_362] = c$vecflat_353[i_362*16+:16];
  end
  endgenerate

  assign c$o_regVal_case_alt_7 = vec_360[(64'sd0)];
  // index end

  assign c$vecflat_354 = {internRegister,dt_171};

  // index begin
  wire signed [15:0] vec_361 [0:2-1];

  genvar i_363;
  generate
  for (i_363=0; i_363 < 2; i_363=i_363+1) begin : mk_array_361
    assign vec_361[(2-1)-i_363] = c$vecflat_354[i_363*16+:16];
  end
  endgenerate

  assign c$o_regVal_case_alt_8 = vec_361[(64'sd1)];
  // index end

  assign c$bv_38 = ({((result_306[(64'sd0)])),((result_306[(64'sd1)]))});

  assign result_307_selection_res = (c$bv_38[(64'sd0)]) == (1'b1);

  always @(*) begin
    if(result_307_selection_res)
      result_307 = c$o_regVal_case_alt_8;
    else
      result_307 = c$o_regVal_case_alt_7;
  end

  always @(*) begin
    case(internRegister1)
      4'b0100 : b_93 = 1'b1;
      default : b_93 = 1'b0;
    endcase
  end

  always @(*) begin
    if(b_93)
      result_308 = 1'b1;
    else
      result_308 = 1'b0;
  end

  assign c$cout_app_arg_77 = result_308[(64'sd0)];

  assign result_309 = {((~ c$cout_app_arg_77)),(c$cout_app_arg_77)};

  // register begin
  reg signed [15:0] dt_172_reg = 16'sd0;
  always @(posedge \c$$d(%,%)1_0 [1:1] or posedge \c$$d(%,%)1_0 [0:0]) begin : dt_172_register
    if (\c$$d(%,%)1_0 [0:0]) begin
      dt_172_reg <= 16'sd0;
    end else begin
      dt_172_reg <= result_310;
    end
  end
  assign dt_172 = dt_172_reg;
  // register end

  assign c$vecflat_355 = {internRegister,dt_172};

  // index begin
  wire signed [15:0] vec_362 [0:2-1];

  genvar i_364;
  generate
  for (i_364=0; i_364 < 2; i_364=i_364+1) begin : mk_array_362
    assign vec_362[(2-1)-i_364] = c$vecflat_355[i_364*16+:16];
  end
  endgenerate

  assign c$o_regVal_case_alt_9 = vec_362[(64'sd0)];
  // index end

  assign c$vecflat_356 = {internRegister,dt_172};

  // index begin
  wire signed [15:0] vec_363 [0:2-1];

  genvar i_365;
  generate
  for (i_365=0; i_365 < 2; i_365=i_365+1) begin : mk_array_363
    assign vec_363[(2-1)-i_365] = c$vecflat_356[i_365*16+:16];
  end
  endgenerate

  assign c$o_regVal_case_alt_10 = vec_363[(64'sd1)];
  // index end

  assign c$bv_39 = ({((result_309[(64'sd0)])),((result_309[(64'sd1)]))});

  assign result_310_selection_res = (c$bv_39[(64'sd0)]) == (1'b1);

  always @(*) begin
    if(result_310_selection_res)
      result_310 = c$o_regVal_case_alt_10;
    else
      result_310 = c$o_regVal_case_alt_9;
  end

  always @(*) begin
    case(internRegister1)
      4'b0011 : b_94 = 1'b1;
      default : b_94 = 1'b0;
    endcase
  end

  always @(*) begin
    if(b_94)
      result_311 = 1'b1;
    else
      result_311 = 1'b0;
  end

  assign c$cout_app_arg_78 = result_311[(64'sd0)];

  assign result_312 = {((~ c$cout_app_arg_78)),(c$cout_app_arg_78)};

  // register begin
  reg signed [15:0] dt_173_reg = 16'sd0;
  always @(posedge \c$$d(%,%)1_0 [1:1] or posedge \c$$d(%,%)1_0 [0:0]) begin : dt_173_register
    if (\c$$d(%,%)1_0 [0:0]) begin
      dt_173_reg <= 16'sd0;
    end else begin
      dt_173_reg <= result_313;
    end
  end
  assign dt_173 = dt_173_reg;
  // register end

  assign c$vecflat_357 = {internRegister,dt_173};

  // index begin
  wire signed [15:0] vec_364 [0:2-1];

  genvar i_366;
  generate
  for (i_366=0; i_366 < 2; i_366=i_366+1) begin : mk_array_364
    assign vec_364[(2-1)-i_366] = c$vecflat_357[i_366*16+:16];
  end
  endgenerate

  assign c$o_regVal_case_alt_11 = vec_364[(64'sd0)];
  // index end

  assign c$vecflat_358 = {internRegister,dt_173};

  // index begin
  wire signed [15:0] vec_365 [0:2-1];

  genvar i_367;
  generate
  for (i_367=0; i_367 < 2; i_367=i_367+1) begin : mk_array_365
    assign vec_365[(2-1)-i_367] = c$vecflat_358[i_367*16+:16];
  end
  endgenerate

  assign c$o_regVal_case_alt_12 = vec_365[(64'sd1)];
  // index end

  assign c$bv_40 = ({((result_312[(64'sd0)])),((result_312[(64'sd1)]))});

  assign result_313_selection_res = (c$bv_40[(64'sd0)]) == (1'b1);

  always @(*) begin
    if(result_313_selection_res)
      result_313 = c$o_regVal_case_alt_12;
    else
      result_313 = c$o_regVal_case_alt_11;
  end

  assign result_314 = {result_316
                      ,result_315
                      ,result_317};

  assign result_315_selection_res = (bs_110[(64'sd0)]) == (1'b1);

  always @(*) begin
    if(result_315_selection_res)
      result_315 = c$o_fullreg_case_alt;
    else
      result_315 = c$o_fullreg_case_alt_0;
  end

  assign result_316_selection_res = (bs_111[(64'sd0)]) == (1'b1);

  always @(*) begin
    if(result_316_selection_res)
      result_316 = \c$_INTERNAL_.o_buffer_case_alt ;
    else
      result_316 = \c$_INTERNAL_.o_buffer_case_alt_0 ;
  end

  assign result_317_selection_res = (bs_112[(64'sd0)]) == (1'b1);

  always @(*) begin
    if(result_317_selection_res)
      result_317 = c$o_regname_case_alt;
    else
      result_317 = c$o_regname_case_alt_0;
  end

  assign c$vecflat_359 = {dt_174,16'sd0,dt_177};

  // index begin
  wire signed [15:0] vec_366 [0:3-1];

  genvar i_368;
  generate
  for (i_368=0; i_368 < 3; i_368=i_368+1) begin : mk_array_366
    assign vec_366[(3-1)-i_368] = c$vecflat_359[i_368*16+:16];
  end
  endgenerate

  assign c$o_fullreg_case_alt = vec_366[(64'sd2)];
  // index end

  assign c$o_fullreg_case_alt_0_selection_res = (bs_110[(64'sd1)]) == (1'b1);

  always @(*) begin
    if(c$o_fullreg_case_alt_0_selection_res)
      c$o_fullreg_case_alt_0 = c$o_fullreg_case_alt_1;
    else
      c$o_fullreg_case_alt_0 = c$o_fullreg_case_alt_2;
  end

  assign c$vecflat_360 = {c_buffer,dt_175};

  // index begin
  wire [7:0] vec_367 [0:2-1];

  genvar i_369;
  generate
  for (i_369=0; i_369 < 2; i_369=i_369+1) begin : mk_array_367
    assign vec_367[(2-1)-i_369] = c$vecflat_360[i_369*8+:8];
  end
  endgenerate

  assign \c$_INTERNAL_.o_buffer_case_alt  = vec_367[(64'sd1)];
  // index end

  assign c$vecflat_361 = {c_buffer,dt_175};

  // index begin
  wire [7:0] vec_368 [0:2-1];

  genvar i_370;
  generate
  for (i_370=0; i_370 < 2; i_370=i_370+1) begin : mk_array_368
    assign vec_368[(2-1)-i_370] = c$vecflat_361[i_370*8+:8];
  end
  endgenerate

  assign \c$_INTERNAL_.o_buffer_case_alt_0  = vec_368[(64'sd0)];
  // index end

  assign c$vecflat_362 = {dt_176,4'd0,dt_178};

  // index begin
  wire [3:0] vec_369 [0:3-1];

  genvar i_371;
  generate
  for (i_371=0; i_371 < 3; i_371=i_371+1) begin : mk_array_369
    assign vec_369[(3-1)-i_371] = c$vecflat_362[i_371*4+:4];
  end
  endgenerate

  assign c$o_regname_case_alt = vec_369[(64'sd2)];
  // index end

  assign c$o_regname_case_alt_0_selection_res = (bs_112[(64'sd1)]) == (1'b1);

  always @(*) begin
    if(c$o_regname_case_alt_0_selection_res)
      c$o_regname_case_alt_0 = c$o_regname_case_alt_1;
    else
      c$o_regname_case_alt_0 = c$o_regname_case_alt_2;
  end

  assign c$vecflat_363 = {dt_174,16'sd0,dt_177};

  // index begin
  wire signed [15:0] vec_370 [0:3-1];

  genvar i_372;
  generate
  for (i_372=0; i_372 < 3; i_372=i_372+1) begin : mk_array_370
    assign vec_370[(3-1)-i_372] = c$vecflat_363[i_372*16+:16];
  end
  endgenerate

  assign c$o_fullreg_case_alt_1 = vec_370[(64'sd1)];
  // index end

  assign c$vecflat_364 = {dt_174,16'sd0,dt_177};

  // index begin
  wire signed [15:0] vec_371 [0:3-1];

  genvar i_373;
  generate
  for (i_373=0; i_373 < 3; i_373=i_373+1) begin : mk_array_371
    assign vec_371[(3-1)-i_373] = c$vecflat_364[i_373*16+:16];
  end
  endgenerate

  assign c$o_fullreg_case_alt_2 = vec_371[(64'sd0)];
  // index end

  assign c$vecflat_365 = {dt_176,4'd0,dt_178};

  // index begin
  wire [3:0] vec_372 [0:3-1];

  genvar i_374;
  generate
  for (i_374=0; i_374 < 3; i_374=i_374+1) begin : mk_array_372
    assign vec_372[(3-1)-i_374] = c$vecflat_365[i_374*4+:4];
  end
  endgenerate

  assign c$o_regname_case_alt_1 = vec_372[(64'sd1)];
  // index end

  assign c$vecflat_366 = {dt_176,4'd0,dt_178};

  // index begin
  wire [3:0] vec_373 [0:3-1];

  genvar i_375;
  generate
  for (i_375=0; i_375 < 3; i_375=i_375+1) begin : mk_array_373
    assign vec_373[(3-1)-i_375] = c$vecflat_366[i_375*4+:4];
  end
  endgenerate

  assign c$o_regname_case_alt_2 = vec_373[(64'sd0)];
  // index end

  assign bs_110 = {((result_318[(64'sd2)])),({((result_318[(64'sd3)])),((result_318[(64'sd4)]))})};

  assign bs_111 = {((result_318[(64'sd0)])),((result_318[(64'sd1)]))};

  assign bs_112 = {((result_318[(64'sd5)])),({((result_318[(64'sd6)])),((result_318[(64'sd7)]))})};

  // register begin
  reg [7:0] c_buffer_reg = 8'b00000000;
  always @(posedge \c$$d(%,%)1_0 [1:1] or posedge \c$$d(%,%)1_0 [0:0]) begin : c_buffer_register
    if (\c$$d(%,%)1_0 [0:0]) begin
      c_buffer_reg <= 8'b00000000;
    end else begin
      c_buffer_reg <= result_316;
    end
  end
  assign c_buffer = c_buffer_reg;
  // register end

  // register begin
  reg signed [15:0] dt_174_reg = 16'sd0;
  always @(posedge \c$$d(%,%)1_0 [1:1] or posedge \c$$d(%,%)1_0 [0:0]) begin : dt_174_register
    if (\c$$d(%,%)1_0 [0:0]) begin
      dt_174_reg <= 16'sd0;
    end else begin
      dt_174_reg <= result_315;
    end
  end
  assign dt_174 = dt_174_reg;
  // register end

  assign dt_175 = w6_4;

  // register begin
  reg [3:0] dt_176_reg = 4'd0;
  always @(posedge \c$$d(%,%)1_0 [1:1] or posedge \c$$d(%,%)1_0 [0:0]) begin : dt_176_register
    if (\c$$d(%,%)1_0 [0:0]) begin
      dt_176_reg <= 4'd0;
    end else begin
      dt_176_reg <= result_317;
    end
  end
  assign dt_176 = dt_176_reg;
  // register end

  assign w6_4_selection = result_272[15:2];

  always @(*) begin
    case(w6_4_selection[13:13])
      1'b0 : w6_4 = 8'b00000000;
      default : w6_4 = ds1_3[7:0];
    endcase
  end

  assign ds1_3 = result_272[14:2];

  assign result_318 = {c$cout_app_arg_80,({c$cout_app_arg_81,({1'b0,({c$cout_app_arg_80,({c$cout_app_arg_81,({1'b0,({(c$cout_app_arg_82),((~ c$cout_app_arg_82))})})})})})})};

  assign dt_177 = $signed(((({8'b00000000,w6_4}) << (64'sd8)) | ({8'b00000000,c_buffer})));

  assign dt_178_selection = result_272[15:2];

  always @(*) begin
    case(dt_178_selection[13:13])
      1'b0 : dt_178 = 4'd0;
      default : dt_178 = ds1_3[12:9];
    endcase
  end

  assign c$cout_app_arg_79 = cin_26[(64'sd1)];

  assign cin_26 = {result_320,result_319};

  assign c$cout_app_arg_80 = c$cout_app_arg_79;

  always @(*) begin
    if(b_95)
      result_319 = 1'b1;
    else
      result_319 = 1'b0;
  end

  always @(*) begin
    if(b_96)
      result_320 = 1'b1;
    else
      result_320 = 1'b0;
  end

  assign c$cout_app_arg_81 = (~ c$cout_app_arg_79);

  assign b_95_selection = result_272[15:2];

  always @(*) begin
    case(b_95_selection[13:13])
      1'b0 : b_95 = 1'b0;
      default : b_95 = ds3_1 == 1'd0;
    endcase
  end

  assign b_96_selection = result_272[15:2];

  always @(*) begin
    case(b_96_selection[13:13])
      1'b0 : b_96 = 1'b0;
      default : b_96 = ds3_1 == 1'd1;
    endcase
  end

  assign ds3_1 = ds1_3[8:8];

  assign c$cout_app_arg_82 = cin_26[(64'sd0)];

  always @(*) begin
    case(internRegister1)
      4'b0010 : b_97 = 1'b1;
      default : b_97 = 1'b0;
    endcase
  end

  always @(*) begin
    if(b_97)
      result_321 = 1'b1;
    else
      result_321 = 1'b0;
  end

  assign c$cout_app_arg_83 = result_321[(64'sd0)];

  assign result_322 = {((~ c$cout_app_arg_83)),(c$cout_app_arg_83)};

  // register begin
  reg signed [15:0] dt_179_reg = 16'sd0;
  always @(posedge \c$$d(%,%)1_0 [1:1] or posedge \c$$d(%,%)1_0 [0:0]) begin : dt_179_register
    if (\c$$d(%,%)1_0 [0:0]) begin
      dt_179_reg <= 16'sd0;
    end else begin
      dt_179_reg <= result_323;
    end
  end
  assign dt_179 = dt_179_reg;
  // register end

  assign c$vecflat_367 = {internRegister,dt_179};

  // index begin
  wire signed [15:0] vec_374 [0:2-1];

  genvar i_376;
  generate
  for (i_376=0; i_376 < 2; i_376=i_376+1) begin : mk_array_374
    assign vec_374[(2-1)-i_376] = c$vecflat_367[i_376*16+:16];
  end
  endgenerate

  assign c$o_regVal_case_alt_13 = vec_374[(64'sd0)];
  // index end

  assign c$vecflat_368 = {internRegister,dt_179};

  // index begin
  wire signed [15:0] vec_375 [0:2-1];

  genvar i_377;
  generate
  for (i_377=0; i_377 < 2; i_377=i_377+1) begin : mk_array_375
    assign vec_375[(2-1)-i_377] = c$vecflat_368[i_377*16+:16];
  end
  endgenerate

  assign c$o_regVal_case_alt_14 = vec_375[(64'sd1)];
  // index end

  assign c$bv_41 = ({((result_322[(64'sd0)])),((result_322[(64'sd1)]))});

  assign result_323_selection_res = (c$bv_41[(64'sd0)]) == (1'b1);

  always @(*) begin
    if(result_323_selection_res)
      result_323 = c$o_regVal_case_alt_14;
    else
      result_323 = c$o_regVal_case_alt_13;
  end

  assign internRegister1 = result_314[3:0];

  assign internRegister = result_314[19:4];

  assign \c$$d(%,%)1_0  = {\$d(%,%) [1:1]
                          ,\$d(%,%) [0:0]};

  always @(*) begin
    case(internRegister1)
      4'b0001 : b_98 = 1'b1;
      default : b_98 = 1'b0;
    endcase
  end

  always @(*) begin
    if(b_98)
      result_324 = 1'b1;
    else
      result_324 = 1'b0;
  end

  assign c$cout_app_arg_84 = result_324[(64'sd0)];

  assign result_325 = {((~ c$cout_app_arg_84)),(c$cout_app_arg_84)};

  // register begin
  reg signed [15:0] dt_180_reg = 16'sd0;
  always @(posedge \c$$d(%,%)1_0 [1:1] or posedge \c$$d(%,%)1_0 [0:0]) begin : dt_180_register
    if (\c$$d(%,%)1_0 [0:0]) begin
      dt_180_reg <= 16'sd0;
    end else begin
      dt_180_reg <= result_326;
    end
  end
  assign dt_180 = dt_180_reg;
  // register end

  assign c$vecflat_369 = {internRegister,dt_180};

  // index begin
  wire signed [15:0] vec_376 [0:2-1];

  genvar i_378;
  generate
  for (i_378=0; i_378 < 2; i_378=i_378+1) begin : mk_array_376
    assign vec_376[(2-1)-i_378] = c$vecflat_369[i_378*16+:16];
  end
  endgenerate

  assign c$o_regVal_case_alt_15 = vec_376[(64'sd0)];
  // index end

  assign c$vecflat_370 = {internRegister,dt_180};

  // index begin
  wire signed [15:0] vec_377 [0:2-1];

  genvar i_379;
  generate
  for (i_379=0; i_379 < 2; i_379=i_379+1) begin : mk_array_377
    assign vec_377[(2-1)-i_379] = c$vecflat_370[i_379*16+:16];
  end
  endgenerate

  assign c$o_regVal_case_alt_16 = vec_377[(64'sd1)];
  // index end

  assign c$bv_42 = ({((result_325[(64'sd0)])),((result_325[(64'sd1)]))});

  assign result_326_selection_res = (c$bv_42[(64'sd0)]) == (1'b1);

  always @(*) begin
    if(result_326_selection_res)
      result_326 = c$o_regVal_case_alt_16;
    else
      result_326 = c$o_regVal_case_alt_15;
  end

  assign result_327 = {result_326
                      ,result_323
                      ,result_313
                      ,result_310
                      ,result_307
                      ,result_304
                      ,result_301
                      ,result_298
                      ,result_295};

  assign result_328 = {c$case_alt_10,result_327};

  // register begin
  reg signed [15:0] c$ds1_app_arg_1_reg = 16'sd0;
  always @(posedge \$d(%,%) [1:1] or posedge \$d(%,%) [0:0]) begin : c$ds1_app_arg_1_register
    if (\$d(%,%) [0:0]) begin
      c$ds1_app_arg_1_reg <= 16'sd0;
    end else begin
      c$ds1_app_arg_1_reg <= (scrut1_2[112-1 -: 16]);
    end
  end
  assign c$ds1_app_arg_1 = c$ds1_app_arg_1_reg;
  // register end

  assign gyroz = scrut4[64-1 -: 16];

  assign gyrox = scrut2_2[96-1 -: 16];

  assign gyroy = scrut3_1[80-1 -: 16];

  assign scrut4 = scrut3_1[64-1 : 0];

  assign scrut3_1 = scrut2_2[80-1 : 0];

  assign scrut2_2 = scrut1_2[96-1 : 0];

  assign scrut1_2 = scrut_1[112-1 : 0];

  assign scrut_1 = ds1_4[128-1 : 0];

  assign ds1_4 = result_328[143:0];

  // register begin
  reg  result_329_reg = (1'b0);
  always @(posedge \$d(%,%) [1:1] or posedge \$d(%,%) [0:0]) begin : result_329_register
    if (\$d(%,%) [0:0]) begin
      result_329_reg <= (1'b0);
    end else begin
      result_329_reg <= c$resetPin_case_alt;
    end
  end
  assign result_329 = result_329_reg;
  // register end

  always @(*) begin
    if(h)
      c$resetPin_case_alt = 1'b0;
    else
      c$resetPin_case_alt = c$resetPin_case_alt_0;
  end

  assign h = ds_4[1:1];

  always @(*) begin
    case(i)
      1'd0 : c$resetPin_case_alt_0 = 1'b0;
      default : c$resetPin_case_alt_0 = 1'b1;
    endcase
  end

  assign ds_4 = {result_330,c$ds_app_arg_0};

  assign i = ds_4[0:0];

  // register begin
  reg [0:0] c$ds_app_arg_0_reg = 1'd0;
  always @(posedge \$d(%,%) [1:1] or posedge \$d(%,%) [0:0]) begin : c$ds_app_arg_0_register
    if (\$d(%,%) [0:0]) begin
      c$ds_app_arg_0_reg <= 1'd0;
    end else begin
      c$ds_app_arg_0_reg <= 1'd1;
    end
  end
  assign c$ds_app_arg_0 = c$ds_app_arg_0_reg;
  // register end

  // blockRam begin
  reg  result_330_RAM [0:1-1];

  reg [0:0] ram_init;
  integer i_380;
  initial begin
    ram_init = 1'b0;
    for (i_380=0; i_380 < 1; i_380 = i_380 + 1) begin
      result_330_RAM[1-1-i_380] = ram_init[i_380*1+:1];
    end
  end

  always @(posedge \$d(%,%) [1:1]) begin : result_330_blockRam
    if (c$ds_app_arg_1) begin
      result_330_RAM[(wild_6)] <= tup_0[0:0];
    end
    result_330 <= result_330_RAM[(64'sd0)];
  end
  // blockRam end

  always @(*) begin
    case(wrM_0[65:65])
      1'b0 : c$ds_app_arg_1 = 1'b0;
      default : c$ds_app_arg_1 = 1'b1;
    endcase
  end

  assign wrM_0_selection_res = c$resetPin_case_alt == (1'b1);

  always @(*) begin
    if(wrM_0_selection_res)
      wrM_0 = {1'b1,{64'sd0,1'b1}};
    else
      wrM_0 = {1'b0,65'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx};
  end

  always @(*) begin
    case(wrM_0[65:65])
      1'b0 : tup_0 = {65 {1'bx}};
      default : tup_0 = x_8;
    endcase
  end

  assign wild_6 = $signed(n);

  assign n = tup_0[64:1];

  assign x_8 = wrM_0[64:0];

  assign result = {result_329
                  ,1'b0
                  ,7'b0001001
                  ,result_108[12:12]
                  ,result_108[11:9]
                  ,result_108[8:6]
                  ,result_108[5:2]
                  ,result_108[1:1]
                  ,result_108[0:0]
                  ,result_126[16:16]
                  ,result_126[12:12]
                  ,result_126[13:13]
                  ,result_126[15:15]
                  ,result_126[14:14]
                  ,1'b0
                  ,1'b0
                  ,1'b0
                  ,1'b0
                  ,1'b0
                  ,1'b0};

  assign MANRST = result[32:32];

  assign TX = result[31:31];

  assign LED = result[30:24];

  assign CLK_OUT = result[23:23];

  assign C1 = result[22:20];

  assign C2 = result[19:17];

  assign DATA = result[16:13];

  assign LAT = result[12:12];

  assign OE = result[11:11];

  assign CS_AG = result[10:10];

  assign CS_M = result[9:9];

  assign CS_ALT = result[8:8];

  assign SDI = result[7:7];

  assign SCK = result[6:6];

  assign INT = result[5:5];

  assign DRDY_M = result[4:4];

  assign PM1_0 = result[3:3];

  assign PM1_2 = result[2:2];

  assign PM1_5 = result[1:1];

  assign PM1_7 = result[0:0];
endmodule

