read_verilog ../top_nocarry.v
hierarchy -top top
proc


equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -noiopad # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
select -assert-count 2 t:CARRY4
select -assert-none t:LUT* t:CARRY4 %% t:* %D


design -load preopt
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -nocarry -noiopad # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
select -assert-none t:CARRY4
select -assert-none t:LUT* %% t:* %D