read_verilog ../top_dsp.v
design -save read

hierarchy -top top
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:DSP48E1
select -assert-none t:DSP48E1 %% t:* %D

design -load read
hierarchy -top top
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -nodsp # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
stat
select -assert-count 15 t:LUT2
select -assert-count 3 t:LUT3
select -assert-count 4 t:LUT4
select -assert-count 5 t:LUT5
select -assert-count 45 t:LUT6
select -assert-count 11 t:MUXCY
select -assert-count 9 t:MUXF7
select -assert-count 3 t:MUXF8
select -assert-count 12 t:XORCY
select -assert-none t:LUT2 t:LUT3 t:LUT4 t:LUT5 t:LUT6 t:MUXCY t:MUXF7 t:MUXF8 t:XORCY %% t:* %D