read_verilog ../cmacc.v
hierarchy -top cmacc
proc
flatten
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)

cd cmacc
#Vivado synthesizes 5 DSP48E1, 32 FDRE, 18 LUT.
stat
select -assert-count 1 t:BUFG
select -assert-count 65 t:FDRE
select -assert-count 3 t:DSP48E1
select -assert-count 18 t:LUT2
select -assert-count 34 t:LUT3
select -assert-count 25 t:MUXCY
select -assert-count 29 t:XORCY

select -assert-none t:BUFG t:FDRE t:DSP48E1 t:LUT2 t:LUT3 t:MUXCY t:XORCY %% t:* %D