read_verilog ../top_counter.v
design -save read

hierarchy -top top
proc
equiv_opt -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
stat
select -assert-count 4 t:CCU2C
select -assert-count 8 t:TRELLIS_FF
select -assert-none t:CCU2C t:TRELLIS_FF %% t:* %D

design -load read
hierarchy -top top
proc
equiv_opt -map +/ecp5/cells_sim.v synth_ecp5 -noccu2 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
stat
select -assert-count 10 t:LUT4
select -assert-count 1 t:PFUMX
select -assert-count 8 t:TRELLIS_FF
select -assert-none t:LUT4 t:PFUMX t:TRELLIS_FF %% t:* %D