read_verilog ../cmacc.v
hierarchy -top cmacc
proc
flatten
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)

cd cmacc
#Vivado synthesizes 5 DSP48E1, 32 FDRE, 18 LUT.
stat
select -assert-count 1 t:BUFG
select -assert-count 77 t:FDRE
select -assert-count 5 t:LUT1
select -assert-count 46 t:LUT2
select -assert-count 25 t:LUT3
select -assert-count 8 t:LUT4
select -assert-count 16 t:LUT5
select -assert-count 85 t:LUT6
select -assert-count 54 t:MUXCY
select -assert-count 8 t:MUXF7
select -assert-count 2 t:MUXF8
select -assert-count 22 t:SRL16E
select -assert-count 62 t:XORCY

select -assert-none t:BUFG t:FDRE t:LUT1 t:LUT2 t:LUT3 t:LUT4 t:LUT5 t:LUT6 t:MUXCY t:MUXF7 t:MUXF8 t:SRL16E t:XORCY %% t:* %D