/* Generated by Yosys 0.8+96 (git sha1 2d73e1b6, gcc 8.2.0-7ubuntu1 -Og -fPIC) */

(* cells_not_processed =  1  *)
(* src = "top.v:1" *)
module FSM(clk, rst, en, ls, rs, stop, busy, finish);
  (* src = "top.v:71" *)
  wire [2:0] _00_;
  (* src = "top.v:19" *)
  (* unused_bits = "0 1 2 3" *)
  wire [3:0] _01_;
  (* src = "top.v:80" *)
  wire [31:0] _02_;
  (* src = "top.v:43" *)
  wire _03_;
  (* src = "top.v:76" *)
  wire _04_;
  (* src = "top.v:85" *)
  wire _05_;
  (* src = "top.v:85" *)
  wire _06_;
  (* src = "top.v:87" *)
  wire _07_;
  (* src = "top.v:89" *)
  wire _08_;
  (* src = "top.v:89" *)
  wire _09_;
  (* src = "top.v:39" *)
  wire _10_;
  (* src = "top.v:53" *)
  wire _11_;
  (* src = "top.v:60" *)
  wire _12_;
  (* src = "top.v:85" *)
  wire _13_;
  (* src = "top.v:89" *)
  wire _14_;
  wire [2:0] _15_;
  wire [2:0] _16_;
  (* unused_bits = "0" *)
  wire _17_;
  (* unused_bits = "0" *)
  wire _18_;
  (* unused_bits = "0" *)
  wire _19_;
  (* unused_bits = "0" *)
  wire _20_;
  (* unused_bits = "0" *)
  wire _21_;
  (* unused_bits = "0" *)
  wire _22_;
  (* unused_bits = "0" *)
  wire _23_;
  (* unused_bits = "0" *)
  wire _24_;
  (* unused_bits = "0" *)
  wire _25_;
  (* unused_bits = "0" *)
  wire _26_;
  (* unused_bits = "0" *)
  wire _27_;
  (* unused_bits = "0" *)
  wire _28_;
  (* unused_bits = "0" *)
  wire _29_;
  (* unused_bits = "0" *)
  wire _30_;
  (* unused_bits = "0" *)
  wire _31_;
  (* unused_bits = "0" *)
  wire _32_;
  (* unused_bits = "0" *)
  wire _33_;
  (* unused_bits = "0" *)
  wire _34_;
  (* unused_bits = "0" *)
  wire _35_;
  (* unused_bits = "0" *)
  wire _36_;
  (* src = "top.v:9" *)
  output busy;
  (* src = "top.v:2" *)
  input clk;
  (* src = "top.v:16" *)
  reg [2:0] count;
  (* src = "top.v:4" *)
  input en;
  (* src = "top.v:10" *)
  output finish;
  (* src = "top.v:5" *)
  input ls;
  (* src = "top.v:6" *)
  input rs;
  (* src = "top.v:3" *)
  input rst;
  (* src = "top.v:8" *)
  output stop;
  assign _02_ = count + (* src = "top.v:80" *) 32'd1;
  assign _03_ = ~ (* src = "top.v:43" *) ls;
  (* fsm_encoding = "auto" *)
  (* src = "top.v:14" *)
  \$fsm  #(
    .ARST_POLARITY(1'h1),
    .CLK_POLARITY(1'h1),
    .CTRL_IN_WIDTH(32'd7),
    .CTRL_OUT_WIDTH(32'd6),
    .NAME("\\st"),
    .STATE_BITS(32'd14),
    .STATE_NUM(32'd14),
    .STATE_NUM_LOG2(32'd4),
    .STATE_RST(32'd0),
    .STATE_TABLE(196'b1zzzzzzzzzzzzzz1zzzzzzzzzzzzzz1zzzzzzzzzzzzzz1zzzzzzzzzzzzzz1zzzzzzzzzzzzzz1zzzzzzzzzzzzzz1zzzzzzzzzzzzzz1zzzzzzzzzzzzzz1zzzzzzzzzzzzzz1zzzzzzzzzzzzzz1zzzzzzzzzzzzzz1zzzzzzzzzzzzzz1zzzzzzzzzzzzzz1),
    .TRANS_NUM(32'd34),
    .TRANS_TABLE(714'b1101zzz0z0z10100000001101zzz1z0z10010000001101zzzzz1z00000000001100zzzzz0z00110000001100zzzzz1z00000000001011zzzzz0z01110000011011zzzzz1z00000000011010zzzzz0z10101000001010zzzzz1z000010000010010zzzz0z101100000010011zzzz0z01100000001001zzzzz1z00000000001000zzzzz0z00010010001000zzzzz1z00000010000111zzzzz0z01000000000111zzzzz1z00000000000110zzzz10z11010000000110zzzz00z00010000000110zzzzz1z00000000000101zzzzz0111000000000101zzzzz0000100000000101zzzzz1z00000000000100zz1zz0z10110000000100zz0zz0z00100000000100zzzzz1z00000000000011zzzzz0z01010000100011zzzzz1z00000000100010z0zzz0z10010100000010z1zzz0z01010100000010zzzzz1z00000100000001zzzzz0z10000001000001zzzzz1z00000001000000zzzzz0z01110000000000zzzzz1z0000000000)
  ) _39_ (
    .ARST(1'h0),
    .CLK(clk),
    .CTRL_IN({ _03_, _10_, rs, _11_, ls, rst, _12_ }),
    .CTRL_OUT({ _07_, _04_, _09_, _08_, _06_, _05_ })
  );
  assign _10_ = count > (* src = "top.v:39" *) 32'd7;
  assign _11_ = ls && (* src = "top.v:53" *) rs;
  assign _12_ = ls || (* src = "top.v:60" *) rs;
  assign _13_ = _05_ || (* src = "top.v:85" *) _06_;
  assign _14_ = _08_ || (* src = "top.v:89" *) _09_;
  always @(posedge clk)
      count <= _00_;
  assign _15_ = _10_ ? (* src = "top.v:77" *) 3'h0 : _02_[2:0];
  assign _16_ = _04_ ? (* src = "top.v:76" *) _15_ : count;
  assign _00_ = rst ? (* src = "top.v:72" *) _16_ : 3'h0;
  assign stop = _13_ ? (* src = "top.v:85" *) 1'h1 : 1'h0;
  assign finish = _07_ ? (* src = "top.v:87" *) 1'h1 : 1'h0;
  assign busy = _14_ ? (* src = "top.v:89" *) 1'h1 : 1'h0;
endmodule

(* cells_not_processed =  1  *)
(* src = "top.v:94" *)
module top(clk, rst, en, a, b, s, bs, f);
  (* src = "top.v:98" *)
  input a;
  (* src = "top.v:99" *)
  input b;
  (* src = "top.v:101" *)
  output bs;
  (* src = "top.v:95" *)
  input clk;
  (* src = "top.v:97" *)
  input en;
  (* src = "top.v:102" *)
  output f;
  (* src = "top.v:96" *)
  input rst;
  (* src = "top.v:100" *)
  output s;
  (* module_not_derived = 32'd1 *)
  (* src = "top.v:105" *)
  FSM u_FSM (
    .busy(bs),
    .clk(clk),
    .en(en),
    .finish(f),
    .ls(a),
    .rs(b),
    .rst(rst),
    .stop(s)
  );
endmodule