library(top) {

 /* unit attributes */
  time_unit : "1ns";
  voltage_unit : "1V";
  current_unit : "1uA";
  pulling_resistance_unit : "1kohm";
  leakage_power_unit : "1nW";
  capacitive_load_unit(1,pf);

/* positive edge triggered D flip-flop with active low reset */
cell(top) {
area : 972;
cell_footprint : "latch";
latch(IQ, IQN) {
enable : "CLK" ;
data_in : "D" ;
preset : "CLR" ;}
pin(D) {
direction : input;
capacitance : 0.0225;
timing() { /* hold time constraint for a rising transition on G */
timing_type : hold_falling;
rise_constraint(scalar) { values("-0.298"); }
fall_constraint(scalar) { values("-0.298"); }
related_pin : "CLK";
}
timing() { /* setup time constraint for a rising transition on G */
timing_type : setup_falling;
rise_constraint(scalar) { values("0.018"); }
fall_constraint(scalar) { values("0.018"); }
related_pin : "CLK";
}
} /* end of pin D */
pin ( CLK ) {
direction : input;
capacitance : 0.0585;
clock : true;
} /* end of pin CLK */
pin ( CLR ) {
direction : input;
capacitance : 0.0135;
} /* end of pin CLR */
pin ( Q ) {
direction : output;
function : "IQ";
timing () { /* propagation delay from rising edge of CLK to Q */
timing_type : falling_edge;
cell_rise(lu5x5) { values( "0.018" );}
rise_transition(lu5x5) { values( "0.018" );}
cell_fall(lu5x5) { values( "0.018" );}
fall_transition(lu5x5) { values( "0.018" );}
related_pin : "CLK";
} /* end of Q timing related to CLK */
timing () { /* propagation delay from falling edge of clear to Q=0 */
timing_type : preset;
timing_sense : negative_unate;
cell_fall(lu5x5) { values( "0.018" );}
fall_transition(lu5x5) { values( "0.018" );}
related_pin : "CLR";
} /* end of Q timing related to CLR */
} /* end of pin Q */
} /* end of cell dff */

}