read_verilog ../rams_sp_rf.v
hierarchy -top rams_sp_rf
proc
memory -nomap
equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
memory
opt -full

# TODO
#equiv_opt -run prove: -assert null
miter -equiv -flatten -make_assert -make_outputs gold gate miter
#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter

design -load postopt
cd rams_sp_rf
stat
#Vivado synthesizes 1 RAMB18E1.
select -assert-count 1 t:BUFG
select -assert-count 1 t:LUT2
select -assert-count 1 t:RAMB18E1

select -assert-none t:BUFG t:LUT2 t:RAMB18E1 %% t:* %D