read_verilog ../latches.v
proc
hierarchy -top latches
flatten
synth_xilinx
#Vivado synthesizes 1 BUFG, 8 LDCE.
select -assert-count 2 t:LUT2
select -assert-count 1 t:LDCE
#select -assert-none t:LUT2 t:LDCE %% t:* %D